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use assert false instead of term

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This commit is contained in:
lizzie 2026-03-30 08:21:08 +00:00
parent 88d0ea45e8
commit a305deeb36
74 changed files with 430 additions and 430 deletions
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4
src/dynarmic/src/dynarmic/backend/arm64/abi.h
View file

@ -33,7 +33,7 @@ constexpr auto Rscratch0() {
} else if constexpr (bitsize == 64) {
return Xscratch0;
} else {
return Xscratch0; //std::terminate(); //unreachable
return Xscratch0; //assert(false && "unreachable");
}
}
@ -44,7 +44,7 @@ constexpr auto Rscratch1() {
} else if constexpr (bitsize == 64) {
return Xscratch1;
} else {
return Xscratch1; //std::terminate(); //unreachable
return Xscratch1; //assert(false && "unreachable");
}
}

6
src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp
View file

@ -260,7 +260,7 @@ void AddressSpace::Link(EmittedBlockInfo& block_info) {
c.BL(prelude_info.get_ticks_remaining);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -294,7 +294,7 @@ void AddressSpace::LinkBlockLinks(const CodePtr entry_point, const CodePtr targe
}
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
}
@ -346,7 +346,7 @@ FakeCall AddressSpace::FastmemCallback(u64 host_pc) {
fail:
fmt::print("dynarmic: Segfault happened within JITted code at host_pc = {:016x}\n"
"Segfault wasn't at a fastmem patch location!\n", host_pc);
std::terminate(); //unreachable
assert(false && "unreachable");
}
} // namespace Dynarmic::Backend::Arm64

8
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp
View file

@ -112,7 +112,7 @@ void EmitIR<IR::Opcode::GetNZCVFromOp>(oaknut::CodeGenerator& code, EmitContext&
break;
}
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -142,7 +142,7 @@ void EmitIR<IR::Opcode::GetNZFromOp>(oaknut::CodeGenerator& code, EmitContext& c
break;
}
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -239,7 +239,7 @@ EmittedBlockInfo EmitArm64(oaknut::CodeGenerator& code, IR::Block block, const E
#undef A32OPC
#undef A64OPC
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
reg_alloc.UpdateAllUses();
@ -283,7 +283,7 @@ void EmitBlockLinkRelocation(oaknut::CodeGenerator& code, EmitContext& ctx, cons
code.NOP();
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}

10
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp
View file

@ -24,7 +24,7 @@ using namespace oaknut::util;
static void EmitCoprocessorException() {
// TODO: Raise coproc except
std::terminate(); //unreachable
assert(false && "unreachable");
}
static void CallCoprocCallback(oaknut::CodeGenerator& code, EmitContext& ctx, A32::Coprocessor::Callback callback, IR::Inst* inst = nullptr, std::optional<Argument::copyable_reference> arg0 = {}, std::optional<Argument::copyable_reference> arg1 = {}) {
@ -107,7 +107,7 @@ void EmitIR<IR::Opcode::A32CoprocSendOneWord>(oaknut::CodeGenerator& code, EmitC
return;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -151,7 +151,7 @@ void EmitIR<IR::Opcode::A32CoprocSendTwoWords>(oaknut::CodeGenerator& code, Emit
return;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -193,7 +193,7 @@ void EmitIR<IR::Opcode::A32CoprocGetOneWord>(oaknut::CodeGenerator& code, EmitCo
return;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -235,7 +235,7 @@ void EmitIR<IR::Opcode::A32CoprocGetTwoWords>(oaknut::CodeGenerator& code, EmitC
return;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>

2
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_cryptography.cpp
View file

@ -120,7 +120,7 @@ void EmitIR<IR::Opcode::SM4AccessSubstitutionBox>(oaknut::CodeGenerator& code, E
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>

44
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp
View file

@ -126,10 +126,10 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
code.FCVTAS(Rto, Vfrom);
break;
case FP::RoundingMode::ToOdd:
std::terminate(); //unreachable
assert(false && "unreachable");
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
} else {
switch (rounding_mode) {
@ -149,10 +149,10 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
code.FCVTAU(Rto, Vfrom);
break;
case FP::RoundingMode::ToOdd:
std::terminate(); //unreachable
assert(false && "unreachable");
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
}
@ -189,7 +189,7 @@ void EmitIR<IR::Opcode::FPAbs16>(oaknut::CodeGenerator& code, EmitContext& ctx,
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -316,7 +316,7 @@ void EmitIR<IR::Opcode::FPMulAdd16>(oaknut::CodeGenerator& code, EmitContext& ct
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -334,7 +334,7 @@ void EmitIR<IR::Opcode::FPMulSub16>(oaknut::CodeGenerator& code, EmitContext& ct
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -362,7 +362,7 @@ void EmitIR<IR::Opcode::FPNeg16>(oaknut::CodeGenerator& code, EmitContext& ctx,
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -380,7 +380,7 @@ void EmitIR<IR::Opcode::FPRecipEstimate16>(oaknut::CodeGenerator& code, EmitCont
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -398,7 +398,7 @@ void EmitIR<IR::Opcode::FPRecipExponent16>(oaknut::CodeGenerator& code, EmitCont
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -416,7 +416,7 @@ void EmitIR<IR::Opcode::FPRecipStepFused16>(oaknut::CodeGenerator& code, EmitCon
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -434,7 +434,7 @@ void EmitIR<IR::Opcode::FPRoundInt16>(oaknut::CodeGenerator& code, EmitContext&
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -469,7 +469,7 @@ void EmitIR<IR::Opcode::FPRoundInt32>(oaknut::CodeGenerator& code, EmitContext&
code.FRINTA(Sresult, Soperand);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
}
@ -506,7 +506,7 @@ void EmitIR<IR::Opcode::FPRoundInt64>(oaknut::CodeGenerator& code, EmitContext&
code.FRINTA(Dresult, Doperand);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
}
@ -516,7 +516,7 @@ void EmitIR<IR::Opcode::FPRSqrtEstimate16>(oaknut::CodeGenerator& code, EmitCont
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -534,7 +534,7 @@ void EmitIR<IR::Opcode::FPRSqrtStepFused16>(oaknut::CodeGenerator& code, EmitCon
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -648,7 +648,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS16>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -656,7 +656,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS32>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -664,7 +664,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS64>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -672,7 +672,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU16>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -680,7 +680,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU32>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -688,7 +688,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU64>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>

22
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp
View file

@ -48,7 +48,7 @@ LinkTarget ReadMemoryLinkTarget(size_t bitsize) {
case 128:
return LinkTarget::ReadMemory128;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
LinkTarget WriteMemoryLinkTarget(size_t bitsize) {
@ -64,7 +64,7 @@ LinkTarget WriteMemoryLinkTarget(size_t bitsize) {
case 128:
return LinkTarget::WriteMemory128;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
LinkTarget WrappedReadMemoryLinkTarget(size_t bitsize) {
@ -80,7 +80,7 @@ LinkTarget WrappedReadMemoryLinkTarget(size_t bitsize) {
case 128:
return LinkTarget::WrappedReadMemory128;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
LinkTarget WrappedWriteMemoryLinkTarget(size_t bitsize) {
@ -96,7 +96,7 @@ LinkTarget WrappedWriteMemoryLinkTarget(size_t bitsize) {
case 128:
return LinkTarget::WrappedWriteMemory128;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
LinkTarget ExclusiveReadMemoryLinkTarget(size_t bitsize) {
@ -112,7 +112,7 @@ LinkTarget ExclusiveReadMemoryLinkTarget(size_t bitsize) {
case 128:
return LinkTarget::ExclusiveReadMemory128;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
LinkTarget ExclusiveWriteMemoryLinkTarget(size_t bitsize) {
@ -128,7 +128,7 @@ LinkTarget ExclusiveWriteMemoryLinkTarget(size_t bitsize) {
case 128:
return LinkTarget::ExclusiveWriteMemory128;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<std::size_t bitsize>
@ -235,7 +235,7 @@ void EmitDetectMisalignedVAddr(oaknut::CodeGenerator& code, EmitContext& ctx, oa
case 128:
return 0b1111;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}();
@ -318,7 +318,7 @@ CodePtr EmitMemoryLdr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
code.DMB(oaknut::BarrierOp::ISH);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
} else {
fastmem_location = code.xptr<CodePtr>();
@ -340,7 +340,7 @@ CodePtr EmitMemoryLdr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
code.LDR(oaknut::QReg{value_idx}, Xbase, Roffset, index_ext);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -379,7 +379,7 @@ CodePtr EmitMemoryStr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
code.DMB(oaknut::BarrierOp::ISH);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
} else {
fastmem_location = code.xptr<CodePtr>();
@ -401,7 +401,7 @@ CodePtr EmitMemoryStr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
code.STR(oaknut::QReg{value_idx}, Xbase, Roffset, index_ext);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}

36
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp
View file

@ -134,7 +134,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd8>(oaknut::CodeGenerator& code, EmitCo
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -142,7 +142,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd16>(oaknut::CodeGenerator& code, EmitC
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -150,7 +150,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd32>(oaknut::CodeGenerator& code, EmitC
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -158,7 +158,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd64>(oaknut::CodeGenerator& code, EmitC
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -166,7 +166,7 @@ void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh16>(oaknut::Cod
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -174,7 +174,7 @@ void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh32>(oaknut::Cod
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -182,7 +182,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub8>(oaknut::CodeGenerator& code, EmitCo
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -190,7 +190,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub16>(oaknut::CodeGenerator& code, EmitC
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -198,7 +198,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub32>(oaknut::CodeGenerator& code, EmitC
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -206,7 +206,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub64>(oaknut::CodeGenerator& code, EmitC
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -214,7 +214,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd8>(oaknut::CodeGenerator& code, Emit
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -222,7 +222,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd16>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -230,7 +230,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd32>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -238,7 +238,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd64>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -246,7 +246,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub8>(oaknut::CodeGenerator& code, Emit
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -254,7 +254,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub16>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -262,7 +262,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub32>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -270,7 +270,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub64>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
} // namespace Dynarmic::Backend::Arm64

46
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp
View file

@ -45,7 +45,7 @@ static void EmitTwoOpArranged(oaknut::CodeGenerator& code, EmitContext& ctx, IR:
} else if constexpr (size == 64) {
emit(Qresult->D2(), Qoperand->D2());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
});
}
@ -68,7 +68,7 @@ static void EmitTwoOpArrangedWiden(oaknut::CodeGenerator& code, EmitContext& ctx
} else if constexpr (size == 32) {
emit(Qresult->D2(), Qoperand->toD().S2());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
});
}
@ -83,7 +83,7 @@ static void EmitTwoOpArrangedNarrow(oaknut::CodeGenerator& code, EmitContext& ct
} else if constexpr (size == 64) {
emit(Qresult->toD().S2(), Qoperand->D2());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
});
}
@ -106,7 +106,7 @@ static void EmitTwoOpArrangedPairWiden(oaknut::CodeGenerator& code, EmitContext&
} else if constexpr (size == 32) {
emit(Qresult->D2(), Qoperand->S4());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
});
}
@ -121,7 +121,7 @@ static void EmitTwoOpArrangedLower(oaknut::CodeGenerator& code, EmitContext& ctx
} else if constexpr (size == 32) {
emit(Qresult->toD().S2(), Qoperand->toD().S2());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
});
}
@ -149,7 +149,7 @@ static void EmitThreeOpArranged(oaknut::CodeGenerator& code, EmitContext& ctx, I
} else if constexpr (size == 64) {
emit(Qresult->D2(), Qa->D2(), Qb->D2());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
});
}
@ -174,7 +174,7 @@ static void EmitThreeOpArrangedWiden(oaknut::CodeGenerator& code, EmitContext& c
} else if constexpr (size == 64) {
emit(Qresult->Q1(), Qa->toD().D1(), Qb->toD().D1());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
});
}
@ -197,7 +197,7 @@ static void EmitThreeOpArrangedLower(oaknut::CodeGenerator& code, EmitContext& c
} else if constexpr (size == 32) {
emit(Qresult->toD().S2(), Qa->toD().S2(), Qb->toD().S2());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
});
}
@ -219,7 +219,7 @@ static void EmitSaturatedAccumulate(oaknut::CodeGenerator&, EmitContext& ctx, IR
} else if constexpr (size == 64) {
emit(Qaccumulator->D2(), Qoperand->D2());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -240,7 +240,7 @@ static void EmitImmShift(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* ins
} else if constexpr (size == 64) {
emit(Qresult->D2(), Qoperand->D2(), shift_amount);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -268,7 +268,7 @@ static void EmitReduce(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst,
} else if constexpr (size == 64) {
emit(Vresult, Qoperand->D2());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -640,7 +640,7 @@ void EmitIR<IR::Opcode::VectorEqual128>(oaknut::CodeGenerator& code, EmitContext
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -869,7 +869,7 @@ void EmitIR<IR::Opcode::VectorMaxS64>(oaknut::CodeGenerator& code, EmitContext&
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -892,7 +892,7 @@ void EmitIR<IR::Opcode::VectorMaxU64>(oaknut::CodeGenerator& code, EmitContext&
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -915,7 +915,7 @@ void EmitIR<IR::Opcode::VectorMinS64>(oaknut::CodeGenerator& code, EmitContext&
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -938,7 +938,7 @@ void EmitIR<IR::Opcode::VectorMinU64>(oaknut::CodeGenerator& code, EmitContext&
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -1385,7 +1385,7 @@ void EmitIR<IR::Opcode::VectorSignExtend64>(oaknut::CodeGenerator& code, EmitCon
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -1408,7 +1408,7 @@ void EmitIR<IR::Opcode::VectorSignedMultiply16>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -1416,7 +1416,7 @@ void EmitIR<IR::Opcode::VectorSignedMultiply32>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -1668,7 +1668,7 @@ void EmitIR<IR::Opcode::VectorTableLookup64>(oaknut::CodeGenerator& code, EmitCo
}
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -1732,7 +1732,7 @@ void EmitIR<IR::Opcode::VectorTableLookup128>(oaknut::CodeGenerator& code, EmitC
}
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -1780,7 +1780,7 @@ void EmitIR<IR::Opcode::VectorUnsignedMultiply16>(oaknut::CodeGenerator& code, E
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -1788,7 +1788,7 @@ void EmitIR<IR::Opcode::VectorUnsignedMultiply32>(oaknut::CodeGenerator& code, E
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>

44
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
View file

@ -75,7 +75,7 @@ static void EmitTwoOpArranged(oaknut::CodeGenerator& code, EmitContext& ctx, IR:
} else if constexpr (size == 64) {
emit(Qresult->D2(), Qa->D2());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
});
}
@ -103,7 +103,7 @@ static void EmitThreeOpArranged(oaknut::CodeGenerator& code, EmitContext& ctx, I
} else if constexpr (size == 64) {
emit(Qresult->D2(), Qa->D2(), Qb->D2());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
});
}
@ -126,7 +126,7 @@ static void EmitFMA(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* ins
} else if constexpr (size == 64) {
emit(Qresult->D2(), Qm->D2(), Qn->D2());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
});
}
@ -148,7 +148,7 @@ static void EmitFromFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Ins
} else if constexpr (size == 64) {
emit(Qto->D2(), Qfrom->D2(), fbits);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
});
}
@ -170,7 +170,7 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
} else if constexpr (fsize == 64) {
return Qto->D2();
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}();
auto Vfrom = [&] {
@ -179,7 +179,7 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
} else if constexpr (fsize == 64) {
return Qfrom->D2();
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}();
@ -218,10 +218,10 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
code.FCVTAS(Vto, Vfrom);
break;
case FP::RoundingMode::ToOdd:
std::terminate(); //unreachable
assert(false && "unreachable");
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
} else {
switch (rounding_mode) {
@ -241,10 +241,10 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
code.FCVTAU(Vto, Vfrom);
break;
case FP::RoundingMode::ToOdd:
std::terminate(); //unreachable
assert(false && "unreachable");
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
}
@ -329,7 +329,7 @@ void EmitIR<IR::Opcode::FPVectorEqual16>(oaknut::CodeGenerator& code, EmitContex
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -454,7 +454,7 @@ void EmitIR<IR::Opcode::FPVectorMulAdd16>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -482,7 +482,7 @@ void EmitIR<IR::Opcode::FPVectorNeg16>(oaknut::CodeGenerator& code, EmitContext&
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -527,7 +527,7 @@ void EmitIR<IR::Opcode::FPVectorRecipEstimate16>(oaknut::CodeGenerator& code, Em
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -545,7 +545,7 @@ void EmitIR<IR::Opcode::FPVectorRecipStepFused16>(oaknut::CodeGenerator& code, E
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -599,7 +599,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt16>(oaknut::CodeGenerator& code, EmitCon
: EmitTwoOpFallback<3>(code, ctx, inst, EmitIRVectorRoundInt16Thunk<FPT, FP::RoundingMode::ToNearest_TieAwayFromZero, false>);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -637,7 +637,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt32>(oaknut::CodeGenerator& code, EmitCon
code.FRINTA(Qresult->S4(), Qoperand->S4());
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
});
@ -677,7 +677,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt64>(oaknut::CodeGenerator& code, EmitCon
code.FRINTA(Qresult->D2(), Qoperand->D2());
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
});
@ -688,7 +688,7 @@ void EmitIR<IR::Opcode::FPVectorRSqrtEstimate16>(oaknut::CodeGenerator& code, Em
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -706,7 +706,7 @@ void EmitIR<IR::Opcode::FPVectorRSqrtStepFused16>(oaknut::CodeGenerator& code, E
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -761,7 +761,7 @@ void EmitIR<IR::Opcode::FPVectorToSignedFixed16>(oaknut::CodeGenerator& code, Em
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>
@ -779,7 +779,7 @@ void EmitIR<IR::Opcode::FPVectorToUnsignedFixed16>(oaknut::CodeGenerator& code,
(void)code;
(void)ctx;
(void)inst;
std::terminate(); //unreachable
assert(false && "unreachable");
}
template<>

2
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_saturation.cpp
View file

@ -41,7 +41,7 @@ static void Emit(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst, EmitF
} else if constexpr (size == 64) {
emit(Qresult->D2(), Qa->D2(), Qb->D2());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}

22
src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp
View file

@ -298,7 +298,7 @@ int RegAlloc::GenerateImmediate(const IR::Value& value) {
return 0;
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -325,7 +325,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
switch (current_location->kind) {
case HostLoc::Kind::Gpr:
std::terminate(); //unreachable //logic error
assert(false && "unreachable"); //logic error
case HostLoc::Kind::Fpr:
code.FMOV(oaknut::XReg{new_location_index}, oaknut::DReg{current_location->index});
// assert size fits
@ -350,7 +350,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
code.FMOV(oaknut::DReg{new_location_index}, oaknut::XReg{current_location->index});
break;
case HostLoc::Kind::Fpr:
std::terminate(); //unreachable //logic error
assert(false && "unreachable"); //logic error
case HostLoc::Kind::Spill:
code.LDR(oaknut::QReg{new_location_index}, SP, spill_offset + current_location->index * spill_slot_size);
break;
@ -363,9 +363,9 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
fprs[new_location_index].realized = true;
return new_location_index;
} else if constexpr (required_kind == HostLoc::Kind::Flags) {
std::terminate(); //unreachable //A simple read from flags is likely a logic error
assert(false && "unreachable"); //A simple read from flags is likely a logic error
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -389,7 +389,7 @@ int RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
flags.SetupLocation(value);
return 0;
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -409,7 +409,7 @@ int RegAlloc::RealizeReadWriteImpl(const IR::Value& read_value, const IR::Inst*
} else if constexpr (kind == HostLoc::Kind::Flags) {
assert(false && "Incorrect function for ReadWrite of flags");
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -479,7 +479,7 @@ void RegAlloc::ReadWriteFlags(Argument& read, IR::Inst* write) {
code.LDR(Wscratch0, SP, spill_offset + current_location->index * spill_slot_size);
code.MSR(oaknut::SystemReg::NZCV, Xscratch0);
} else {
std::terminate(); //unreachable //assert(false && "Invalid current location for flags");
assert(false && "unreachable"); //assert(false && "Invalid current location for flags");
}
if (write) {
@ -551,7 +551,7 @@ void RegAlloc::LoadCopyInto(const IR::Value& value, oaknut::QReg reg) {
code.LDR(reg, SP, spill_offset + current_location->index * spill_slot_size);
break;
case HostLoc::Kind::Flags:
std::terminate(); //unreachable //assert(false && "Moving from flags into fprs is not currently supported");
assert(false && "unreachable"); //assert(false && "Moving from flags into fprs is not currently supported");
}
}
@ -584,7 +584,7 @@ HostLocInfo& RegAlloc::ValueInfo(HostLoc host_loc) {
case HostLoc::Kind::Spill:
return spills[static_cast<size_t>(host_loc.index)];
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
@ -599,7 +599,7 @@ HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
} else if (const auto iter = std::find_if(spills.begin(), spills.end(), contains_value); iter != spills.end()) {
return *iter;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
} // namespace Dynarmic::Backend::Arm64

14
src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h
View file

@ -186,7 +186,7 @@ public:
} else if constexpr (size == 32) {
return ReadW(arg);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -203,7 +203,7 @@ public:
} else if constexpr (size == 8) {
return ReadB(arg);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -225,7 +225,7 @@ public:
} else if constexpr (size == 32) {
return WriteW(inst);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -242,7 +242,7 @@ public:
} else if constexpr (size == 8) {
return WriteB(inst);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -262,7 +262,7 @@ public:
} else if constexpr (size == 32) {
return ReadWriteW(arg, inst);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -279,7 +279,7 @@ public:
} else if constexpr (size == 8) {
return ReadWriteB(arg, inst);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -370,7 +370,7 @@ void RAReg<T>::Realize() {
reg = T{reg_alloc.RealizeReadWriteImpl<kind>(read_value, write_value)};
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}

2
src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp
View file

@ -128,7 +128,7 @@ void A32AddressSpace::Link(EmittedBlockInfo& block_info) {
break;
}
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
}

2
src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp
View file

@ -110,7 +110,7 @@ struct Jit::Impl final {
private:
void RequestCacheInvalidation() {
// std::terminate(); //unreachable
// assert(false && "unreachable");
invalidate_entire_cache = false;
invalid_cache_ranges.clear();

2
src/dynarmic/src/dynarmic/backend/riscv64/a64_interface.cpp
View file

@ -160,7 +160,7 @@ struct Jit::Impl final {
private:
void RequestCacheInvalidation() {
// std::terminate(); //unreachable
// assert(false && "unreachable");
invalidate_entire_cache = false;
invalid_cache_ranges.clear();
}

2
src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp
View file

@ -143,7 +143,7 @@ EmittedBlockInfo EmitRV64(biscuit::Assembler& as, IR::Block block, const EmitCon
#undef A32OPC
#undef A64OPC
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}

2
src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp
View file

@ -108,7 +108,7 @@ void EmitA32Cond(biscuit::Assembler& as, EmitContext&, IR::Cond cond, biscuit::L
as.BNEZ(Xscratch0, label);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}

14
src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp
View file

@ -163,7 +163,7 @@ u32 RegAlloc::GenerateImmediate(const IR::Value& value) {
} else if constexpr (kind == HostLoc::Kind::Fpr) {
std::terminate(); //unimplemented
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
return 0;
}
@ -191,7 +191,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
switch (current_location->kind) {
case HostLoc::Kind::Gpr:
std::terminate(); //unreachable //logic error
assert(false && "unreachable"); //logic error
case HostLoc::Kind::Fpr:
as.FMV_X_D(biscuit::GPR(new_location_index), biscuit::FPR{current_location->index});
// assert size fits
@ -213,7 +213,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
as.FMV_D_X(biscuit::FPR{new_location_index}, biscuit::GPR(current_location->index));
break;
case HostLoc::Kind::Fpr:
std::terminate(); //unreachable //logic error
assert(false && "unreachable"); //logic error
case HostLoc::Kind::Spill:
as.FLD(biscuit::FPR{new_location_index}, spill_offset + current_location->index * spill_slot_size, biscuit::sp);
break;
@ -223,7 +223,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
fprs[new_location_index].realized = true;
return new_location_index;
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -250,7 +250,7 @@ u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
setup_location(fprs[new_location_index]);
return new_location_index;
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -322,7 +322,7 @@ HostLocInfo& RegAlloc::ValueInfo(HostLoc host_loc) {
case HostLoc::Kind::Spill:
return spills[size_t(host_loc.index)];
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
@ -336,7 +336,7 @@ HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
} else if (const auto iter = std::find_if(spills.begin(), spills.end(), contains_value); iter != gprs.end()) {
return *iter;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
} // namespace Dynarmic::Backend::RV64

16
src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp
View file

@ -56,7 +56,7 @@ static Xbyak::Address MJitStateExtReg(A32::ExtReg reg) {
const size_t index = size_t(reg) - size_t(A32::ExtReg::Q0);
return xword[BlockOfCode::ABI_JIT_PTR + offsetof(A32JitState, ExtReg) + 2 * sizeof(u64) * index];
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
A32EmitContext::A32EmitContext(const A32::UserConfig& conf, RegAlloc& reg_alloc, IR::Block& block)
@ -135,7 +135,7 @@ A32EmitX64::BlockDescriptor A32EmitX64::Emit(IR::Block& block) {
#undef A32OPC
#undef A64OPC
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
reg_alloc.EndOfAllocScope();
#ifndef NDEBUG
@ -833,7 +833,7 @@ void A32EmitX64::EmitA32SetFpscrNZCV(A32EmitContext& ctx, IR::Inst* inst) {
}
static void EmitCoprocessorException() {
std::terminate(); //unreachable
assert(false && "unreachable");
}
static void CallCoprocCallback(BlockOfCode& code, RegAlloc& reg_alloc, A32::Coprocessor::Callback callback, IR::Inst* inst = nullptr, std::optional<Argument::copyable_reference> arg0 = {}, std::optional<Argument::copyable_reference> arg1 = {}) {
@ -909,7 +909,7 @@ void A32EmitX64::EmitA32CoprocSendOneWord(A32EmitContext& ctx, IR::Inst* inst) {
return;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
void A32EmitX64::EmitA32CoprocSendTwoWords(A32EmitContext& ctx, IR::Inst* inst) {
@ -952,7 +952,7 @@ void A32EmitX64::EmitA32CoprocSendTwoWords(A32EmitContext& ctx, IR::Inst* inst)
return;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
void A32EmitX64::EmitA32CoprocGetOneWord(A32EmitContext& ctx, IR::Inst* inst) {
@ -995,7 +995,7 @@ void A32EmitX64::EmitA32CoprocGetOneWord(A32EmitContext& ctx, IR::Inst* inst) {
return;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
void A32EmitX64::EmitA32CoprocGetTwoWords(A32EmitContext& ctx, IR::Inst* inst) {
@ -1040,7 +1040,7 @@ void A32EmitX64::EmitA32CoprocGetTwoWords(A32EmitContext& ctx, IR::Inst* inst) {
return;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
void A32EmitX64::EmitA32CoprocLoadWords(A32EmitContext& ctx, IR::Inst* inst) {
@ -1216,7 +1216,7 @@ void EmitTerminalImpl(A32EmitX64& e, IR::Term::CheckHalt terminal, IR::LocationD
}
void EmitTerminalImpl(A32EmitX64&, IR::Term::Invalid, IR::LocationDescriptor, bool) {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}

4
src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp
View file

@ -123,7 +123,7 @@ A64EmitX64::BlockDescriptor A64EmitX64::Emit(IR::Block& block) noexcept {
#undef A32OPC
#undef A64OPC
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
opcode_branch:
(this->*opcode_handlers[size_t(opcode)])(ctx, &inst);
@ -710,7 +710,7 @@ void EmitTerminalImpl(A64EmitX64& e, IR::Term::CheckHalt terminal, IR::LocationD
}
void EmitTerminalImpl(A64EmitX64&, IR::Term::Invalid, IR::LocationDescriptor, bool) {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}

2
src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp
View file

@ -515,7 +515,7 @@ void BlockOfCode::LoadRequiredFlagsForCondFromRax(IR::Cond cond) {
case IR::Cond::NV:
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}

2
src/dynarmic/src/dynarmic/backend/x64/block_of_code.h
View file

@ -120,7 +120,7 @@ public:
case 64:
return;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}

8
src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp
View file

@ -53,7 +53,7 @@ std::optional<EmitX64::BlockDescriptor> EmitX64::GetBasicBlock(IR::LocationDescr
}
void EmitX64::EmitInvalid(EmitContext&, IR::Inst* inst) {
std::terminate(); //unreachable
assert(false && "unreachable");
}
void EmitX64::EmitVoid(EmitContext&, IR::Inst*) {
@ -193,7 +193,7 @@ void EmitX64::EmitGetNZFromOp(EmitContext& ctx, IR::Inst* inst) {
case IR::Type::U64:
return 64;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}();
@ -224,7 +224,7 @@ void EmitX64::EmitGetNZCVFromOp(EmitContext& ctx, IR::Inst* inst) {
case IR::Type::U64:
return 64;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}();
@ -339,7 +339,7 @@ Xbyak::Label EmitX64::EmitCond(IR::Cond cond) {
code.jle(pass);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
return pass;
}

2
src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp
View file

@ -194,7 +194,7 @@ static void EmitConditionalSelect(BlockOfCode& code, EmitContext& ctx, IR::Inst*
code.mov(else_, then_);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
ctx.reg_alloc.DefineValue(code, inst, else_);

4
src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp
View file

@ -659,7 +659,7 @@ static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, bo
FCODE(ucomis)(result, result);
code.jp(*fallback, code.T_NEAR);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
if (ctx.FPCR().DN()) {
ForceToDefaultNaN<fsize>(code, result);
@ -1079,7 +1079,7 @@ static void EmitFPRound(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, siz
case 64: code.CallFunction(EmitFPRoundThunk<u64>); break;
case 32: code.CallFunction(EmitFPRoundThunk<u32>); break;
case 16: code.CallFunction(EmitFPRoundThunk<u16>); break;
default: std::terminate(); //unreachable
default: assert(false && "unreachable");
}
}
}

4
src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc
View file

@ -43,7 +43,7 @@ FakeCall AxxEmitX64::FastmemCallback(u64 rip_) {
}
fmt::print("dynarmic: Segfault happened within JITted code at rip = {:016x}\n"
"Segfault wasn't at a fastmem patch location!\n", rip_);
std::terminate(); //unreachable //("iter != fastmem_patch_info.end()");
assert(false && "unreachable"); //("iter != fastmem_patch_info.end()");
}
template<std::size_t bitsize, auto callback>
@ -489,7 +489,7 @@ void AxxEmitX64::EmitExclusiveWriteMemoryInline(AxxEmitContext& ctx, IR::Inst* i
code.cmpxchg16b(ptr[dest_ptr]);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
code.setnz(status.cvt8());

10
src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h
View file

@ -45,7 +45,7 @@ void EmitDetectMisalignedVAddr(BlockOfCode& code, EmitContext& ctx, size_t bitsi
case 128:
return 0b1111;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}();
@ -247,7 +247,7 @@ const void* EmitReadMemoryMov(BlockOfCode& code, int value_idx, const Xbyak::Reg
}
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
return fastmem_location;
} else {
@ -269,7 +269,7 @@ const void* EmitReadMemoryMov(BlockOfCode& code, int value_idx, const Xbyak::Reg
code.movups(Xbyak::Xmm(value_idx), xword[addr]);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
return fastmem_location;
}
@ -315,7 +315,7 @@ const void* EmitWriteMemoryMov(BlockOfCode& code, const Xbyak::RegExp& addr, int
break;
}
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
return fastmem_location;
} else {
@ -337,7 +337,7 @@ const void* EmitWriteMemoryMov(BlockOfCode& code, const Xbyak::RegExp& addr, int
code.movups(xword[addr], Xbyak::Xmm(value_idx));
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
return fastmem_location;
}

26
src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp
View file

@ -2280,27 +2280,27 @@ void EmitX64::EmitVectorMultiply64(EmitContext& ctx, IR::Inst* inst) {
}
void EmitX64::EmitVectorMultiplySignedWiden8(EmitContext&, IR::Inst*) {
std::terminate(); //unreachable
assert(false && "unreachable");
}
void EmitX64::EmitVectorMultiplySignedWiden16(EmitContext&, IR::Inst*) {
std::terminate(); //unreachable
assert(false && "unreachable");
}
void EmitX64::EmitVectorMultiplySignedWiden32(EmitContext&, IR::Inst*) {
std::terminate(); //unreachable
assert(false && "unreachable");
}
void EmitX64::EmitVectorMultiplyUnsignedWiden8(EmitContext&, IR::Inst*) {
std::terminate(); //unreachable
assert(false && "unreachable");
}
void EmitX64::EmitVectorMultiplyUnsignedWiden16(EmitContext&, IR::Inst*) {
std::terminate(); //unreachable
assert(false && "unreachable");
}
void EmitX64::EmitVectorMultiplyUnsignedWiden32(EmitContext&, IR::Inst*) {
std::terminate(); //unreachable
assert(false && "unreachable");
}
void EmitX64::EmitVectorNarrow16(EmitContext& ctx, IR::Inst* inst) {
@ -3869,7 +3869,7 @@ static void EmitVectorSignedAbsoluteDifference(size_t esize, EmitContext& ctx, I
code.psubd(x, tmp);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
} else {
code.movdqa(tmp, y);
@ -3888,7 +3888,7 @@ static void EmitVectorSignedAbsoluteDifference(size_t esize, EmitContext& ctx, I
code.psubd(x, tmp);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -4092,7 +4092,7 @@ static void EmitVectorSignedSaturatedAbs(size_t esize, BlockOfCode& code, EmitCo
break;
}
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
code.or_(code.dword[code.ABI_JIT_PTR + code.GetJitStateInfo().offsetof_fpsr_qc], bit);
@ -4542,7 +4542,7 @@ static void EmitVectorSignedSaturatedNarrowToSigned(size_t original_esize, Block
code.punpcklwd(reconstructed, sign);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
const Xbyak::Reg32 bit = ctx.reg_alloc.ScratchGpr(code).cvt32();
@ -4597,7 +4597,7 @@ static void EmitVectorSignedSaturatedNarrowToUnsigned(size_t original_esize, Blo
code.punpcklwd(reconstructed, xmm0);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
const Xbyak::Reg32 bit = ctx.reg_alloc.ScratchGpr(code).cvt32();
@ -4661,7 +4661,7 @@ static void EmitVectorSignedSaturatedNeg(size_t esize, BlockOfCode& code, EmitCo
case 64:
return code.Const(xword, 0x8000000000000000, 0x8000000000000000);
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}();
@ -4957,7 +4957,7 @@ void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) {
break;
}
default:
std::terminate(); //unreachable
assert(false && "unreachable");
break;
}
return;

12
src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp
View file

@ -265,7 +265,7 @@ struct PairedIndexer {
case 1:
return std::make_tuple(b[2 * i], b[2 * i + 1]);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
};
@ -288,7 +288,7 @@ struct PairedLowerIndexer {
}
return std::make_tuple(0, 0);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
};
@ -681,7 +681,7 @@ void EmitX64::EmitFPVectorFromHalf32(EmitContext& ctx, IR::Inst* inst) {
EmitTwoOpFallback<2>(code, ctx, inst, EmitFPVectorFromHalf32Thunk<FP::RoundingMode::ToNearest_TieAwayFromZero>);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
}
@ -1679,7 +1679,7 @@ void EmitFPVectorRoundInt(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
case FP::RoundingMode::TowardsPlusInfinity: return 0b10;
case FP::RoundingMode::TowardsMinusInfinity: return 0b01;
case FP::RoundingMode::TowardsZero: return 0b11;
default: std::terminate(); //unreachable
default: assert(false && "unreachable");
}
}();
@ -1720,7 +1720,7 @@ void EmitFPVectorRoundInt(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
: EmitTwoOpFallback<3>(code, ctx, inst, EmitFPVectorRoundIntThunk<FPT, FP::RoundingMode::ToNearest_TieAwayFromZero, false>);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -1988,7 +1988,7 @@ void EmitX64::EmitFPVectorToHalf32(EmitContext& ctx, IR::Inst* inst) {
EmitTwoOpFallback<2>(code, ctx, inst, EmitFPVectorToHalf32Thunk<FP::RoundingMode::ToNearest_TieAwayFromZero>);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
}

2
src/dynarmic/src/dynarmic/backend/x64/hostloc.h
View file

@ -106,7 +106,7 @@ constexpr size_t HostLocBitWidth(HostLoc loc) {
return 128;
else if (HostLocIsFlag(loc))
return 1;
std::terminate(); //unreachable
assert(false && "unreachable");
}
constexpr std::bitset<32> BuildRegSet(std::initializer_list<HostLoc> regs) {

4
src/dynarmic/src/dynarmic/backend/x64/oparg.h
View file

@ -30,7 +30,7 @@ struct OpArg {
case Type::Reg:
return inner_reg;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
void setBit(int bits) {
@ -57,7 +57,7 @@ struct OpArg {
return;
}
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
private:

14
src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp
View file

@ -47,7 +47,7 @@ static inline size_t GetBitWidth(const IR::Type type) noexcept {
return 32; // TODO: Update to 16 when flags optimization is done
default:
// A32REG A32EXTREG A64REG A64VEC COPROCINFO COND VOID TABLE ACCTYPE OPAQUE
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -375,7 +375,7 @@ void RegAlloc::HostCall(
case IR::Type::U64:
break; //no op
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
}
@ -548,7 +548,7 @@ HostLoc RegAlloc::FindFreeSpill(bool is_xmm) const noexcept {
for (size_t i = size_t(HostLoc::FirstSpill); i < hostloc_info.size(); ++i)
if (const auto loc = HostLoc(i); LocInfo(loc).IsEmpty())
return loc;
std::terminate(); //unreachable
assert(false && "unreachable");
}
#define MAYBE_AVX(OPCODE, ...) \
@ -576,7 +576,7 @@ HostLoc RegAlloc::LoadImmediate(BlockOfCode& code, IR::Value imm, HostLoc host_l
MAYBE_AVX(movaps, reg, code.Const(code.xword, imm_value));
}
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
return host_loc;
}
@ -630,7 +630,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
MAYBE_AVX(movss, HostLocToXmm(to), spill_addr);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
} else if (HostLocIsSpill(to) && HostLocIsXMM(from)) {
const Xbyak::Address spill_addr = spill_xmm_to_op(to);
@ -648,7 +648,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
MAYBE_AVX(movss, spill_addr, HostLocToXmm(from));
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
} else if (HostLocIsGPR(to) && HostLocIsSpill(from)) {
assert(bit_width != 128);
@ -665,7 +665,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
code.mov(Xbyak::util::dword[spill_to_op_arg_helper(to, reserved_stack_space)], HostLocToReg64(from).cvt32());
}
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
#undef MAYBE_AVX

4
src/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp
View file

@ -55,7 +55,7 @@ FPT FPRecipEstimate(FPT op, FPCR fpcr, FPSR& fpsr) {
case RoundingMode::TowardsZero:
return false;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}();
@ -86,7 +86,7 @@ FPT FPRecipEstimate(FPT op, FPCR fpcr, FPSR& fpsr) {
result_exponent++;
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}

2
src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp
View file

@ -72,7 +72,7 @@ u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr)
round_up = error > ResidualError::Half || (error == ResidualError::Half && !mcl::bit::most_significant_bit(int_result));
break;
case RoundingMode::ToOdd:
std::terminate(); //unreachable
assert(false && "unreachable");
}
if (round_up) {

2
src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp
View file

@ -70,7 +70,7 @@ u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, Rou
round_up = error > ResidualError::Half || (error == ResidualError::Half && !mcl::bit::most_significant_bit(int_result));
break;
case RoundingMode::ToOdd:
std::terminate(); //unreachable
assert(false && "unreachable");
}
if (round_up) {

2
src/dynarmic/src/dynarmic/common/fp/process_exception.cpp
View file

@ -42,7 +42,7 @@ void FPProcessException(FPExc exception, FPCR fpcr, FPSR& fpsr) {
fpsr.IDC(true);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}

10
src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp
View file

@ -35,7 +35,7 @@ size_t IREmitter::ArchVersion() const {
case ArchVersion::v8:
return 8;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
u32 IREmitter::PC() const {
@ -60,7 +60,7 @@ IR::U32U64 IREmitter::GetExtendedRegister(ExtReg reg) {
return Inst<IR::U32U64>(Opcode::A32GetExtendedRegister32, IR::Value(reg));
else if (A32::IsDoubleExtReg(reg))
return Inst<IR::U32U64>(Opcode::A32GetExtendedRegister64, IR::Value(reg));
std::terminate(); //unreachable
assert(false && "unreachable");
}
IR::U128 IREmitter::GetVector(ExtReg reg) {
@ -79,7 +79,7 @@ void IREmitter::SetExtendedRegister(const ExtReg reg, const IR::U32U64& value) {
} else if (A32::IsDoubleExtReg(reg)) {
Inst(Opcode::A32SetExtendedRegister64, IR::Value(reg), value);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -236,7 +236,7 @@ IR::UAny IREmitter::ReadMemory(size_t bitsize, const IR::U32& vaddr, IR::AccType
case 64:
return ReadMemory64(vaddr, acc_type);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
IR::U8 IREmitter::ReadMemory8(const IR::U32& vaddr, IR::AccType acc_type) {
@ -294,7 +294,7 @@ void IREmitter::WriteMemory(size_t bitsize, const IR::U32& vaddr, const IR::UAny
case 64:
return WriteMemory64(vaddr, value, acc_type);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
void IREmitter::WriteMemory8(const IR::U32& vaddr, const IR::U8& value, IR::AccType acc_type) {

2
src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_crc32.cpp
View file

@ -77,7 +77,7 @@ bool CRC32Variant(TranslatorVisitor& v, Cond cond, Imm<2> sz, Reg n, Reg d, Reg
}
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
v.ir.SetRegister(d, result);

6
src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp
View file

@ -66,7 +66,7 @@ IR::UAny TranslatorVisitor::I(size_t bitsize, u64 value) {
case 64:
return ir.Imm64(value);
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -92,7 +92,7 @@ IR::ResultAndCarry<IR::U32> TranslatorVisitor::EmitImmShift(IR::U32 value, Shift
return ir.RotateRightExtended(value, carry_in);
}
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
IR::ResultAndCarry<IR::U32> TranslatorVisitor::EmitRegShift(IR::U32 value, ShiftType type, IR::U8 amount, IR::U1 carry_in) {
@ -106,7 +106,7 @@ IR::ResultAndCarry<IR::U32> TranslatorVisitor::EmitRegShift(IR::U32 value, Shift
case ShiftType::ROR:
return ir.RotateRight(value, amount, carry_in);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
} // namespace Dynarmic::A32

2
src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h
View file

@ -77,7 +77,7 @@ struct TranslatorVisitor final {
case 0b11:
return mcl::bit::replicate_element<u8, u32>(imm8);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
return {imm32, carry_in};
}

2
src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp
View file

@ -72,7 +72,7 @@ std::optional<std::tuple<size_t, size_t, size_t>> DecodeType(Imm<4> type, size_t
}
return std::tuple<size_t, size_t, size_t>{4, 1, 2};
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
} // namespace

2
src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp
View file

@ -110,7 +110,7 @@ bool TranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c, Imm
return bic();
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
} // namespace Dynarmic::A32

2
src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
View file

@ -172,7 +172,7 @@ bool TranslatorVisitor::asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool
return ir.VectorReverseElementsInHalfGroups(esize, reg_m);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
ir.SetVector(d, result);

2
src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
View file

@ -133,7 +133,7 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, bool D, size_t imm6, size_t Vd, b
assert(signedness == Signedness::Signed);
return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
v.ir.SetVector(d, result);

6
src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp
View file

@ -870,11 +870,11 @@ bool TranslatorVisitor::arm_LDMIB(Cond cond, bool W, Reg n, RegList list) {
}
bool TranslatorVisitor::arm_LDM_usr() {
std::terminate(); //unreachable
assert(false && "unreachable");
}
bool TranslatorVisitor::arm_LDM_eret() {
std::terminate(); //unreachable
assert(false && "unreachable");
}
static bool STMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::U32 start_address, IR::U32 writeback_address) {
@ -955,7 +955,7 @@ bool TranslatorVisitor::arm_STMIB(Cond cond, bool W, Reg n, RegList list) {
}
bool TranslatorVisitor::arm_STM_usr() {
std::terminate(); //unreachable
assert(false && "unreachable");
}
} // namespace Dynarmic::A32

6
src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp
View file

@ -15,7 +15,7 @@ namespace Dynarmic::A32 {
// CPS<effect> <iflags>{, #<mode>}
// CPS #<mode>
bool TranslatorVisitor::arm_CPS() {
std::terminate(); //unreachable
assert(false && "unreachable");
}
// MRS<c> <Rd>, <spec_reg>
@ -107,7 +107,7 @@ bool TranslatorVisitor::arm_MSR_reg(Cond cond, unsigned mask, Reg n) {
// RFE{<amode>} <Rn>{!}
bool TranslatorVisitor::arm_RFE() {
std::terminate(); //unreachable
assert(false && "unreachable");
}
// SETEND <endian_specifier>
@ -118,7 +118,7 @@ bool TranslatorVisitor::arm_SETEND(bool E) {
// SRS{<amode>} SP{!}, #<mode>
bool TranslatorVisitor::arm_SRS() {
std::terminate(); //unreachable
assert(false && "unreachable");
}
} // namespace Dynarmic::A32

8
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp
View file

@ -30,7 +30,7 @@ bool TranslatorVisitor::SCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg
case 64:
return ir.FPSignedFixedToDouble(intval, fracbits, rounding_mode);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
V_scalar(*fltsize, Vd, fltval);
@ -57,7 +57,7 @@ bool TranslatorVisitor::UCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg
case 64:
return ir.FPUnsignedFixedToDouble(intval, fracbits, rounding_mode);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
V_scalar(*fltsize, Vd, fltval);
@ -82,7 +82,7 @@ bool TranslatorVisitor::FCVTZS_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec
} else if (intsize == 64) {
intval = ir.FPToFixedS64(fltval, fracbits, FP::RoundingMode::TowardsZero);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
X(intsize, Rd, intval);
@ -107,7 +107,7 @@ bool TranslatorVisitor::FCVTZU_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec
} else if (intsize == 64) {
intval = ir.FPToFixedU64(fltval, fracbits, FP::RoundingMode::TowardsZero);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
X(intsize, Rd, intval);

10
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp
View file

@ -26,7 +26,7 @@ bool TranslatorVisitor::SCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
} else if (*fltsize == 64) {
fltval = ir.FPSignedFixedToDouble(intval, 0, ir.current_location->FPCR().RMode());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
V_scalar(*fltsize, Vd, fltval);
@ -49,7 +49,7 @@ bool TranslatorVisitor::UCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
} else if (*fltsize == 64) {
fltval = ir.FPUnsignedFixedToDouble(intval, 0, ir.current_location->FPCR().RMode());
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
V_scalar(*fltsize, Vd, fltval);
@ -78,7 +78,7 @@ bool TranslatorVisitor::FMOV_float_gen(bool sf, Imm<2> type, Imm<1> rmode_0, Imm
case 0b11:
return 16;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}();
@ -130,7 +130,7 @@ static bool FloaingPointConvertSignedInteger(TranslatorVisitor& v, bool sf, Imm<
} else if (intsize == 64) {
intval = v.ir.FPToFixedS64(fltval, 0, rounding_mode);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
v.X(intsize, Rd, intval);
@ -152,7 +152,7 @@ static bool FloaingPointConvertUnsignedInteger(TranslatorVisitor& v, bool sf, Im
} else if (intsize == 64) {
intval = v.ir.FPToFixedU64(fltval, 0, rounding_mode);
} else {
std::terminate(); //unreachable
assert(false && "unreachable");
}
v.X(intsize, Rd, intval);

32
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp
View file

@ -19,7 +19,7 @@ bool TranslatorVisitor::UnpredictableInstruction() {
}
bool TranslatorVisitor::DecodeError() {
std::terminate(); //unreachable
assert(false && "unreachable");
}
bool TranslatorVisitor::ReservedValue() {
@ -72,7 +72,7 @@ IR::UAny TranslatorVisitor::I(size_t bitsize, u64 value) {
case 64:
return ir.Imm64(value);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
IR::UAny TranslatorVisitor::X(size_t bitsize, Reg reg) {
@ -86,7 +86,7 @@ IR::UAny TranslatorVisitor::X(size_t bitsize, Reg reg) {
case 64:
return ir.GetX(reg);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
void TranslatorVisitor::X(size_t bitsize, Reg reg, IR::U32U64 value) {
@ -98,7 +98,7 @@ void TranslatorVisitor::X(size_t bitsize, Reg reg, IR::U32U64 value) {
ir.SetX(reg, value);
return;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
IR::U32U64 TranslatorVisitor::SP(size_t bitsize) {
@ -108,7 +108,7 @@ IR::U32U64 TranslatorVisitor::SP(size_t bitsize) {
case 64:
return ir.GetSP();
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
void TranslatorVisitor::SP(size_t bitsize, IR::U32U64 value) {
@ -120,7 +120,7 @@ void TranslatorVisitor::SP(size_t bitsize, IR::U32U64 value) {
ir.SetSP(value);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -133,7 +133,7 @@ IR::U128 TranslatorVisitor::V(size_t bitsize, Vec vec) {
case 128:
return ir.GetQ(vec);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
void TranslatorVisitor::V(size_t bitsize, Vec vec, IR::U128 value) {
@ -149,7 +149,7 @@ void TranslatorVisitor::V(size_t bitsize, Vec vec, IR::U128 value) {
ir.SetQ(vec, value);
return;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
IR::UAnyU128 TranslatorVisitor::V_scalar(size_t bitsize, Vec vec) {
@ -223,7 +223,7 @@ IR::UAnyU128 TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccTyp
case 16:
return ir.ReadMemory128(address, acc_type);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccType acc_type, IR::UAnyU128 value) {
@ -244,7 +244,7 @@ void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccType acc_ty
ir.WriteMemory128(address, value, acc_type);
return;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
IR::UAnyU128 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::AccType acc_type) {
@ -260,7 +260,7 @@ IR::UAnyU128 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, I
case 16:
return ir.ExclusiveReadMemory128(address, acc_type);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
IR::U32 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::AccType acc_type, IR::UAnyU128 value) {
@ -276,7 +276,7 @@ IR::U32 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::Ac
case 16:
return ir.ExclusiveWriteMemory128(address, value, acc_type);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
IR::U32U64 TranslatorVisitor::SignExtend(IR::UAny value, size_t to_size) {
@ -286,7 +286,7 @@ IR::U32U64 TranslatorVisitor::SignExtend(IR::UAny value, size_t to_size) {
case 64:
return ir.SignExtendToLong(value);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
IR::U32U64 TranslatorVisitor::ZeroExtend(IR::UAny value, size_t to_size) {
@ -296,7 +296,7 @@ IR::U32U64 TranslatorVisitor::ZeroExtend(IR::UAny value, size_t to_size) {
case 64:
return ir.ZeroExtendToLong(value);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
IR::U32U64 TranslatorVisitor::ShiftReg(size_t bitsize, Reg reg, Imm<2> shift, IR::U8 amount) {
@ -311,7 +311,7 @@ IR::U32U64 TranslatorVisitor::ShiftReg(size_t bitsize, Reg reg, Imm<2> shift, IR
case 0b11:
return ir.RotateRight(result, amount);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, u8 shift) {
@ -374,7 +374,7 @@ IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option,
break;
}
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
if (len < bitsize) {

4
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp
View file

@ -72,7 +72,7 @@ static bool ExclusiveSharedDecodeAndOperation(TranslatorVisitor& v, bool pair, s
break;
}
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
return true;
@ -175,7 +175,7 @@ static bool OrderedSharedDecodeAndOperation(TranslatorVisitor& v, size_t size, b
break;
}
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
return true;

2
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp
View file

@ -153,7 +153,7 @@ static bool LoadStoreSIMD(TranslatorVisitor& v, bool wback, bool postindex, size
}
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
if (wback) {

4
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp
View file

@ -66,7 +66,7 @@ bool TranslatorVisitor::STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback,
break;
}
case IR::MemOp::PREFETCH:
std::terminate(); //unreachable
assert(false && "unreachable");
}
if (wback) {
@ -136,7 +136,7 @@ bool TranslatorVisitor::STP_LDP_fpsimd(Imm<2> opc, bool not_postindex, bool wbac
break;
}
case IR::MemOp::PREFETCH:
std::terminate(); //unreachable
assert(false && "unreachable");
}
if (wback) {

4
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp
View file

@ -70,7 +70,7 @@ static bool RegSharedDecodeAndOperation(TranslatorVisitor& v, size_t scale, u8 s
// TODO: Prefetch
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
return true;
@ -128,7 +128,7 @@ static bool VecSharedDecodeAndOperation(TranslatorVisitor& v, size_t scale, u8 s
break;
}
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
return true;

4
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp
View file

@ -81,7 +81,7 @@ bool FPMinMax(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, MinMaxOpera
case MinMaxOperation::MinNumeric:
return v.ir.FPMinNumeric(lhs, rhs);
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
};
@ -144,7 +144,7 @@ bool ScalarMinMax(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, Sca
return v.ir.MinUnsigned(a, b);
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
};

2
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp
View file

@ -95,7 +95,7 @@ bool TranslatorVisitor::MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<
return bic();
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
bool TranslatorVisitor::FMOV_2(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd) {

2
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp
View file

@ -34,7 +34,7 @@ bool FPPairwiseMinMax(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, MinMaxOpera
case MinMaxOperationSSPW::MinNumeric:
return v.ir.FPMinNumeric(element1, element2);
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}();

4
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
View file

@ -201,7 +201,7 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn,
assert(SignednessSSSBI == SignednessSSSBI::Signed);
return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
const IR::UAny segment = v.ir.VectorGetElement(esize, result, 0);
@ -251,7 +251,7 @@ bool ScalarFPConvertWithRound(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Ve
: v.ir.FPUnsignedFixedToSingle(operand, fbits, rounding_mode);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
v.V_scalar(esize, Vd, result);

2
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp
View file

@ -120,7 +120,7 @@ bool ScalarFPCompareRegister(TranslatorVisitor& v, bool sz, Vec Vm, Vec Vn, Vec
v.ir.FPVectorAbs(esize, operand2));
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
v.V_scalar(datasize, Vd, v.ir.VectorGetElement(esize, result, 0));

2
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
View file

@ -43,7 +43,7 @@ bool ScalarFPCompareAgainstZero(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, C
return v.ir.FPVectorGreater(esize, zero, operand);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
v.V_scalar(datasize, Vd, v.ir.VectorGetElement(esize, result, 0));

4
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
View file

@ -130,7 +130,7 @@ bool ShiftRightNarrowingSSBI(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> i
assert(SignednessSSBI == SignednessSSBI::Signed);
return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
v.Vpart(64, Vd, part, result);
@ -222,7 +222,7 @@ bool ConvertFloat(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn
? v.ir.FPVectorToSignedFixed(esize, operand, fbits, rounding_mode)
: v.ir.FPVectorToUnsignedFixed(esize, operand, fbits, rounding_mode);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
v.V(datasize, Vd, result);

6
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp
View file

@ -161,7 +161,7 @@ bool FPCompareRegister(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Ve
v.ir.FPVectorAbs(esize, operand2));
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
v.V(datasize, Vd, result);
@ -198,7 +198,7 @@ bool VectorMinMaxOperationSTS(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm,
return v.ir.VectorMinUnsigned(esize, operand1, operand2);
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}();
@ -275,7 +275,7 @@ bool PairedMinMaxOperationSTS(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm,
return Q ? v.ir.VectorPairedMinUnsigned(esize, operand1, operand2) : v.ir.VectorPairedMinUnsignedLower(esize, operand1, operand2);
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}();

2
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp
View file

@ -77,7 +77,7 @@ bool FPCompareAgainstZero(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd,
return v.ir.FPVectorGreater(esize, zero, operand);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
v.V(datasize, Vd, result);

4
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp
View file

@ -83,7 +83,7 @@ bool FPMultiplyByElement(TranslatorVisitor& v, bool Q, bool sz, Imm<1> L, Imm<1>
case ExtraBehaviorSVXIE::Subtract:
return v.ir.FPVectorMulAdd(esize, operand3, v.ir.FPVectorNeg(esize, operand1), operand2);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
v.V(datasize, Vd, result);
return true;
@ -113,7 +113,7 @@ bool FPMultiplyByElementHalfPrecision(TranslatorVisitor& v, bool Q, Imm<1> L, Im
case ExtraBehaviorSVXIE::Subtract:
return v.ir.FPVectorMulAdd(esize, operand3, v.ir.FPVectorNeg(esize, operand1), operand2);
}
std::terminate(); //unreachable
assert(false && "unreachable");
}();
v.V(datasize, Vd, result);
return true;

4
src/dynarmic/src/dynarmic/frontend/A64/translate/impl/system.cpp
View file

@ -118,7 +118,7 @@ bool TranslatorVisitor::MSR_reg(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, I
default:
break;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
bool TranslatorVisitor::MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
@ -158,7 +158,7 @@ bool TranslatorVisitor::MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3
X(64, Rt, ir.GetTPIDRRO());
return true;
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
} // namespace Dynarmic::A64

2
src/dynarmic/src/dynarmic/frontend/imm.cpp
View file

@ -64,7 +64,7 @@ u64 AdvSIMDExpandImm(bool op, Imm<4> cmode, Imm<8> imm8) {
return result;
}
}
std::terminate(); //unreachable
assert(false && "unreachable");
}
} // namespace Dynarmic

286
src/dynarmic/src/dynarmic/ir/ir_emitter.h
View file

File diff suppressed because it is too large Load diff

4
src/dynarmic/src/dynarmic/ir/value.cpp
View file

@ -220,7 +220,7 @@ s64 Value::GetImmediateAsS64() const {
case IR::Type::U64:
return s64(GetU64());
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}
@ -238,7 +238,7 @@ u64 Value::GetImmediateAsU64() const {
case IR::Type::U64:
return u64(GetU64());
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
}

2
src/dynarmic/tests/A32/fuzz_arm.cpp
View file

@ -273,7 +273,7 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
} else if (bitstring.substr(0, 8) == "11110100") {
bitstring.replace(0, 8, "11111001");
} else {
std::terminate(); //unreachable // "Unhandled ASIMD instruction: {} {}", fn, bs);
assert(false && "unreachable"); // "Unhandled ASIMD instruction: {} {}", fn, bs);
}
if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
invalid.emplace_back(InstructionGenerator{bitstring.c_str()});

8
src/dynarmic/tests/A32/testenv.h
View file

@ -98,11 +98,11 @@ public:
}
void CallSVC(std::uint32_t swi) override {
std::terminate(); //unreachable //assert(false && "CallSVC({})", swi);
assert(false && "unreachable"); //assert(false && "CallSVC({})", swi);
}
void ExceptionRaised(u32 pc, Dynarmic::A32::Exception /*exception*/) override {
std::terminate(); //unreachable //assert(false && "ExceptionRaised({:08x}) code = {:08x}", pc, *MemoryReadCode(pc));
assert(false && "unreachable"); //assert(false && "ExceptionRaised({:08x}) code = {:08x}", pc, *MemoryReadCode(pc));
}
void AddTicks(std::uint64_t ticks) override {
@ -187,11 +187,11 @@ public:
}
void CallSVC(std::uint32_t swi) override {
std::terminate(); //unreachable //assert(false && "CallSVC({})", swi);
assert(false && "unreachable"); //assert(false && "CallSVC({})", swi);
}
void ExceptionRaised(std::uint32_t pc, Dynarmic::A32::Exception) override {
std::terminate(); //unreachable //assert(false && "ExceptionRaised({:016x})", pc);
assert(false && "unreachable"); //assert(false && "ExceptionRaised({:016x})", pc);
}
void AddTicks(std::uint64_t ticks) override {

8
src/dynarmic/tests/A64/testenv.h
View file

@ -106,11 +106,11 @@ public:
}
void CallSVC(std::uint32_t swi) override {
std::terminate(); //unreachable //assert(false && "CallSVC({})", swi);
assert(false && "unreachable"); //assert(false && "CallSVC({})", swi);
}
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception /*exception*/) override {
std::terminate(); //unreachable //assert(false && "ExceptionRaised({:016x})", pc);
assert(false && "unreachable"); //assert(false && "ExceptionRaised({:016x})", pc);
}
void AddTicks(std::uint64_t ticks) override {
@ -205,11 +205,11 @@ public:
}
void CallSVC(std::uint32_t swi) override {
std::terminate(); //unreachable //assert(false && "CallSVC({})", swi);
assert(false && "unreachable"); //assert(false && "CallSVC({})", swi);
}
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception) override {
std::terminate(); //unreachable //assert(false && "ExceptionRaised({:016x})", pc);
assert(false && "unreachable"); //assert(false && "ExceptionRaised({:016x})", pc);
}
void AddTicks(std::uint64_t ticks) override {

2
src/dynarmic/tests/test_generator.cpp
View file

@ -301,7 +301,7 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
} else if (bitstring.substr(0, 8) == "11110100") {
bitstring.replace(0, 8, "11111001");
} else {
std::terminate(); //unreachable // "Unhandled ASIMD instruction: {} {}", fn, bs);
assert(false && "unreachable"); // "Unhandled ASIMD instruction: {} {}", fn, bs);
}
if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
invalid.emplace_back(InstructionGenerator{bitstring.c_str()});

2
src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp
View file

@ -336,7 +336,7 @@ bool A32Unicorn<TestEnvironment>::MemoryWriteHook(uc_engine* /*uc*/, uc_mem_type
this_->testenv.MemoryWrite64(start_address, value);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
return true;

2
src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp
View file

@ -242,7 +242,7 @@ bool A64Unicorn::MemoryWriteHook(uc_engine* /*uc*/, uc_mem_type /*type*/, u64 st
this_->testenv.MemoryWrite64(start_address, value);
break;
default:
std::terminate(); //unreachable
assert(false && "unreachable");
}
return true;