diff --git a/src/dynarmic/src/dynarmic/backend/arm64/abi.h b/src/dynarmic/src/dynarmic/backend/arm64/abi.h
index 40f21c2ee4..8a4e48d81c 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/abi.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/abi.h
@@ -33,7 +33,7 @@ constexpr auto Rscratch0() {
     } else if constexpr (bitsize == 64) {
         return Xscratch0;
     } else {
-        return Xscratch0; //std::terminate(); //unreachable
+        return Xscratch0; //assert(false && "unreachable");
     }
 }
 
@@ -44,7 +44,7 @@ constexpr auto Rscratch1() {
     } else if constexpr (bitsize == 64) {
         return Xscratch1;
     } else {
-        return Xscratch1; //std::terminate(); //unreachable
+        return Xscratch1; //assert(false && "unreachable");
     }
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp b/src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp
index 0cb1ca2b91..5fe542fc66 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp
@@ -260,7 +260,7 @@ void AddressSpace::Link(EmittedBlockInfo& block_info) {
             c.BL(prelude_info.get_ticks_remaining);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -294,7 +294,7 @@ void AddressSpace::LinkBlockLinks(const CodePtr entry_point, const CodePtr targe
             }
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 }
@@ -346,7 +346,7 @@ FakeCall AddressSpace::FastmemCallback(u64 host_pc) {
 fail:
     fmt::print("dynarmic: Segfault happened within JITted code at host_pc = {:016x}\n"
         "Segfault wasn't at a fastmem patch location!\n", host_pc);
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 }  // namespace Dynarmic::Backend::Arm64
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp
index ec719ae350..2a4d3beaf5 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp
@@ -112,7 +112,7 @@ void EmitIR<IR::Opcode::GetNZCVFromOp>(oaknut::CodeGenerator& code, EmitContext&
         break;
     }
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -142,7 +142,7 @@ void EmitIR<IR::Opcode::GetNZFromOp>(oaknut::CodeGenerator& code, EmitContext& c
         break;
     }
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -239,7 +239,7 @@ EmittedBlockInfo EmitArm64(oaknut::CodeGenerator& code, IR::Block block, const E
 #undef A32OPC
 #undef A64OPC
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
 
         reg_alloc.UpdateAllUses();
@@ -283,7 +283,7 @@ void EmitBlockLinkRelocation(oaknut::CodeGenerator& code, EmitContext& ctx, cons
         code.NOP();
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp
index 7d937ba407..d48cf756ab 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp
@@ -24,7 +24,7 @@ using namespace oaknut::util;
 
 static void EmitCoprocessorException() {
     // TODO: Raise coproc except
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 static void CallCoprocCallback(oaknut::CodeGenerator& code, EmitContext& ctx, A32::Coprocessor::Callback callback, IR::Inst* inst = nullptr, std::optional<Argument::copyable_reference> arg0 = {}, std::optional<Argument::copyable_reference> arg1 = {}) {
@@ -107,7 +107,7 @@ void EmitIR<IR::Opcode::A32CoprocSendOneWord>(oaknut::CodeGenerator& code, EmitC
         return;
     }
 
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -151,7 +151,7 @@ void EmitIR<IR::Opcode::A32CoprocSendTwoWords>(oaknut::CodeGenerator& code, Emit
         return;
     }
 
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -193,7 +193,7 @@ void EmitIR<IR::Opcode::A32CoprocGetOneWord>(oaknut::CodeGenerator& code, EmitCo
         return;
     }
 
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -235,7 +235,7 @@ void EmitIR<IR::Opcode::A32CoprocGetTwoWords>(oaknut::CodeGenerator& code, EmitC
         return;
     }
 
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_cryptography.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_cryptography.cpp
index f48549d9a0..8515ed16b5 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_cryptography.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_cryptography.cpp
@@ -120,7 +120,7 @@ void EmitIR<IR::Opcode::SM4AccessSubstitutionBox>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp
index ce9d60d83e..8825d7d247 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp
@@ -126,10 +126,10 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
                 code.FCVTAS(Rto, Vfrom);
                 break;
             case FP::RoundingMode::ToOdd:
-                std::terminate(); //unreachable
+                assert(false && "unreachable");
                 break;
             default:
-                std::terminate(); //unreachable
+                assert(false && "unreachable");
             }
         } else {
             switch (rounding_mode) {
@@ -149,10 +149,10 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
                 code.FCVTAU(Rto, Vfrom);
                 break;
             case FP::RoundingMode::ToOdd:
-                std::terminate(); //unreachable
+                assert(false && "unreachable");
                 break;
             default:
-                std::terminate(); //unreachable
+                assert(false && "unreachable");
             }
         }
     }
@@ -189,7 +189,7 @@ void EmitIR<IR::Opcode::FPAbs16>(oaknut::CodeGenerator& code, EmitContext& ctx,
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -316,7 +316,7 @@ void EmitIR<IR::Opcode::FPMulAdd16>(oaknut::CodeGenerator& code, EmitContext& ct
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -334,7 +334,7 @@ void EmitIR<IR::Opcode::FPMulSub16>(oaknut::CodeGenerator& code, EmitContext& ct
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -362,7 +362,7 @@ void EmitIR<IR::Opcode::FPNeg16>(oaknut::CodeGenerator& code, EmitContext& ctx,
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -380,7 +380,7 @@ void EmitIR<IR::Opcode::FPRecipEstimate16>(oaknut::CodeGenerator& code, EmitCont
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -398,7 +398,7 @@ void EmitIR<IR::Opcode::FPRecipExponent16>(oaknut::CodeGenerator& code, EmitCont
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -416,7 +416,7 @@ void EmitIR<IR::Opcode::FPRecipStepFused16>(oaknut::CodeGenerator& code, EmitCon
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -434,7 +434,7 @@ void EmitIR<IR::Opcode::FPRoundInt16>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -469,7 +469,7 @@ void EmitIR<IR::Opcode::FPRoundInt32>(oaknut::CodeGenerator& code, EmitContext&
             code.FRINTA(Sresult, Soperand);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 }
@@ -506,7 +506,7 @@ void EmitIR<IR::Opcode::FPRoundInt64>(oaknut::CodeGenerator& code, EmitContext&
             code.FRINTA(Dresult, Doperand);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 }
@@ -516,7 +516,7 @@ void EmitIR<IR::Opcode::FPRSqrtEstimate16>(oaknut::CodeGenerator& code, EmitCont
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -534,7 +534,7 @@ void EmitIR<IR::Opcode::FPRSqrtStepFused16>(oaknut::CodeGenerator& code, EmitCon
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -648,7 +648,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS16>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -656,7 +656,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS32>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -664,7 +664,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS64>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -672,7 +672,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU16>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -680,7 +680,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU32>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -688,7 +688,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU64>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp
index b809d30b9e..d0e1a72e65 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp
@@ -48,7 +48,7 @@ LinkTarget ReadMemoryLinkTarget(size_t bitsize) {
     case 128:
         return LinkTarget::ReadMemory128;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 LinkTarget WriteMemoryLinkTarget(size_t bitsize) {
@@ -64,7 +64,7 @@ LinkTarget WriteMemoryLinkTarget(size_t bitsize) {
     case 128:
         return LinkTarget::WriteMemory128;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 LinkTarget WrappedReadMemoryLinkTarget(size_t bitsize) {
@@ -80,7 +80,7 @@ LinkTarget WrappedReadMemoryLinkTarget(size_t bitsize) {
     case 128:
         return LinkTarget::WrappedReadMemory128;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 LinkTarget WrappedWriteMemoryLinkTarget(size_t bitsize) {
@@ -96,7 +96,7 @@ LinkTarget WrappedWriteMemoryLinkTarget(size_t bitsize) {
     case 128:
         return LinkTarget::WrappedWriteMemory128;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 LinkTarget ExclusiveReadMemoryLinkTarget(size_t bitsize) {
@@ -112,7 +112,7 @@ LinkTarget ExclusiveReadMemoryLinkTarget(size_t bitsize) {
     case 128:
         return LinkTarget::ExclusiveReadMemory128;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 LinkTarget ExclusiveWriteMemoryLinkTarget(size_t bitsize) {
@@ -128,7 +128,7 @@ LinkTarget ExclusiveWriteMemoryLinkTarget(size_t bitsize) {
     case 128:
         return LinkTarget::ExclusiveWriteMemory128;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<std::size_t bitsize>
@@ -235,7 +235,7 @@ void EmitDetectMisalignedVAddr(oaknut::CodeGenerator& code, EmitContext& ctx, oa
             case 128:
                 return 0b1111;
             default:
-                std::terminate(); //unreachable
+                assert(false && "unreachable");
             }
         }();
 
@@ -318,7 +318,7 @@ CodePtr EmitMemoryLdr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
             code.DMB(oaknut::BarrierOp::ISH);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     } else {
         fastmem_location = code.xptr<CodePtr>();
@@ -340,7 +340,7 @@ CodePtr EmitMemoryLdr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
             code.LDR(oaknut::QReg{value_idx}, Xbase, Roffset, index_ext);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -379,7 +379,7 @@ CodePtr EmitMemoryStr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
             code.DMB(oaknut::BarrierOp::ISH);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     } else {
         fastmem_location = code.xptr<CodePtr>();
@@ -401,7 +401,7 @@ CodePtr EmitMemoryStr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
             code.STR(oaknut::QReg{value_idx}, Xbase, Roffset, index_ext);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp
index c2338c4e58..d07d7fa7ae 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp
@@ -134,7 +134,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd8>(oaknut::CodeGenerator& code, EmitCo
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -142,7 +142,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd16>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -150,7 +150,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd32>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -158,7 +158,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd64>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -166,7 +166,7 @@ void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh16>(oaknut::Cod
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -174,7 +174,7 @@ void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh32>(oaknut::Cod
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -182,7 +182,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub8>(oaknut::CodeGenerator& code, EmitCo
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -190,7 +190,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub16>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -198,7 +198,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub32>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -206,7 +206,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub64>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -214,7 +214,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd8>(oaknut::CodeGenerator& code, Emit
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -222,7 +222,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd16>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -230,7 +230,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd32>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -238,7 +238,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd64>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -246,7 +246,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub8>(oaknut::CodeGenerator& code, Emit
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -254,7 +254,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub16>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -262,7 +262,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub32>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -270,7 +270,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub64>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 }  // namespace Dynarmic::Backend::Arm64
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp
index 4ffe4c38df..2dd6946e46 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp
@@ -45,7 +45,7 @@ static void EmitTwoOpArranged(oaknut::CodeGenerator& code, EmitContext& ctx, IR:
         } else if constexpr (size == 64) {
             emit(Qresult->D2(), Qoperand->D2());
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     });
 }
@@ -68,7 +68,7 @@ static void EmitTwoOpArrangedWiden(oaknut::CodeGenerator& code, EmitContext& ctx
         } else if constexpr (size == 32) {
             emit(Qresult->D2(), Qoperand->toD().S2());
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     });
 }
@@ -83,7 +83,7 @@ static void EmitTwoOpArrangedNarrow(oaknut::CodeGenerator& code, EmitContext& ct
         } else if constexpr (size == 64) {
             emit(Qresult->toD().S2(), Qoperand->D2());
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     });
 }
@@ -106,7 +106,7 @@ static void EmitTwoOpArrangedPairWiden(oaknut::CodeGenerator& code, EmitContext&
         } else if constexpr (size == 32) {
             emit(Qresult->D2(), Qoperand->S4());
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     });
 }
@@ -121,7 +121,7 @@ static void EmitTwoOpArrangedLower(oaknut::CodeGenerator& code, EmitContext& ctx
         } else if constexpr (size == 32) {
             emit(Qresult->toD().S2(), Qoperand->toD().S2());
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     });
 }
@@ -149,7 +149,7 @@ static void EmitThreeOpArranged(oaknut::CodeGenerator& code, EmitContext& ctx, I
         } else if constexpr (size == 64) {
             emit(Qresult->D2(), Qa->D2(), Qb->D2());
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     });
 }
@@ -174,7 +174,7 @@ static void EmitThreeOpArrangedWiden(oaknut::CodeGenerator& code, EmitContext& c
         } else if constexpr (size == 64) {
             emit(Qresult->Q1(), Qa->toD().D1(), Qb->toD().D1());
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     });
 }
@@ -197,7 +197,7 @@ static void EmitThreeOpArrangedLower(oaknut::CodeGenerator& code, EmitContext& c
         } else if constexpr (size == 32) {
             emit(Qresult->toD().S2(), Qa->toD().S2(), Qb->toD().S2());
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     });
 }
@@ -219,7 +219,7 @@ static void EmitSaturatedAccumulate(oaknut::CodeGenerator&, EmitContext& ctx, IR
     } else if constexpr (size == 64) {
         emit(Qaccumulator->D2(), Qoperand->D2());
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -240,7 +240,7 @@ static void EmitImmShift(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* ins
     } else if constexpr (size == 64) {
         emit(Qresult->D2(), Qoperand->D2(), shift_amount);
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -268,7 +268,7 @@ static void EmitReduce(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst,
     } else if constexpr (size == 64) {
         emit(Vresult, Qoperand->D2());
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -640,7 +640,7 @@ void EmitIR<IR::Opcode::VectorEqual128>(oaknut::CodeGenerator& code, EmitContext
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -869,7 +869,7 @@ void EmitIR<IR::Opcode::VectorMaxS64>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -892,7 +892,7 @@ void EmitIR<IR::Opcode::VectorMaxU64>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -915,7 +915,7 @@ void EmitIR<IR::Opcode::VectorMinS64>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -938,7 +938,7 @@ void EmitIR<IR::Opcode::VectorMinU64>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -1385,7 +1385,7 @@ void EmitIR<IR::Opcode::VectorSignExtend64>(oaknut::CodeGenerator& code, EmitCon
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -1408,7 +1408,7 @@ void EmitIR<IR::Opcode::VectorSignedMultiply16>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -1416,7 +1416,7 @@ void EmitIR<IR::Opcode::VectorSignedMultiply32>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -1668,7 +1668,7 @@ void EmitIR<IR::Opcode::VectorTableLookup64>(oaknut::CodeGenerator& code, EmitCo
         }
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -1732,7 +1732,7 @@ void EmitIR<IR::Opcode::VectorTableLookup128>(oaknut::CodeGenerator& code, EmitC
         }
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -1780,7 +1780,7 @@ void EmitIR<IR::Opcode::VectorUnsignedMultiply16>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -1788,7 +1788,7 @@ void EmitIR<IR::Opcode::VectorUnsignedMultiply32>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
index b12f7460b5..421de4b6cb 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
@@ -75,7 +75,7 @@ static void EmitTwoOpArranged(oaknut::CodeGenerator& code, EmitContext& ctx, IR:
         } else if constexpr (size == 64) {
             emit(Qresult->D2(), Qa->D2());
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     });
 }
@@ -103,7 +103,7 @@ static void EmitThreeOpArranged(oaknut::CodeGenerator& code, EmitContext& ctx, I
         } else if constexpr (size == 64) {
             emit(Qresult->D2(), Qa->D2(), Qb->D2());
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     });
 }
@@ -126,7 +126,7 @@ static void EmitFMA(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* ins
         } else if constexpr (size == 64) {
             emit(Qresult->D2(), Qm->D2(), Qn->D2());
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     });
 }
@@ -148,7 +148,7 @@ static void EmitFromFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Ins
         } else if constexpr (size == 64) {
             emit(Qto->D2(), Qfrom->D2(), fbits);
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     });
 }
@@ -170,7 +170,7 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
         } else if constexpr (fsize == 64) {
             return Qto->D2();
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }();
     auto Vfrom = [&] {
@@ -179,7 +179,7 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
         } else if constexpr (fsize == 64) {
             return Qfrom->D2();
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }();
 
@@ -218,10 +218,10 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
                     code.FCVTAS(Vto, Vfrom);
                     break;
                 case FP::RoundingMode::ToOdd:
-                    std::terminate(); //unreachable
+                    assert(false && "unreachable");
                     break;
                 default:
-                    std::terminate(); //unreachable
+                    assert(false && "unreachable");
                 }
             } else {
                 switch (rounding_mode) {
@@ -241,10 +241,10 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
                     code.FCVTAU(Vto, Vfrom);
                     break;
                 case FP::RoundingMode::ToOdd:
-                    std::terminate(); //unreachable
+                    assert(false && "unreachable");
                     break;
                 default:
-                    std::terminate(); //unreachable
+                    assert(false && "unreachable");
                 }
             }
         }
@@ -329,7 +329,7 @@ void EmitIR<IR::Opcode::FPVectorEqual16>(oaknut::CodeGenerator& code, EmitContex
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -454,7 +454,7 @@ void EmitIR<IR::Opcode::FPVectorMulAdd16>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -482,7 +482,7 @@ void EmitIR<IR::Opcode::FPVectorNeg16>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -527,7 +527,7 @@ void EmitIR<IR::Opcode::FPVectorRecipEstimate16>(oaknut::CodeGenerator& code, Em
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -545,7 +545,7 @@ void EmitIR<IR::Opcode::FPVectorRecipStepFused16>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -599,7 +599,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt16>(oaknut::CodeGenerator& code, EmitCon
             : EmitTwoOpFallback<3>(code, ctx, inst, EmitIRVectorRoundInt16Thunk<FPT, FP::RoundingMode::ToNearest_TieAwayFromZero, false>);
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -637,7 +637,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt32>(oaknut::CodeGenerator& code, EmitCon
                 code.FRINTA(Qresult->S4(), Qoperand->S4());
                 break;
             default:
-                std::terminate(); //unreachable
+                assert(false && "unreachable");
             }
         }
     });
@@ -677,7 +677,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt64>(oaknut::CodeGenerator& code, EmitCon
                 code.FRINTA(Qresult->D2(), Qoperand->D2());
                 break;
             default:
-                std::terminate(); //unreachable
+                assert(false && "unreachable");
             }
         }
     });
@@ -688,7 +688,7 @@ void EmitIR<IR::Opcode::FPVectorRSqrtEstimate16>(oaknut::CodeGenerator& code, Em
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -706,7 +706,7 @@ void EmitIR<IR::Opcode::FPVectorRSqrtStepFused16>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -761,7 +761,7 @@ void EmitIR<IR::Opcode::FPVectorToSignedFixed16>(oaknut::CodeGenerator& code, Em
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
@@ -779,7 +779,7 @@ void EmitIR<IR::Opcode::FPVectorToUnsignedFixed16>(oaknut::CodeGenerator& code,
     (void)code;
     (void)ctx;
     (void)inst;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 template<>
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_saturation.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_saturation.cpp
index 0fe8dd11bd..97b3ed7100 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_saturation.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_saturation.cpp
@@ -41,7 +41,7 @@ static void Emit(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst, EmitF
     } else if constexpr (size == 64) {
         emit(Qresult->D2(), Qa->D2(), Qb->D2());
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp
index eff72ee08e..e269f53e8d 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp
@@ -298,7 +298,7 @@ int RegAlloc::GenerateImmediate(const IR::Value& value) {
 
         return 0;
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -325,7 +325,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
 
         switch (current_location->kind) {
         case HostLoc::Kind::Gpr:
-            std::terminate(); //unreachable //logic error
+            assert(false && "unreachable"); //logic error
         case HostLoc::Kind::Fpr:
             code.FMOV(oaknut::XReg{new_location_index}, oaknut::DReg{current_location->index});
             // assert size fits
@@ -350,7 +350,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
             code.FMOV(oaknut::DReg{new_location_index}, oaknut::XReg{current_location->index});
             break;
         case HostLoc::Kind::Fpr:
-            std::terminate(); //unreachable //logic error
+            assert(false && "unreachable"); //logic error
         case HostLoc::Kind::Spill:
             code.LDR(oaknut::QReg{new_location_index}, SP, spill_offset + current_location->index * spill_slot_size);
             break;
@@ -363,9 +363,9 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
         fprs[new_location_index].realized = true;
         return new_location_index;
     } else if constexpr (required_kind == HostLoc::Kind::Flags) {
-        std::terminate(); //unreachable //A simple read from flags is likely a logic error
+        assert(false && "unreachable"); //A simple read from flags is likely a logic error
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -389,7 +389,7 @@ int RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
         flags.SetupLocation(value);
         return 0;
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -409,7 +409,7 @@ int RegAlloc::RealizeReadWriteImpl(const IR::Value& read_value, const IR::Inst*
     } else if constexpr (kind == HostLoc::Kind::Flags) {
         assert(false && "Incorrect function for ReadWrite of flags");
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -479,7 +479,7 @@ void RegAlloc::ReadWriteFlags(Argument& read, IR::Inst* write) {
         code.LDR(Wscratch0, SP, spill_offset + current_location->index * spill_slot_size);
         code.MSR(oaknut::SystemReg::NZCV, Xscratch0);
     } else {
-        std::terminate(); //unreachable //assert(false && "Invalid current location for flags");
+        assert(false && "unreachable"); //assert(false && "Invalid current location for flags");
     }
 
     if (write) {
@@ -551,7 +551,7 @@ void RegAlloc::LoadCopyInto(const IR::Value& value, oaknut::QReg reg) {
         code.LDR(reg, SP, spill_offset + current_location->index * spill_slot_size);
         break;
     case HostLoc::Kind::Flags:
-        std::terminate(); //unreachable //assert(false && "Moving from flags into fprs is not currently supported");
+        assert(false && "unreachable"); //assert(false && "Moving from flags into fprs is not currently supported");
     }
 }
 
@@ -584,7 +584,7 @@ HostLocInfo& RegAlloc::ValueInfo(HostLoc host_loc) {
     case HostLoc::Kind::Spill:
         return spills[static_cast<size_t>(host_loc.index)];
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
@@ -599,7 +599,7 @@ HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
     } else if (const auto iter = std::find_if(spills.begin(), spills.end(), contains_value); iter != spills.end()) {
         return *iter;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 }  // namespace Dynarmic::Backend::Arm64
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h
index 79ab9b3d96..f4039448f3 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h
@@ -186,7 +186,7 @@ public:
         } else if constexpr (size == 32) {
             return ReadW(arg);
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -203,7 +203,7 @@ public:
         } else if constexpr (size == 8) {
             return ReadB(arg);
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -225,7 +225,7 @@ public:
         } else if constexpr (size == 32) {
             return WriteW(inst);
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -242,7 +242,7 @@ public:
         } else if constexpr (size == 8) {
             return WriteB(inst);
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -262,7 +262,7 @@ public:
         } else if constexpr (size == 32) {
             return ReadWriteW(arg, inst);
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -279,7 +279,7 @@ public:
         } else if constexpr (size == 8) {
             return ReadWriteB(arg, inst);
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -370,7 +370,7 @@ void RAReg<T>::Realize() {
         reg = T{reg_alloc.RealizeReadWriteImpl<kind>(read_value, write_value)};
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp
index 575e6997ec..d291ea8887 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp
@@ -128,7 +128,7 @@ void A32AddressSpace::Link(EmittedBlockInfo& block_info) {
             break;
         }
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 }
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp
index f8f66fbf2b..543f48b3b8 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp
@@ -110,7 +110,7 @@ struct Jit::Impl final {
 
 private:
     void RequestCacheInvalidation() {
-        // std::terminate(); //unreachable
+        // assert(false && "unreachable");
 
         invalidate_entire_cache = false;
         invalid_cache_ranges.clear();
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/a64_interface.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/a64_interface.cpp
index cee46bd02b..b9342cb54d 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/a64_interface.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/a64_interface.cpp
@@ -160,7 +160,7 @@ struct Jit::Impl final {
 
 private:
     void RequestCacheInvalidation() {
-        // std::terminate(); //unreachable
+        // assert(false && "unreachable");
         invalidate_entire_cache = false;
         invalid_cache_ranges.clear();
     }
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp
index e4a7d8d7c3..26ff1c0cd6 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp
@@ -143,7 +143,7 @@ EmittedBlockInfo EmitRV64(biscuit::Assembler& as, IR::Block block, const EmitCon
 #undef A32OPC
 #undef A64OPC
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp
index 18d3469123..c869e6546a 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp
@@ -108,7 +108,7 @@ void EmitA32Cond(biscuit::Assembler& as, EmitContext&, IR::Cond cond, biscuit::L
         as.BNEZ(Xscratch0, label);
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp
index 282ff06a7f..836a0d16ca 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp
@@ -163,7 +163,7 @@ u32 RegAlloc::GenerateImmediate(const IR::Value& value) {
     } else if constexpr (kind == HostLoc::Kind::Fpr) {
         std::terminate(); //unimplemented
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
     return 0;
 }
@@ -191,7 +191,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
 
         switch (current_location->kind) {
         case HostLoc::Kind::Gpr:
-            std::terminate(); //unreachable //logic error
+            assert(false && "unreachable"); //logic error
         case HostLoc::Kind::Fpr:
             as.FMV_X_D(biscuit::GPR(new_location_index), biscuit::FPR{current_location->index});
             // assert size fits
@@ -213,7 +213,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
             as.FMV_D_X(biscuit::FPR{new_location_index}, biscuit::GPR(current_location->index));
             break;
         case HostLoc::Kind::Fpr:
-            std::terminate(); //unreachable //logic error
+            assert(false && "unreachable"); //logic error
         case HostLoc::Kind::Spill:
             as.FLD(biscuit::FPR{new_location_index}, spill_offset + current_location->index * spill_slot_size, biscuit::sp);
             break;
@@ -223,7 +223,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
         fprs[new_location_index].realized = true;
         return new_location_index;
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -250,7 +250,7 @@ u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
         setup_location(fprs[new_location_index]);
         return new_location_index;
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -322,7 +322,7 @@ HostLocInfo& RegAlloc::ValueInfo(HostLoc host_loc) {
     case HostLoc::Kind::Spill:
         return spills[size_t(host_loc.index)];
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
@@ -336,7 +336,7 @@ HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
     } else if (const auto iter = std::find_if(spills.begin(), spills.end(), contains_value); iter != gprs.end()) {
         return *iter;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp b/src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp
index f7e6f06a64..09b5d61023 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp
@@ -56,7 +56,7 @@ static Xbyak::Address MJitStateExtReg(A32::ExtReg reg) {
         const size_t index = size_t(reg) - size_t(A32::ExtReg::Q0);
         return xword[BlockOfCode::ABI_JIT_PTR + offsetof(A32JitState, ExtReg) + 2 * sizeof(u64) * index];
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 A32EmitContext::A32EmitContext(const A32::UserConfig& conf, RegAlloc& reg_alloc, IR::Block& block)
@@ -135,7 +135,7 @@ A32EmitX64::BlockDescriptor A32EmitX64::Emit(IR::Block& block) {
 #undef A32OPC
 #undef A64OPC
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
         reg_alloc.EndOfAllocScope();
 #ifndef NDEBUG
@@ -833,7 +833,7 @@ void A32EmitX64::EmitA32SetFpscrNZCV(A32EmitContext& ctx, IR::Inst* inst) {
 }
 
 static void EmitCoprocessorException() {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 static void CallCoprocCallback(BlockOfCode& code, RegAlloc& reg_alloc, A32::Coprocessor::Callback callback, IR::Inst* inst = nullptr, std::optional<Argument::copyable_reference> arg0 = {}, std::optional<Argument::copyable_reference> arg1 = {}) {
@@ -909,7 +909,7 @@ void A32EmitX64::EmitA32CoprocSendOneWord(A32EmitContext& ctx, IR::Inst* inst) {
         return;
     }
 
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void A32EmitX64::EmitA32CoprocSendTwoWords(A32EmitContext& ctx, IR::Inst* inst) {
@@ -952,7 +952,7 @@ void A32EmitX64::EmitA32CoprocSendTwoWords(A32EmitContext& ctx, IR::Inst* inst)
         return;
     }
 
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void A32EmitX64::EmitA32CoprocGetOneWord(A32EmitContext& ctx, IR::Inst* inst) {
@@ -995,7 +995,7 @@ void A32EmitX64::EmitA32CoprocGetOneWord(A32EmitContext& ctx, IR::Inst* inst) {
         return;
     }
 
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void A32EmitX64::EmitA32CoprocGetTwoWords(A32EmitContext& ctx, IR::Inst* inst) {
@@ -1040,7 +1040,7 @@ void A32EmitX64::EmitA32CoprocGetTwoWords(A32EmitContext& ctx, IR::Inst* inst) {
         return;
     }
 
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void A32EmitX64::EmitA32CoprocLoadWords(A32EmitContext& ctx, IR::Inst* inst) {
@@ -1216,7 +1216,7 @@ void EmitTerminalImpl(A32EmitX64& e, IR::Term::CheckHalt terminal, IR::LocationD
 }
 
 void EmitTerminalImpl(A32EmitX64&, IR::Term::Invalid, IR::LocationDescriptor, bool) {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp b/src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp
index 4b16176b6b..985e22e174 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp
@@ -123,7 +123,7 @@ A64EmitX64::BlockDescriptor A64EmitX64::Emit(IR::Block& block) noexcept {
 #undef A32OPC
 #undef A64OPC
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
 opcode_branch:
         (this->*opcode_handlers[size_t(opcode)])(ctx, &inst);
@@ -710,7 +710,7 @@ void EmitTerminalImpl(A64EmitX64& e, IR::Term::CheckHalt terminal, IR::LocationD
 }
 
 void EmitTerminalImpl(A64EmitX64&, IR::Term::Invalid, IR::LocationDescriptor, bool) {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp b/src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp
index efaf463983..a21ab87480 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp
@@ -515,7 +515,7 @@ void BlockOfCode::LoadRequiredFlagsForCondFromRax(IR::Cond cond) {
     case IR::Cond::NV:
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/block_of_code.h b/src/dynarmic/src/dynarmic/backend/x64/block_of_code.h
index ab05a0fa40..be27f81579 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/block_of_code.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/block_of_code.h
@@ -120,7 +120,7 @@ public:
         case 64:
             return;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp
index b9fe0f27cc..4025a70646 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp
@@ -53,7 +53,7 @@ std::optional<EmitX64::BlockDescriptor> EmitX64::GetBasicBlock(IR::LocationDescr
 }
 
 void EmitX64::EmitInvalid(EmitContext&, IR::Inst* inst) {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void EmitX64::EmitVoid(EmitContext&, IR::Inst*) {
@@ -193,7 +193,7 @@ void EmitX64::EmitGetNZFromOp(EmitContext& ctx, IR::Inst* inst) {
         case IR::Type::U64:
             return 64;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }();
 
@@ -224,7 +224,7 @@ void EmitX64::EmitGetNZCVFromOp(EmitContext& ctx, IR::Inst* inst) {
         case IR::Type::U64:
             return 64;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }();
 
@@ -339,7 +339,7 @@ Xbyak::Label EmitX64::EmitCond(IR::Cond cond) {
         code.jle(pass);
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
     return pass;
 }
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp
index f0d2bef7af..bce5b27397 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp
@@ -194,7 +194,7 @@ static void EmitConditionalSelect(BlockOfCode& code, EmitContext& ctx, IR::Inst*
         code.mov(else_, then_);
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     ctx.reg_alloc.DefineValue(code, inst, else_);
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp
index bac10be02e..2e16ffa6de 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp
@@ -659,7 +659,7 @@ static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, bo
                 FCODE(ucomis)(result, result);
                 code.jp(*fallback, code.T_NEAR);
             } else {
-                std::terminate(); //unreachable
+                assert(false && "unreachable");
             }
             if (ctx.FPCR().DN()) {
                 ForceToDefaultNaN<fsize>(code, result);
@@ -1079,7 +1079,7 @@ static void EmitFPRound(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, siz
         case 64: code.CallFunction(EmitFPRoundThunk<u64>); break;
         case 32: code.CallFunction(EmitFPRoundThunk<u32>); break;
         case 16: code.CallFunction(EmitFPRoundThunk<u16>); break;
-        default: std::terminate(); //unreachable
+        default: assert(false && "unreachable");
         }
     }
 }
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc
index 45d767f67f..b84375ef26 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc
@@ -43,7 +43,7 @@ FakeCall AxxEmitX64::FastmemCallback(u64 rip_) {
     }
     fmt::print("dynarmic: Segfault happened within JITted code at rip = {:016x}\n"
         "Segfault wasn't at a fastmem patch location!\n", rip_);
-    std::terminate(); //unreachable //("iter != fastmem_patch_info.end()");
+    assert(false && "unreachable"); //("iter != fastmem_patch_info.end()");
 }
 
 template<std::size_t bitsize, auto callback>
@@ -489,7 +489,7 @@ void AxxEmitX64::EmitExclusiveWriteMemoryInline(AxxEmitContext& ctx, IR::Inst* i
             code.cmpxchg16b(ptr[dest_ptr]);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
 
         code.setnz(status.cvt8());
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h
index 83211c6c7c..dfb0b28df1 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h
@@ -45,7 +45,7 @@ void EmitDetectMisalignedVAddr(BlockOfCode& code, EmitContext& ctx, size_t bitsi
         case 128:
             return 0b1111;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }();
 
@@ -247,7 +247,7 @@ const void* EmitReadMemoryMov(BlockOfCode& code, int value_idx, const Xbyak::Reg
             }
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
         return fastmem_location;
     } else {
@@ -269,7 +269,7 @@ const void* EmitReadMemoryMov(BlockOfCode& code, int value_idx, const Xbyak::Reg
             code.movups(Xbyak::Xmm(value_idx), xword[addr]);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
         return fastmem_location;
     }
@@ -315,7 +315,7 @@ const void* EmitWriteMemoryMov(BlockOfCode& code, const Xbyak::RegExp& addr, int
             break;
         }
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
         return fastmem_location;
     } else {
@@ -337,7 +337,7 @@ const void* EmitWriteMemoryMov(BlockOfCode& code, const Xbyak::RegExp& addr, int
             code.movups(xword[addr], Xbyak::Xmm(value_idx));
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
         return fastmem_location;
     }
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp
index 8a062fffde..c906cdec93 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp
@@ -2280,27 +2280,27 @@ void EmitX64::EmitVectorMultiply64(EmitContext& ctx, IR::Inst* inst) {
 }
 
 void EmitX64::EmitVectorMultiplySignedWiden8(EmitContext&, IR::Inst*) {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void EmitX64::EmitVectorMultiplySignedWiden16(EmitContext&, IR::Inst*) {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void EmitX64::EmitVectorMultiplySignedWiden32(EmitContext&, IR::Inst*) {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void EmitX64::EmitVectorMultiplyUnsignedWiden8(EmitContext&, IR::Inst*) {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void EmitX64::EmitVectorMultiplyUnsignedWiden16(EmitContext&, IR::Inst*) {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void EmitX64::EmitVectorMultiplyUnsignedWiden32(EmitContext&, IR::Inst*) {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void EmitX64::EmitVectorNarrow16(EmitContext& ctx, IR::Inst* inst) {
@@ -3869,7 +3869,7 @@ static void EmitVectorSignedAbsoluteDifference(size_t esize, EmitContext& ctx, I
             code.psubd(x, tmp);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     } else {
         code.movdqa(tmp, y);
@@ -3888,7 +3888,7 @@ static void EmitVectorSignedAbsoluteDifference(size_t esize, EmitContext& ctx, I
             code.psubd(x, tmp);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -4092,7 +4092,7 @@ static void EmitVectorSignedSaturatedAbs(size_t esize, BlockOfCode& code, EmitCo
         break;
     }
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     code.or_(code.dword[code.ABI_JIT_PTR + code.GetJitStateInfo().offsetof_fpsr_qc], bit);
@@ -4542,7 +4542,7 @@ static void EmitVectorSignedSaturatedNarrowToSigned(size_t original_esize, Block
         code.punpcklwd(reconstructed, sign);
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     const Xbyak::Reg32 bit = ctx.reg_alloc.ScratchGpr(code).cvt32();
@@ -4597,7 +4597,7 @@ static void EmitVectorSignedSaturatedNarrowToUnsigned(size_t original_esize, Blo
         code.punpcklwd(reconstructed, xmm0);
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     const Xbyak::Reg32 bit = ctx.reg_alloc.ScratchGpr(code).cvt32();
@@ -4661,7 +4661,7 @@ static void EmitVectorSignedSaturatedNeg(size_t esize, BlockOfCode& code, EmitCo
         case 64:
             return code.Const(xword, 0x8000000000000000, 0x8000000000000000);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }();
 
@@ -4957,7 +4957,7 @@ void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) {
             break;
         }
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
             break;
         }
         return;
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp
index 9c3d972fd7..6faab89f2e 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp
@@ -265,7 +265,7 @@ struct PairedIndexer {
         case 1:
             return std::make_tuple(b[2 * i], b[2 * i + 1]);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 };
 
@@ -288,7 +288,7 @@ struct PairedLowerIndexer {
             }
             return std::make_tuple(0, 0);
         } else {
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 };
@@ -681,7 +681,7 @@ void EmitX64::EmitFPVectorFromHalf32(EmitContext& ctx, IR::Inst* inst) {
             EmitTwoOpFallback<2>(code, ctx, inst, EmitFPVectorFromHalf32Thunk<FP::RoundingMode::ToNearest_TieAwayFromZero>);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 }
@@ -1679,7 +1679,7 @@ void EmitFPVectorRoundInt(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
                 case FP::RoundingMode::TowardsPlusInfinity: return 0b10;
                 case FP::RoundingMode::TowardsMinusInfinity: return 0b01;
                 case FP::RoundingMode::TowardsZero: return 0b11;
-                default: std::terminate(); //unreachable
+                default: assert(false && "unreachable");
                 }
             }();
 
@@ -1720,7 +1720,7 @@ void EmitFPVectorRoundInt(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
             : EmitTwoOpFallback<3>(code, ctx, inst, EmitFPVectorRoundIntThunk<FPT, FP::RoundingMode::ToNearest_TieAwayFromZero, false>);
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -1988,7 +1988,7 @@ void EmitX64::EmitFPVectorToHalf32(EmitContext& ctx, IR::Inst* inst) {
             EmitTwoOpFallback<2>(code, ctx, inst, EmitFPVectorToHalf32Thunk<FP::RoundingMode::ToNearest_TieAwayFromZero>);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 }
diff --git a/src/dynarmic/src/dynarmic/backend/x64/hostloc.h b/src/dynarmic/src/dynarmic/backend/x64/hostloc.h
index 654ffa7510..88e8df9f90 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/hostloc.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/hostloc.h
@@ -106,7 +106,7 @@ constexpr size_t HostLocBitWidth(HostLoc loc) {
         return 128;
     else if (HostLocIsFlag(loc))
         return 1;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 constexpr std::bitset<32> BuildRegSet(std::initializer_list<HostLoc> regs) {
diff --git a/src/dynarmic/src/dynarmic/backend/x64/oparg.h b/src/dynarmic/src/dynarmic/backend/x64/oparg.h
index bd2e68b3dd..ae170452ba 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/oparg.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/oparg.h
@@ -30,7 +30,7 @@ struct OpArg {
         case Type::Reg:
             return inner_reg;
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     void setBit(int bits) {
@@ -57,7 +57,7 @@ struct OpArg {
                 return;
             }
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
 private:
diff --git a/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp b/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp
index a02657dd55..08581babf2 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp
@@ -47,7 +47,7 @@ static inline size_t GetBitWidth(const IR::Type type) noexcept {
         return 32;  // TODO: Update to 16 when flags optimization is done
     default:
         // A32REG A32EXTREG A64REG A64VEC COPROCINFO COND VOID TABLE ACCTYPE OPAQUE
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -375,7 +375,7 @@ void RegAlloc::HostCall(
             case IR::Type::U64:
                 break; //no op
             default:
-                std::terminate(); //unreachable
+                assert(false && "unreachable");
             }
         }
     }
@@ -548,7 +548,7 @@ HostLoc RegAlloc::FindFreeSpill(bool is_xmm) const noexcept {
     for (size_t i = size_t(HostLoc::FirstSpill); i < hostloc_info.size(); ++i)
         if (const auto loc = HostLoc(i); LocInfo(loc).IsEmpty())
             return loc;
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 #define MAYBE_AVX(OPCODE, ...) \
@@ -576,7 +576,7 @@ HostLoc RegAlloc::LoadImmediate(BlockOfCode& code, IR::Value imm, HostLoc host_l
             MAYBE_AVX(movaps, reg, code.Const(code.xword, imm_value));
         }
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
     return host_loc;
 }
@@ -630,7 +630,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
             MAYBE_AVX(movss, HostLocToXmm(to), spill_addr);
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     } else if (HostLocIsSpill(to) && HostLocIsXMM(from)) {
         const Xbyak::Address spill_addr = spill_xmm_to_op(to);
@@ -648,7 +648,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
             MAYBE_AVX(movss, spill_addr, HostLocToXmm(from));
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     } else if (HostLocIsGPR(to) && HostLocIsSpill(from)) {
         assert(bit_width != 128);
@@ -665,7 +665,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
             code.mov(Xbyak::util::dword[spill_to_op_arg_helper(to, reserved_stack_space)], HostLocToReg64(from).cvt32());
         }
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 #undef MAYBE_AVX
diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp b/src/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp
index 83d67ebede..a3d4bb0b54 100644
--- a/src/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp
@@ -55,7 +55,7 @@ FPT FPRecipEstimate(FPT op, FPCR fpcr, FPSR& fpsr) {
             case RoundingMode::TowardsZero:
                 return false;
             default:
-                std::terminate(); //unreachable
+                assert(false && "unreachable");
             }
         }();
 
@@ -86,7 +86,7 @@ FPT FPRecipEstimate(FPT op, FPCR fpcr, FPSR& fpsr) {
             result_exponent++;
             break;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp b/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp
index 6fea954bf8..2dc3a3f747 100644
--- a/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp
@@ -72,7 +72,7 @@ u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr)
         round_up = error > ResidualError::Half || (error == ResidualError::Half && !mcl::bit::most_significant_bit(int_result));
         break;
     case RoundingMode::ToOdd:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     if (round_up) {
diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp b/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp
index 21ffa0139b..33058b4909 100644
--- a/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp
@@ -70,7 +70,7 @@ u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, Rou
         round_up = error > ResidualError::Half || (error == ResidualError::Half && !mcl::bit::most_significant_bit(int_result));
         break;
     case RoundingMode::ToOdd:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     if (round_up) {
diff --git a/src/dynarmic/src/dynarmic/common/fp/process_exception.cpp b/src/dynarmic/src/dynarmic/common/fp/process_exception.cpp
index 108e944f3d..58d23002e9 100644
--- a/src/dynarmic/src/dynarmic/common/fp/process_exception.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/process_exception.cpp
@@ -42,7 +42,7 @@ void FPProcessException(FPExc exception, FPCR fpcr, FPSR& fpsr) {
         fpsr.IDC(true);
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp b/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp
index 2ea9f82492..a7f1d0e9da 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp
@@ -35,7 +35,7 @@ size_t IREmitter::ArchVersion() const {
     case ArchVersion::v8:
         return 8;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 u32 IREmitter::PC() const {
@@ -60,7 +60,7 @@ IR::U32U64 IREmitter::GetExtendedRegister(ExtReg reg) {
         return Inst<IR::U32U64>(Opcode::A32GetExtendedRegister32, IR::Value(reg));
     else if (A32::IsDoubleExtReg(reg))
         return Inst<IR::U32U64>(Opcode::A32GetExtendedRegister64, IR::Value(reg));
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 IR::U128 IREmitter::GetVector(ExtReg reg) {
@@ -79,7 +79,7 @@ void IREmitter::SetExtendedRegister(const ExtReg reg, const IR::U32U64& value) {
     } else if (A32::IsDoubleExtReg(reg)) {
         Inst(Opcode::A32SetExtendedRegister64, IR::Value(reg), value);
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -236,7 +236,7 @@ IR::UAny IREmitter::ReadMemory(size_t bitsize, const IR::U32& vaddr, IR::AccType
     case 64:
         return ReadMemory64(vaddr, acc_type);
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 IR::U8 IREmitter::ReadMemory8(const IR::U32& vaddr, IR::AccType acc_type) {
@@ -294,7 +294,7 @@ void IREmitter::WriteMemory(size_t bitsize, const IR::U32& vaddr, const IR::UAny
     case 64:
         return WriteMemory64(vaddr, value, acc_type);
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void IREmitter::WriteMemory8(const IR::U32& vaddr, const IR::U8& value, IR::AccType acc_type) {
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_crc32.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_crc32.cpp
index 4ae0a5e6b8..b40fafd2cb 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_crc32.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_crc32.cpp
@@ -77,7 +77,7 @@ bool CRC32Variant(TranslatorVisitor& v, Cond cond, Imm<2> sz, Reg n, Reg d, Reg
             }
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
 
     v.ir.SetRegister(d, result);
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp
index b36d85a8d1..5379c59d68 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp
@@ -66,7 +66,7 @@ IR::UAny TranslatorVisitor::I(size_t bitsize, u64 value) {
     case 64:
         return ir.Imm64(value);
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -92,7 +92,7 @@ IR::ResultAndCarry<IR::U32> TranslatorVisitor::EmitImmShift(IR::U32 value, Shift
             return ir.RotateRightExtended(value, carry_in);
         }
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 IR::ResultAndCarry<IR::U32> TranslatorVisitor::EmitRegShift(IR::U32 value, ShiftType type, IR::U8 amount, IR::U1 carry_in) {
@@ -106,7 +106,7 @@ IR::ResultAndCarry<IR::U32> TranslatorVisitor::EmitRegShift(IR::U32 value, Shift
     case ShiftType::ROR:
         return ir.RotateRight(value, amount, carry_in);
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 }  // namespace Dynarmic::A32
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h
index c7306f18ac..ef5438a1d7 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h
@@ -77,7 +77,7 @@ struct TranslatorVisitor final {
                 case 0b11:
                     return mcl::bit::replicate_element<u8, u32>(imm8);
                 }
-                std::terminate(); //unreachable
+                assert(false && "unreachable");
             }();
             return {imm32, carry_in};
         }
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp
index c7beb96d56..27180be470 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp
@@ -72,7 +72,7 @@ std::optional<std::tuple<size_t, size_t, size_t>> DecodeType(Imm<4> type, size_t
         }
         return std::tuple<size_t, size_t, size_t>{4, 1, 2};
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 }  // namespace
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp
index e2cebd0346..71dc9d51c6 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp
@@ -110,7 +110,7 @@ bool TranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c, Imm
         return bic();
     }
 
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 }  // namespace Dynarmic::A32
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
index 2c2fec6940..0f89b0df87 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
@@ -172,7 +172,7 @@ bool TranslatorVisitor::asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool
             return ir.VectorReverseElementsInHalfGroups(esize, reg_m);
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
 
     ir.SetVector(d, result);
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
index 8cc977ea20..8e3874df42 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
@@ -133,7 +133,7 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, bool D, size_t imm6, size_t Vd, b
             assert(signedness == Signedness::Signed);
             return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
 
     v.ir.SetVector(d, result);
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp
index aef0c9d2e9..c218b0930b 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp
@@ -870,11 +870,11 @@ bool TranslatorVisitor::arm_LDMIB(Cond cond, bool W, Reg n, RegList list) {
 }
 
 bool TranslatorVisitor::arm_LDM_usr() {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 bool TranslatorVisitor::arm_LDM_eret() {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 static bool STMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::U32 start_address, IR::U32 writeback_address) {
@@ -955,7 +955,7 @@ bool TranslatorVisitor::arm_STMIB(Cond cond, bool W, Reg n, RegList list) {
 }
 
 bool TranslatorVisitor::arm_STM_usr() {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 }  // namespace Dynarmic::A32
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp
index 2eb045237c..36b75021f4 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp
@@ -15,7 +15,7 @@ namespace Dynarmic::A32 {
 // CPS<effect> <iflags>{, #<mode>}
 // CPS #<mode>
 bool TranslatorVisitor::arm_CPS() {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 // MRS<c> <Rd>, <spec_reg>
@@ -107,7 +107,7 @@ bool TranslatorVisitor::arm_MSR_reg(Cond cond, unsigned mask, Reg n) {
 
 // RFE{<amode>} <Rn>{!}
 bool TranslatorVisitor::arm_RFE() {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 // SETEND <endian_specifier>
@@ -118,7 +118,7 @@ bool TranslatorVisitor::arm_SETEND(bool E) {
 
 // SRS{<amode>} SP{!}, #<mode>
 bool TranslatorVisitor::arm_SRS() {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 }  // namespace Dynarmic::A32
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp
index c89bf108f0..72f1f17e1a 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp
@@ -30,7 +30,7 @@ bool TranslatorVisitor::SCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg
         case 64:
             return ir.FPSignedFixedToDouble(intval, fracbits, rounding_mode);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
 
     V_scalar(*fltsize, Vd, fltval);
@@ -57,7 +57,7 @@ bool TranslatorVisitor::UCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg
         case 64:
             return ir.FPUnsignedFixedToDouble(intval, fracbits, rounding_mode);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
 
     V_scalar(*fltsize, Vd, fltval);
@@ -82,7 +82,7 @@ bool TranslatorVisitor::FCVTZS_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec
     } else if (intsize == 64) {
         intval = ir.FPToFixedS64(fltval, fracbits, FP::RoundingMode::TowardsZero);
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     X(intsize, Rd, intval);
@@ -107,7 +107,7 @@ bool TranslatorVisitor::FCVTZU_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec
     } else if (intsize == 64) {
         intval = ir.FPToFixedU64(fltval, fracbits, FP::RoundingMode::TowardsZero);
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     X(intsize, Rd, intval);
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp
index 417ba04e46..92389d69d5 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp
@@ -26,7 +26,7 @@ bool TranslatorVisitor::SCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
     } else if (*fltsize == 64) {
         fltval = ir.FPSignedFixedToDouble(intval, 0, ir.current_location->FPCR().RMode());
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     V_scalar(*fltsize, Vd, fltval);
@@ -49,7 +49,7 @@ bool TranslatorVisitor::UCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
     } else if (*fltsize == 64) {
         fltval = ir.FPUnsignedFixedToDouble(intval, 0, ir.current_location->FPCR().RMode());
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     V_scalar(*fltsize, Vd, fltval);
@@ -78,7 +78,7 @@ bool TranslatorVisitor::FMOV_float_gen(bool sf, Imm<2> type, Imm<1> rmode_0, Imm
         case 0b11:
             return 16;
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }();
 
@@ -130,7 +130,7 @@ static bool FloaingPointConvertSignedInteger(TranslatorVisitor& v, bool sf, Imm<
     } else if (intsize == 64) {
         intval = v.ir.FPToFixedS64(fltval, 0, rounding_mode);
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     v.X(intsize, Rd, intval);
@@ -152,7 +152,7 @@ static bool FloaingPointConvertUnsignedInteger(TranslatorVisitor& v, bool sf, Im
     } else if (intsize == 64) {
         intval = v.ir.FPToFixedU64(fltval, 0, rounding_mode);
     } else {
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     v.X(intsize, Rd, intval);
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp
index 8c48000e92..47f04aa5ae 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp
@@ -19,7 +19,7 @@ bool TranslatorVisitor::UnpredictableInstruction() {
 }
 
 bool TranslatorVisitor::DecodeError() {
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 bool TranslatorVisitor::ReservedValue() {
@@ -72,7 +72,7 @@ IR::UAny TranslatorVisitor::I(size_t bitsize, u64 value) {
     case 64:
         return ir.Imm64(value);
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 IR::UAny TranslatorVisitor::X(size_t bitsize, Reg reg) {
@@ -86,7 +86,7 @@ IR::UAny TranslatorVisitor::X(size_t bitsize, Reg reg) {
     case 64:
         return ir.GetX(reg);
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void TranslatorVisitor::X(size_t bitsize, Reg reg, IR::U32U64 value) {
@@ -98,7 +98,7 @@ void TranslatorVisitor::X(size_t bitsize, Reg reg, IR::U32U64 value) {
         ir.SetX(reg, value);
         return;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 IR::U32U64 TranslatorVisitor::SP(size_t bitsize) {
@@ -108,7 +108,7 @@ IR::U32U64 TranslatorVisitor::SP(size_t bitsize) {
     case 64:
         return ir.GetSP();
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void TranslatorVisitor::SP(size_t bitsize, IR::U32U64 value) {
@@ -120,7 +120,7 @@ void TranslatorVisitor::SP(size_t bitsize, IR::U32U64 value) {
         ir.SetSP(value);
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -133,7 +133,7 @@ IR::U128 TranslatorVisitor::V(size_t bitsize, Vec vec) {
     case 128:
         return ir.GetQ(vec);
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void TranslatorVisitor::V(size_t bitsize, Vec vec, IR::U128 value) {
@@ -149,7 +149,7 @@ void TranslatorVisitor::V(size_t bitsize, Vec vec, IR::U128 value) {
         ir.SetQ(vec, value);
         return;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 IR::UAnyU128 TranslatorVisitor::V_scalar(size_t bitsize, Vec vec) {
@@ -223,7 +223,7 @@ IR::UAnyU128 TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccTyp
     case 16:
         return ir.ReadMemory128(address, acc_type);
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccType acc_type, IR::UAnyU128 value) {
@@ -244,7 +244,7 @@ void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccType acc_ty
         ir.WriteMemory128(address, value, acc_type);
         return;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 IR::UAnyU128 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::AccType acc_type) {
@@ -260,7 +260,7 @@ IR::UAnyU128 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, I
     case 16:
         return ir.ExclusiveReadMemory128(address, acc_type);
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 IR::U32 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::AccType acc_type, IR::UAnyU128 value) {
@@ -276,7 +276,7 @@ IR::U32 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::Ac
     case 16:
         return ir.ExclusiveWriteMemory128(address, value, acc_type);
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 IR::U32U64 TranslatorVisitor::SignExtend(IR::UAny value, size_t to_size) {
@@ -286,7 +286,7 @@ IR::U32U64 TranslatorVisitor::SignExtend(IR::UAny value, size_t to_size) {
     case 64:
         return ir.SignExtendToLong(value);
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 IR::U32U64 TranslatorVisitor::ZeroExtend(IR::UAny value, size_t to_size) {
@@ -296,7 +296,7 @@ IR::U32U64 TranslatorVisitor::ZeroExtend(IR::UAny value, size_t to_size) {
     case 64:
         return ir.ZeroExtendToLong(value);
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 IR::U32U64 TranslatorVisitor::ShiftReg(size_t bitsize, Reg reg, Imm<2> shift, IR::U8 amount) {
@@ -311,7 +311,7 @@ IR::U32U64 TranslatorVisitor::ShiftReg(size_t bitsize, Reg reg, Imm<2> shift, IR
     case 0b11:
         return ir.RotateRight(result, amount);
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, u8 shift) {
@@ -374,7 +374,7 @@ IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option,
         break;
     }
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     if (len < bitsize) {
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp
index a5c24f5176..fe65f7caae 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp
@@ -72,7 +72,7 @@ static bool ExclusiveSharedDecodeAndOperation(TranslatorVisitor& v, bool pair, s
         break;
     }
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     return true;
@@ -175,7 +175,7 @@ static bool OrderedSharedDecodeAndOperation(TranslatorVisitor& v, size_t size, b
         break;
     }
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     return true;
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp
index befc119567..e73e2cd229 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp
@@ -153,7 +153,7 @@ static bool LoadStoreSIMD(TranslatorVisitor& v, bool wback, bool postindex, size
         }
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     if (wback) {
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp
index 20407b1190..0801739144 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp
@@ -66,7 +66,7 @@ bool TranslatorVisitor::STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback,
         break;
     }
     case IR::MemOp::PREFETCH:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     if (wback) {
@@ -136,7 +136,7 @@ bool TranslatorVisitor::STP_LDP_fpsimd(Imm<2> opc, bool not_postindex, bool wbac
         break;
     }
     case IR::MemOp::PREFETCH:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     if (wback) {
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp
index 4bf8095e3f..5db9e80cd6 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp
@@ -70,7 +70,7 @@ static bool RegSharedDecodeAndOperation(TranslatorVisitor& v, size_t scale, u8 s
         // TODO: Prefetch
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     return true;
@@ -128,7 +128,7 @@ static bool VecSharedDecodeAndOperation(TranslatorVisitor& v, size_t scale, u8 s
         break;
     }
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     return true;
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp
index 907d1794be..1be6632b13 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp
@@ -81,7 +81,7 @@ bool FPMinMax(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, MinMaxOpera
         case MinMaxOperation::MinNumeric:
             return v.ir.FPMinNumeric(lhs, rhs);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     };
 
@@ -144,7 +144,7 @@ bool ScalarMinMax(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, Sca
             return v.ir.MinUnsigned(a, b);
 
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     };
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp
index 166a4a5c2e..87b2b8067a 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp
@@ -95,7 +95,7 @@ bool TranslatorVisitor::MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<
         return bic();
     }
 
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 bool TranslatorVisitor::FMOV_2(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd) {
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp
index 4a00e4f84b..8033d7630b 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp
@@ -34,7 +34,7 @@ bool FPPairwiseMinMax(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, MinMaxOpera
         case MinMaxOperationSSPW::MinNumeric:
             return v.ir.FPMinNumeric(element1, element2);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }();
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
index 02b95b44ea..d7af3496ad 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
@@ -201,7 +201,7 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn,
             assert(SignednessSSSBI == SignednessSSSBI::Signed);
             return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
 
     const IR::UAny segment = v.ir.VectorGetElement(esize, result, 0);
@@ -251,7 +251,7 @@ bool ScalarFPConvertWithRound(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Ve
                      : v.ir.FPUnsignedFixedToSingle(operand, fbits, rounding_mode);
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
 
     v.V_scalar(esize, Vd, result);
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp
index e9a1271008..27c189cc9e 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp
@@ -120,7 +120,7 @@ bool ScalarFPCompareRegister(TranslatorVisitor& v, bool sz, Vec Vm, Vec Vn, Vec
                                         v.ir.FPVectorAbs(esize, operand2));
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
 
     v.V_scalar(datasize, Vd, v.ir.VectorGetElement(esize, result, 0));
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
index 31517e7eb5..358f847592 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
@@ -43,7 +43,7 @@ bool ScalarFPCompareAgainstZero(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, C
             return v.ir.FPVectorGreater(esize, zero, operand);
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
 
     v.V_scalar(datasize, Vd, v.ir.VectorGetElement(esize, result, 0));
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
index 49227afa2a..9386451cb9 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
@@ -130,7 +130,7 @@ bool ShiftRightNarrowingSSBI(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> i
             assert(SignednessSSBI == SignednessSSBI::Signed);
             return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
 
     v.Vpart(64, Vd, part, result);
@@ -222,7 +222,7 @@ bool ConvertFloat(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn
                      ? v.ir.FPVectorToSignedFixed(esize, operand, fbits, rounding_mode)
                      : v.ir.FPVectorToUnsignedFixed(esize, operand, fbits, rounding_mode);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
 
     v.V(datasize, Vd, result);
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp
index c2118c9588..0dcfafdc9b 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp
@@ -161,7 +161,7 @@ bool FPCompareRegister(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Ve
                                         v.ir.FPVectorAbs(esize, operand2));
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
 
     v.V(datasize, Vd, result);
@@ -198,7 +198,7 @@ bool VectorMinMaxOperationSTS(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm,
             return v.ir.VectorMinUnsigned(esize, operand1, operand2);
 
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }();
 
@@ -275,7 +275,7 @@ bool PairedMinMaxOperationSTS(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm,
             return Q ? v.ir.VectorPairedMinUnsigned(esize, operand1, operand2) : v.ir.VectorPairedMinUnsignedLower(esize, operand1, operand2);
 
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }();
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp
index 365713e2b3..46590fa2b8 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp
@@ -77,7 +77,7 @@ bool FPCompareAgainstZero(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd,
             return v.ir.FPVectorGreater(esize, zero, operand);
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
 
     v.V(datasize, Vd, result);
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp
index 5244c6fbc4..a746d2c802 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp
@@ -83,7 +83,7 @@ bool FPMultiplyByElement(TranslatorVisitor& v, bool Q, bool sz, Imm<1> L, Imm<1>
         case ExtraBehaviorSVXIE::Subtract:
             return v.ir.FPVectorMulAdd(esize, operand3, v.ir.FPVectorNeg(esize, operand1), operand2);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
     v.V(datasize, Vd, result);
     return true;
@@ -113,7 +113,7 @@ bool FPMultiplyByElementHalfPrecision(TranslatorVisitor& v, bool Q, Imm<1> L, Im
         case ExtraBehaviorSVXIE::Subtract:
             return v.ir.FPVectorMulAdd(esize, operand3, v.ir.FPVectorNeg(esize, operand1), operand2);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }();
     v.V(datasize, Vd, result);
     return true;
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/system.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/system.cpp
index 40ad6e32df..e01036bf28 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/system.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/system.cpp
@@ -118,7 +118,7 @@ bool TranslatorVisitor::MSR_reg(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, I
     default:
         break;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 bool TranslatorVisitor::MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
@@ -158,7 +158,7 @@ bool TranslatorVisitor::MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3
         X(64, Rt, ir.GetTPIDRRO());
         return true;
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 }  // namespace Dynarmic::A64
diff --git a/src/dynarmic/src/dynarmic/frontend/imm.cpp b/src/dynarmic/src/dynarmic/frontend/imm.cpp
index 51a5d92ebd..58b03e8217 100644
--- a/src/dynarmic/src/dynarmic/frontend/imm.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/imm.cpp
@@ -64,7 +64,7 @@ u64 AdvSIMDExpandImm(bool op, Imm<4> cmode, Imm<8> imm8) {
             return result;
         }
     }
-    std::terminate(); //unreachable
+    assert(false && "unreachable");
 }
 
 }  // namespace Dynarmic
diff --git a/src/dynarmic/src/dynarmic/ir/ir_emitter.h b/src/dynarmic/src/dynarmic/ir/ir_emitter.h
index 25f64e7be7..8fe6a01d69 100644
--- a/src/dynarmic/src/dynarmic/ir/ir_emitter.h
+++ b/src/dynarmic/src/dynarmic/ir/ir_emitter.h
@@ -121,7 +121,7 @@ public:
             assert(value.GetType() == Type::U64);
             return value;
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U32 LeastSignificantWord(const U64& value) {
@@ -430,7 +430,7 @@ public:
         case Type::U64:
             return U64(a);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -445,7 +445,7 @@ public:
         case Type::U64:
             return Inst<U32>(Opcode::LeastSignificantWord, a);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -472,7 +472,7 @@ public:
         case Type::U64:
             return U64(a);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -487,7 +487,7 @@ public:
         case Type::U64:
             return Inst<U32>(Opcode::LeastSignificantWord, a);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -641,7 +641,7 @@ public:
             case IR::Type::U32:
                 return Inst<U32>(Opcode::SignedSaturatedDoublingMultiplyReturnHigh32, a, b);
             default:
-                std::terminate(); //unreachable
+                assert(false && "unreachable");
             }
         }();
         return result;
@@ -715,7 +715,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedAdd64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -730,7 +730,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedSub64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -745,7 +745,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -760,7 +760,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorUnsignedSaturatedSub64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1000,7 +1000,7 @@ public:
         case 64:
             return Inst<U64>(Opcode::VectorGetElement64, a, Imm8(static_cast<u8>(index)));
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1016,7 +1016,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSetElement64, a, Imm8(static_cast<u8>(index)), elem);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1031,7 +1031,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorAbs64, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorAdd(size_t esize, const U128& a, const U128& b) {
@@ -1045,7 +1045,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorAdd64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorAnd(const U128& a, const U128& b) {
@@ -1067,7 +1067,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorArithmeticShiftRight64, a, Imm8(shift_amount));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorArithmeticVShift(size_t esize, const U128& a, const U128& b) {
@@ -1081,7 +1081,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorArithmeticVShift64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorBroadcastLower(size_t esize, const UAny& a) {
@@ -1093,7 +1093,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorBroadcastLower32, U32(a));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorBroadcast(size_t esize, const UAny& a) {
@@ -1107,7 +1107,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorBroadcast64, U64(a));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorBroadcastElementLower(size_t esize, const U128& a, size_t index) {
@@ -1120,7 +1120,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorBroadcastElementLower32, a, u8(index));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorBroadcastElement(size_t esize, const U128& a, size_t index) {
@@ -1135,7 +1135,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorBroadcastElement64, a, u8(index));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorCountLeadingZeros(size_t esize, const U128& a) {
@@ -1147,7 +1147,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorCountLeadingZeros32, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorDeinterleaveEven(size_t esize, const U128& a, const U128& b) {
@@ -1161,7 +1161,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorDeinterleaveEven64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorDeinterleaveOdd(size_t esize, const U128& a, const U128& b) {
@@ -1175,7 +1175,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorDeinterleaveOdd64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorDeinterleaveEvenLower(size_t esize, const U128& a, const U128& b) {
@@ -1187,7 +1187,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorDeinterleaveEvenLower32, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorDeinterleaveOddLower(size_t esize, const U128& a, const U128& b) {
@@ -1199,7 +1199,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorDeinterleaveOddLower32, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorEor(const U128& a, const U128& b) {
@@ -1219,7 +1219,7 @@ public:
         case 128:
             return Inst<U128>(Opcode::VectorEqual128, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorExtract(const U128& a, const U128& b, size_t position) {
@@ -1243,7 +1243,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorGreaterS64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorGreaterEqualSigned(size_t esize, const U128& a, const U128& b) {
@@ -1267,7 +1267,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorHalvingAddS32, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorHalvingAddUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1279,7 +1279,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorHalvingAddU32, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorHalvingSubSigned(size_t esize, const U128& a, const U128& b) {
@@ -1291,7 +1291,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorHalvingSubS32, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorHalvingSubUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1303,7 +1303,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorHalvingSubU32, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorInterleaveLower(size_t esize, const U128& a, const U128& b) {
@@ -1317,7 +1317,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorInterleaveLower64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorInterleaveUpper(size_t esize, const U128& a, const U128& b) {
@@ -1331,7 +1331,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorInterleaveUpper64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorLessEqualSigned(size_t esize, const U128& a, const U128& b) {
@@ -1361,7 +1361,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorLogicalShiftLeft64, a, Imm8(shift_amount));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount) {
@@ -1375,7 +1375,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorLogicalShiftRight64, a, Imm8(shift_amount));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorLogicalVShift(size_t esize, const U128& a, const U128& b) {
@@ -1389,7 +1389,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorLogicalVShift64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorMaxSigned(size_t esize, const U128& a, const U128& b) {
@@ -1403,7 +1403,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorMaxS64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorMaxUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1417,7 +1417,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorMaxU64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorMinSigned(size_t esize, const U128& a, const U128& b) {
@@ -1431,7 +1431,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorMinS64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorMinUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1445,7 +1445,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorMinU64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorMultiply(size_t esize, const U128& a, const U128& b) {
@@ -1459,7 +1459,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorMultiply64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorMultiplySignedWiden(size_t esize, const U128& a, const U128& b) {
@@ -1471,7 +1471,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorMultiplySignedWiden32, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorMultiplyUnsignedWiden(size_t esize, const U128& a, const U128& b) {
@@ -1483,7 +1483,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorMultiplyUnsignedWiden32, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorNarrow(size_t original_esize, const U128& a) {
@@ -1495,7 +1495,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorNarrow64, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorNot(const U128& a) {
@@ -1517,7 +1517,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorPairedAdd64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorPairedAddLower(size_t esize, const U128& a, const U128& b) {
@@ -1529,7 +1529,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedAddLower32, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorPairedAddSignedWiden(size_t original_esize, const U128& a) {
@@ -1541,7 +1541,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedAddSignedWiden32, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorPairedAddUnsignedWiden(size_t original_esize, const U128& a) {
@@ -1553,7 +1553,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedAddUnsignedWiden32, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorPairedMaxSigned(size_t esize, const U128& a, const U128& b) {
@@ -1565,7 +1565,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMaxS32, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1578,7 +1578,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMaxU32, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1591,7 +1591,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMinS32, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1604,7 +1604,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMinU32, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1617,7 +1617,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMaxLowerS32, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1630,7 +1630,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMaxLowerU32, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1643,7 +1643,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMinLowerS32, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1656,7 +1656,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMinLowerU32, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1671,7 +1671,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorPolynomialMultiplyLong64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1688,7 +1688,7 @@ public:
         case 8:
             return Inst<U128>(Opcode::VectorReverseElementsInHalfGroups8, a);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1699,7 +1699,7 @@ public:
         case 16:
             return Inst<U128>(Opcode::VectorReverseElementsInWordGroups16, a);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1712,7 +1712,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorReverseElementsInLongGroups32, a);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1728,7 +1728,7 @@ public:
             return Inst<U128>(Opcode::VectorReduceAdd64, a);
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorRotateLeft(size_t esize, const U128& a, u8 amount) {
@@ -1768,7 +1768,7 @@ public:
             return Inst<U128>(Opcode::VectorRoundingHalvingAddS32, a, b);
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorRoundingHalvingAddUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1781,7 +1781,7 @@ public:
             return Inst<U128>(Opcode::VectorRoundingHalvingAddU32, a, b);
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorRoundingShiftLeftSigned(size_t esize, const U128& a, const U128& b) {
@@ -1796,7 +1796,7 @@ public:
             return Inst<U128>(Opcode::VectorRoundingShiftLeftS64, a, b);
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorRoundingShiftLeftUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1811,7 +1811,7 @@ public:
             return Inst<U128>(Opcode::VectorRoundingShiftLeftU64, a, b);
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorSignExtend(size_t original_esize, const U128& a) {
@@ -1825,7 +1825,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignExtend64, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorSignedAbsoluteDifference(size_t esize, const U128& a, const U128& b) {
@@ -1837,7 +1837,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorSignedAbsoluteDifference32, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     UpperAndLower VectorSignedMultiply(size_t esize, const U128& a, const U128& b) {
@@ -1848,7 +1848,7 @@ public:
             case 32:
                 return Inst(Opcode::VectorSignedMultiply32, a, b);
             }
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }();
 
         return {
@@ -1868,7 +1868,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedAbs64, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorSignedSaturatedAccumulateUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1882,7 +1882,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedAccumulateUnsigned64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorSignedSaturatedDoublingMultiplyHigh(size_t esize, const U128& a, const U128& b) {
@@ -1892,7 +1892,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorSignedSaturatedDoublingMultiplyHigh32, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1903,7 +1903,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorSignedSaturatedDoublingMultiplyHighRounding32, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -1914,7 +1914,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorSignedSaturatedDoublingMultiplyLong32, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorSignedSaturatedNarrowToSigned(size_t original_esize, const U128& a) {
@@ -1926,7 +1926,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedNarrowToSigned64, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorSignedSaturatedNarrowToUnsigned(size_t original_esize, const U128& a) {
@@ -1938,7 +1938,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedNarrowToUnsigned64, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorSignedSaturatedNeg(size_t esize, const U128& a) {
@@ -1952,7 +1952,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedNeg64, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorSignedSaturatedShiftLeft(size_t esize, const U128& a, const U128& b) {
@@ -1966,7 +1966,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedShiftLeft64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorSignedSaturatedShiftLeftUnsigned(size_t esize, const U128& a, u8 shift_amount) {
@@ -1981,7 +1981,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedShiftLeftUnsigned64, a, Imm8(shift_amount));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorSub(size_t esize, const U128& a, const U128& b) {
@@ -1995,7 +1995,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSub64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     Table VectorTable(std::vector<U64> values) {
@@ -2031,7 +2031,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorTranspose64, a, b, Imm1(part));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorUnsignedAbsoluteDifference(size_t esize, const U128& a, const U128& b) {
@@ -2043,7 +2043,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorUnsignedAbsoluteDifference32, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorUnsignedRecipEstimate(const U128& a) {
@@ -2065,7 +2065,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorUnsignedSaturatedAccumulateSigned64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorUnsignedSaturatedNarrow(size_t esize, const U128& a) {
@@ -2077,7 +2077,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorUnsignedSaturatedNarrow64, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorUnsignedSaturatedShiftLeft(size_t esize, const U128& a, const U128& b) {
@@ -2091,7 +2091,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorUnsignedSaturatedShiftLeft64, a, b);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorZeroExtend(size_t original_esize, const U128& a) {
@@ -2105,7 +2105,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorZeroExtend64, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 VectorZeroUpper(const U128& a) {
@@ -2125,7 +2125,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPAbs64, a);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2138,7 +2138,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPAdd64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2153,7 +2153,7 @@ public:
         case Type::U64:
             return Inst<NZCV>(Opcode::FPCompare64, a, b, exc_on_qnan_imm);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2166,7 +2166,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPDiv64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2179,7 +2179,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMax64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2192,7 +2192,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMaxNumeric64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2205,7 +2205,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMin64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2218,7 +2218,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMinNumeric64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2231,7 +2231,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMul64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2246,7 +2246,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMulAdd64, a, b, c);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2261,7 +2261,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMulSub64, a, b, c);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2274,7 +2274,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMulX64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2287,7 +2287,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPNeg64, a);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2300,7 +2300,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPRecipEstimate64, a);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2313,7 +2313,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPRecipExponent64, a);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2328,7 +2328,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPRecipStepFused64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2344,7 +2344,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPRoundInt64, a, rounding_value, exact_imm);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2357,7 +2357,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPRSqrtEstimate64, a);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2372,7 +2372,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPRSqrtStepFused64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2383,7 +2383,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPSqrt64, a);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2396,7 +2396,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPSub64, a, b);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2438,7 +2438,7 @@ public:
         case Type::U64:
             return Inst<U16>(Opcode::FPDoubleToFixedS16, a, fbits_imm, rounding_imm);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2456,7 +2456,7 @@ public:
         case Type::U64:
             return Inst<U32>(Opcode::FPDoubleToFixedS32, a, fbits_imm, rounding_imm);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2474,7 +2474,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPDoubleToFixedS64, a, fbits_imm, rounding_imm);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2492,7 +2492,7 @@ public:
         case Type::U64:
             return Inst<U16>(Opcode::FPDoubleToFixedU16, a, fbits_imm, rounding_imm);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2510,7 +2510,7 @@ public:
         case Type::U64:
             return Inst<U32>(Opcode::FPDoubleToFixedU32, a, fbits_imm, rounding_imm);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2528,7 +2528,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPDoubleToFixedU64, a, fbits_imm, rounding_imm);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2546,7 +2546,7 @@ public:
         case Type::U64:
             return Inst<U32>(Opcode::FPFixedS64ToSingle, a, fbits_imm, rounding_imm);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2564,7 +2564,7 @@ public:
         case Type::U64:
             return Inst<U32>(Opcode::FPFixedU64ToSingle, a, fbits_imm, rounding_imm);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2582,7 +2582,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPFixedS64ToDouble, a, fbits_imm, rounding_imm);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2600,7 +2600,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPFixedU64ToDouble, a, fbits_imm, rounding_imm);
         default:
-            std::terminate(); //unreachable
+            assert(false && "unreachable");
         }
     }
 
@@ -2613,7 +2613,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorAbs64, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2623,7 +2623,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorAdd64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorDiv(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2633,7 +2633,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorDiv64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorEqual(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2645,7 +2645,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorEqual64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorFromHalf(size_t esize, const U128& a, FP::RoundingMode rounding, bool fpcr_controlled = true) {
@@ -2661,7 +2661,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorFromSignedFixed64, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)), Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorFromUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) {
@@ -2672,7 +2672,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorFromUnsignedFixed64, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)), Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorGreater(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2682,7 +2682,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorGreater64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorGreaterEqual(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2692,7 +2692,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorGreaterEqual64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorMax(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2702,7 +2702,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMax64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorMaxNumeric(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2712,7 +2712,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMaxNumeric64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorMin(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2722,7 +2722,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMin64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorMinNumeric(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2732,7 +2732,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMinNumeric64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorMul(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2742,7 +2742,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMul64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorMulAdd(size_t esize, const U128& a, const U128& b, const U128& c, bool fpcr_controlled = true) {
@@ -2754,7 +2754,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMulAdd64, a, b, c, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorMulX(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2764,7 +2764,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMulX64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorNeg(size_t esize, const U128& a) {
@@ -2776,7 +2776,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorNeg64, a);
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2786,7 +2786,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorPairedAdd64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2796,7 +2796,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorPairedAddLower64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled = true) {
@@ -2808,7 +2808,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorRecipEstimate64, a, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2820,7 +2820,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorRecipStepFused64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact, bool fpcr_controlled = true) {
@@ -2835,7 +2835,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorRoundInt64, operand, rounding_imm, exact_imm, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorRSqrtEstimate(size_t esize, const U128& a, bool fpcr_controlled = true) {
@@ -2847,7 +2847,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorRSqrtEstimate64, a, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2859,7 +2859,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorRSqrtStepFused64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorSqrt(size_t esize, const U128& a, bool fpcr_controlled = true) {
@@ -2869,7 +2869,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorSqrt64, a, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorSub(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2879,7 +2879,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorSub64, a, b, Imm1(fpcr_controlled));
         }
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorToHalf(size_t esize, const U128& a, FP::RoundingMode rounding, bool fpcr_controlled = true) {
@@ -2902,7 +2902,7 @@ public:
             return Inst<U128>(Opcode::FPVectorToSignedFixed64, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled));
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     U128 FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) {
@@ -2920,7 +2920,7 @@ public:
             return Inst<U128>(Opcode::FPVectorToUnsignedFixed64, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled));
         }
 
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     void Breakpoint() {
diff --git a/src/dynarmic/src/dynarmic/ir/value.cpp b/src/dynarmic/src/dynarmic/ir/value.cpp
index faf1c445fe..541218f9fd 100644
--- a/src/dynarmic/src/dynarmic/ir/value.cpp
+++ b/src/dynarmic/src/dynarmic/ir/value.cpp
@@ -220,7 +220,7 @@ s64 Value::GetImmediateAsS64() const {
     case IR::Type::U64:
         return s64(GetU64());
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
@@ -238,7 +238,7 @@ u64 Value::GetImmediateAsU64() const {
     case IR::Type::U64:
         return u64(GetU64());
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 }
 
diff --git a/src/dynarmic/tests/A32/fuzz_arm.cpp b/src/dynarmic/tests/A32/fuzz_arm.cpp
index b5c0ff47db..d86b80041a 100644
--- a/src/dynarmic/tests/A32/fuzz_arm.cpp
+++ b/src/dynarmic/tests/A32/fuzz_arm.cpp
@@ -273,7 +273,7 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
             } else if (bitstring.substr(0, 8) == "11110100") {
                 bitstring.replace(0, 8, "11111001");
             } else {
-                std::terminate(); //unreachable // "Unhandled ASIMD instruction: {} {}", fn, bs);
+                assert(false && "unreachable"); // "Unhandled ASIMD instruction: {} {}", fn, bs);
             }
             if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
                 invalid.emplace_back(InstructionGenerator{bitstring.c_str()});
diff --git a/src/dynarmic/tests/A32/testenv.h b/src/dynarmic/tests/A32/testenv.h
index fe60615dfe..639a08e8c4 100644
--- a/src/dynarmic/tests/A32/testenv.h
+++ b/src/dynarmic/tests/A32/testenv.h
@@ -98,11 +98,11 @@ public:
     }
 
     void CallSVC(std::uint32_t swi) override {
-        std::terminate(); //unreachable //assert(false && "CallSVC({})", swi);
+        assert(false && "unreachable"); //assert(false && "CallSVC({})", swi);
     }
 
     void ExceptionRaised(u32 pc, Dynarmic::A32::Exception /*exception*/) override {
-        std::terminate(); //unreachable //assert(false && "ExceptionRaised({:08x}) code = {:08x}", pc, *MemoryReadCode(pc));
+        assert(false && "unreachable"); //assert(false && "ExceptionRaised({:08x}) code = {:08x}", pc, *MemoryReadCode(pc));
     }
 
     void AddTicks(std::uint64_t ticks) override {
@@ -187,11 +187,11 @@ public:
     }
 
     void CallSVC(std::uint32_t swi) override {
-        std::terminate(); //unreachable //assert(false && "CallSVC({})", swi);
+        assert(false && "unreachable"); //assert(false && "CallSVC({})", swi);
     }
 
     void ExceptionRaised(std::uint32_t pc, Dynarmic::A32::Exception) override {
-        std::terminate(); //unreachable //assert(false && "ExceptionRaised({:016x})", pc);
+        assert(false && "unreachable"); //assert(false && "ExceptionRaised({:016x})", pc);
     }
 
     void AddTicks(std::uint64_t ticks) override {
diff --git a/src/dynarmic/tests/A64/testenv.h b/src/dynarmic/tests/A64/testenv.h
index db8eaa3fa1..1a2839cfea 100644
--- a/src/dynarmic/tests/A64/testenv.h
+++ b/src/dynarmic/tests/A64/testenv.h
@@ -106,11 +106,11 @@ public:
     }
 
     void CallSVC(std::uint32_t swi) override {
-        std::terminate(); //unreachable //assert(false && "CallSVC({})", swi);
+        assert(false && "unreachable"); //assert(false && "CallSVC({})", swi);
     }
 
     void ExceptionRaised(u64 pc, Dynarmic::A64::Exception /*exception*/) override {
-        std::terminate(); //unreachable //assert(false && "ExceptionRaised({:016x})", pc);
+        assert(false && "unreachable"); //assert(false && "ExceptionRaised({:016x})", pc);
     }
 
     void AddTicks(std::uint64_t ticks) override {
@@ -205,11 +205,11 @@ public:
     }
 
     void CallSVC(std::uint32_t swi) override {
-        std::terminate(); //unreachable //assert(false && "CallSVC({})", swi);
+        assert(false && "unreachable"); //assert(false && "CallSVC({})", swi);
     }
 
     void ExceptionRaised(u64 pc, Dynarmic::A64::Exception) override {
-        std::terminate(); //unreachable //assert(false && "ExceptionRaised({:016x})", pc);
+        assert(false && "unreachable"); //assert(false && "ExceptionRaised({:016x})", pc);
     }
 
     void AddTicks(std::uint64_t ticks) override {
diff --git a/src/dynarmic/tests/test_generator.cpp b/src/dynarmic/tests/test_generator.cpp
index b469d327d5..1ae4d55515 100644
--- a/src/dynarmic/tests/test_generator.cpp
+++ b/src/dynarmic/tests/test_generator.cpp
@@ -301,7 +301,7 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
             } else if (bitstring.substr(0, 8) == "11110100") {
                 bitstring.replace(0, 8, "11111001");
             } else {
-                std::terminate(); //unreachable // "Unhandled ASIMD instruction: {} {}", fn, bs);
+                assert(false && "unreachable"); // "Unhandled ASIMD instruction: {} {}", fn, bs);
             }
             if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
                 invalid.emplace_back(InstructionGenerator{bitstring.c_str()});
diff --git a/src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp b/src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp
index 8c1da903ce..8b4b716e21 100644
--- a/src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp
+++ b/src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp
@@ -336,7 +336,7 @@ bool A32Unicorn<TestEnvironment>::MemoryWriteHook(uc_engine* /*uc*/, uc_mem_type
         this_->testenv.MemoryWrite64(start_address, value);
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     return true;
diff --git a/src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp b/src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp
index cab3d5d45b..dd2a034872 100644
--- a/src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp
+++ b/src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp
@@ -242,7 +242,7 @@ bool A64Unicorn::MemoryWriteHook(uc_engine* /*uc*/, uc_mem_type /*type*/, u64 st
         this_->testenv.MemoryWrite64(start_address, value);
         break;
     default:
-        std::terminate(); //unreachable
+        assert(false && "unreachable");
     }
 
     return true;