mirror of
https://github.com/Plexi09/Nadir-Kernel.git
synced 2026-10-20 15:07:27 +02:00
128 lines
3.4 KiB
NASM
128 lines
3.4 KiB
NASM
; Nadir stage-2 entry: 32-bit protected mode -> 64-bit long mode -> C.
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;
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; Entered via a near jump to 0x10000 with a flat code segment (Ring 0,
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; CPL 0 —still the privilege BIOS gave us; no userspace exists yet).
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; Privileged instructions used: cpuid, mov cr4/cr0, rdmsr/wrmsr, lgdt.
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; Fault behavior: no IDT is installed, so any exception here triple-faults
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; and resets the machine. The only graceful failure is a CPU without long
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; mode, which prints an error straight to VGA and halts.
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;
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; Steps: verify long mode exists, identity-map the first 1GB with 2MB
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; pages, enable PAE + LME + paging, reload a GDT with a 64-bit code
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; segment, zero BSS, then call the C entry point kmain (System V ABI).
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; Interrupts stay disabled for the whole sequence.
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bits 32
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section .boot32
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global boot32_entry
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extern kmain
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extern __bss_start
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extern __bss_end
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PML4 equ 0x70000
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PDPT equ 0x71000
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PD equ 0x72000
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STACK64_TOP equ 0x90000
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boot32_entry:
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; --- CPUID: does this CPU do 64-bit long mode? ---
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mov eax, 0x80000000
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cpuid
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cmp eax, 0x80000001
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jb .no_longmode
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mov eax, 0x80000001
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cpuid
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test edx, 1 << 29 ; LM bit
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jz .no_longmode
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; --- page tables: PML4 -> PDPT -> PD, 512 x 2MB identity pages ---
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mov edi, PML4
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xor eax, eax
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mov ecx, 0x1000 ; clear 16KB (tables + slack)
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rep stosd
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mov eax, PDPT
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or eax, 0x03 ; present + writable
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mov [PML4], eax
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mov eax, PD
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or eax, 0x03
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mov [PDPT], eax
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mov ecx, 512
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mov edi, PD
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mov eax, 0x83 ; present + writable + 2MB page
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.fill_pd:
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mov [edi], eax
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add eax, 0x200000
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add edi, 8
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loop .fill_pd
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; --- enable long mode ---
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mov eax, PML4 ; page-walk root (CR3 was 0 until now)
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mov cr3, eax
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mov eax, cr4
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or eax, 1 << 5 ; PAE
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mov cr4, eax
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mov ecx, 0xC0000080 ; IA32_EFER
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rdmsr
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or eax, 1 << 8 ; LME
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wrmsr
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mov eax, cr0
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or eax, 1 << 31 ; PG: paging on, long mode active
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mov cr0, eax
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lgdt [gdt64_ptr]
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jmp 0x18:long_entry ; far jump loads the 64-bit code segment
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.no_longmode:
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mov edi, 0xB8000 ; VGA text buffer, line 0
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mov esi, err_nolm
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mov ah, 0x4F ; white on red
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.print:
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lodsb
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test al, al
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jz .die
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stosw
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jmp .print
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.die:
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cli
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.hang:
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hlt
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jmp .hang
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err_nolm db "ERR: CPU has no 64-bit long mode", 0
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; Own GDT: the stage-1 GDT is behind us, so bring null/code32/data32 plus
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; the 64-bit code+data segments this stage needs.
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align 8
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gdt64:
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dq 0x0000000000000000
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dq 0x00CF9A000000FFFF ; code32 (kept for completeness)
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dq 0x00CF92000000FFFF ; data32
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dq 0x00209A0000000000 ; code64: L=1, exec/read
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dq 0x0000920000000000 ; data64: read/write
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gdt64_end:
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gdt64_ptr:
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dw gdt64_end - gdt64 - 1
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dd gdt64
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; ---------------------------------------------------------------------------
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bits 64
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long_entry:
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mov ax, 0x20 ; 64-bit data segment
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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mov rsp, STACK64_TOP
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mov rdi, __bss_start ; zero BSS (uninitialized C statics)
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mov rcx, __bss_end
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sub rcx, rdi
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xor eax, eax
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rep stosb
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call kmain ; first C code — does not return
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cli
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.hang:
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hlt
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jmp .hang
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