mirror of
https://github.com/Plexi09/Nadir-Kernel.git
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107 lines
2.5 KiB
NASM
107 lines
2.5 KiB
NASM
; Nadir exception stubs: vectors 0-31 -> exception_handler.
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;
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; Runs in 64-bit long mode at Ring 0 (CPL 0). Entered by the CPU with
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; IF cleared (interrupt gate); no privilege change, so the CPU pushed
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; RIP/CS/RFLAGS plus an error code only on vectors 8, 10-14, 17, 21.
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; Fault behavior: a fault here (before the IDT is loaded, or inside the
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; handler) triple-faults. Never returns: the C handler halts.
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;
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; Contract with include/idt.h `struct interrupt_frame`: each stub leaves
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; [vector, error] on the stack (pushing a dummy 0 where the CPU did not),
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; then isr_common pushes the 15 GPRs and calls the C handler with RDI
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; pointing at the frame. Field order must stay in sync. Interrupts stay
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; disabled; -mno-red-zone makes the pushes safe.
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bits 64
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section .text
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global isr_stub_table
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extern exception_handler
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; Vectors without a CPU error code: normalize with a dummy 0.
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%macro ISR_NOERR 1
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global isr_stub_%1
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isr_stub_%1:
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push 0
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push %1
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jmp isr_common
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%endmacro
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; Vectors where the CPU already pushed an error code: only push the vector.
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%macro ISR_ERR 1
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global isr_stub_%1
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isr_stub_%1:
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push %1
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jmp isr_common
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%endmacro
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ISR_NOERR 0
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ISR_NOERR 1
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ISR_NOERR 2
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ISR_NOERR 3
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ISR_NOERR 4
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ISR_NOERR 5
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ISR_NOERR 6
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ISR_NOERR 7
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ISR_ERR 8
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ISR_NOERR 9
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ISR_ERR 10
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ISR_ERR 11
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ISR_ERR 12
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ISR_ERR 13
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ISR_ERR 14
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ISR_NOERR 15
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ISR_NOERR 16
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ISR_ERR 17
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ISR_NOERR 18
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ISR_NOERR 19
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ISR_NOERR 20
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ISR_ERR 21
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ISR_NOERR 22
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ISR_NOERR 23
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ISR_NOERR 24
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ISR_NOERR 25
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ISR_NOERR 26
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ISR_NOERR 27
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ISR_NOERR 28
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ISR_NOERR 29
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ISR_NOERR 30
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ISR_NOERR 31
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; Common entry: save GPRs, call void exception_handler(frame in RDI), halt
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; if it ever returns (it must not).
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isr_common:
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push rax
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push rbx
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push rcx
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push rdx
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push rsi
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push rdi
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push rbp
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push r8
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push r9
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push r10
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push r11
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push r12
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push r13
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push r14
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push r15
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mov rdi, rsp
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call exception_handler
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; Unreachable in practice; park the CPU if the handler returns.
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cli
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.hang:
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hlt
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jmp .hang
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section .rodata
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align 8
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isr_stub_table:
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dq isr_stub_0, isr_stub_1, isr_stub_2, isr_stub_3
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dq isr_stub_4, isr_stub_5, isr_stub_6, isr_stub_7
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dq isr_stub_8, isr_stub_9, isr_stub_10, isr_stub_11
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dq isr_stub_12, isr_stub_13, isr_stub_14, isr_stub_15
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dq isr_stub_16, isr_stub_17, isr_stub_18, isr_stub_19
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dq isr_stub_20, isr_stub_21, isr_stub_22, isr_stub_23
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dq isr_stub_24, isr_stub_25, isr_stub_26, isr_stub_27
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dq isr_stub_28, isr_stub_29, isr_stub_30, isr_stub_31
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