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https://github.com/Plexi09/Nadir-Kernel.git
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95 lines
3.2 KiB
C
95 lines
3.2 KiB
C
/* 8254 PIT timer driver (see pit.h).
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*
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* Programs channel 0 in mode 3 (square-wave generator) at 100Hz on IRQ0.
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*
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* Why 1193182Hz base: the PIT input clock is the IBM-PC crystal frequency
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* (14.31818MHz / 12); every PC-compatible PIT ticks at this rate, so the
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* divisor for N Hz is always 1193182 / N.
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* Why mode 3: square-wave output stays high/low for half the period and
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* retriggers the IRQ line cleanly each cycle; mode 2 (rate generator)
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* emits narrow pulses that are fine too, but mode 3 is the conventional
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* choice for periodic system ticks on channel 0.
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* Why volatile + no locking: single-core kernel; s_ticks is written only
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* in IRQ0 context and read in mainline code. `volatile` keeps the compiler
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* from caching the counter across the hlt loop, and on x86-64 an aligned
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* 64-bit load/store is atomic, so no spinlock is needed while IF gates the
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* writer.
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*/
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#include <stdint.h>
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#include "idt.h"
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#include "io.h"
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#include "pit.h"
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#define PIT_CMD 0x43U
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#define PIT_CH0 0x40U
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/* Ch0, lobyte/hibyte access, mode 3 square-wave, binary (not BCD). */
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#define PIT_CMD_CH0_MODE3 0x36U
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/* Compile-time guard: a zero divisor would mean 65536 to the hardware and
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* silently run at ~18Hz instead of PIT_HZ. Frequency is fixed on purpose. */
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_Static_assert(PIT_DIVISOR != 0, "PIT divisor must not be zero");
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_Static_assert(PIT_DIVISOR <= 0xFFFFU, "PIT divisor must fit in 16 bits");
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/* Port I/O is owned by include/io.h (single owner); irq_register_handler
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* is owned by idt.c via include/idt.h. */
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/* Monotonic tick counter: written in IRQ context. */
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static volatile uint64_t s_ticks;
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/* pit_init is idempotent; re-entry after the first programming is a no-op. */
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static uint8_t s_initialized;
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void pit_init(void)
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{
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uint16_t divisor;
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uint8_t lo;
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uint8_t hi;
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if (s_initialized != 0) {
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return;
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}
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/* No cli/sti here on purpose: latch programming is two plain outb
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* writes (safe with IF=0 at boot) and interrupt policy belongs to the
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* caller (kmain integrator), which unmasks IRQ0 and stis afterwards. */
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divisor = (uint16_t)PIT_DIVISOR;
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lo = (uint8_t)(divisor & 0xFFU);
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hi = (uint8_t)((divisor >> 8) & 0xFFU);
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/* Latch order matters: command byte first selects ch0 + lobyte/hibyte
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* mode, then the divisor follows low byte first, high byte second. */
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outb(PIT_CMD, PIT_CMD_CH0_MODE3);
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outb(PIT_CH0, lo);
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outb(PIT_CH0, hi);
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/* Strong idt.h registration: IRQ0 -> vector 32 wires pit_on_tick. */
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irq_register_handler(PIT_IRQ, pit_on_tick);
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s_initialized = 1;
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}
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void pit_on_tick(void)
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{
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/* Single increment async-safe, no logging or port I/O here. The PIC
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* EOI is owned by the IRQ dispatcher not this driver. */
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s_ticks++;
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}
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uint64_t pit_ticks(void)
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{
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return s_ticks;
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}
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void pit_sleep(uint64_t ticks)
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{
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uint64_t start = s_ticks;
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/* hlt (not a spin loop) so the CPU sleeps until the next interrupt.
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* Assumes IF=1 and IRQ0 unmasked; with IF=0 this would halt forever,
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* which is why pit_init leaves interrupt policy to the caller. The
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* unsigned delta keeps working if s_ticks wraps mid-sleep. */
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while ((s_ticks - start) < ticks) {
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__asm__ volatile("hlt");
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}
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}
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