mirror of
https://github.com/Plexi09/Nadir-Kernel.git
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115 lines
3.7 KiB
C
115 lines
3.7 KiB
C
/* Nadir IDT base: 32 CPU-exception gates + fault printer.
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*
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* Runs in 64-bit long mode at Ring 0 (CPL 0) with the stage-2 GDT
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* (kernel code selector 0x18). Privileged primitive: `lidt` in
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* idt_init(). Fault behavior: before idt_init() any fault
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* triple-faults; after, vectors 0-31 print diagnostics and halt.
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* Vectors 32-255 stay not-present until the PIC is remapped.
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* IF stays cleared; exceptions fire regardless of IF.
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*/
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#include <stdint.h>
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#include "console.h"
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#include "idt.h"
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/* 64-bit interrupt gate descriptor (Intel SDM Vol. 3, IDT gate). */
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struct idt_entry {
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uint16_t offset_low;
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uint16_t selector;
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uint8_t ist;
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uint8_t type_attr;
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uint16_t offset_mid;
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uint32_t offset_high;
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uint32_t reserved;
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} __attribute__((packed));
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/* IDTR image for `lidt`. */
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struct idtr {
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uint16_t limit;
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uint64_t base;
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} __attribute__((packed));
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/* Gate flags: present, DPL 0, 64-bit interrupt gate (0xE). */
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#define IDT_FLAG_PRESENT_INT 0x8EU
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/* Kernel code segment from the stage-2 GDT (entry.asm). */
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#define KERNEL_CS 0x18U
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/* Full 256-entry table, 16-byte aligned as the CPU prefers. BSS. */
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static struct idt_entry idt[256] __attribute__((aligned(16)));
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static struct idtr idtr;
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/* Stub addresses from isr.asm, one per exception vector 0-31. */
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extern uint64_t isr_stub_table[IDT_EXCEPTION_COUNT];
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/* Install one gate: handler address + segment + IST index + flags. */
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static void idt_set_gate(uint8_t vector, uint64_t handler, uint16_t selector,
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uint8_t ist, uint8_t flags)
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{
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struct idt_entry *e = &idt[vector];
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e->offset_low = (uint16_t)(handler & 0xFFFFU);
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e->selector = selector;
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e->ist = ist & 0x07U;
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e->type_attr = flags;
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e->offset_mid = (uint16_t)((handler >> 16) & 0xFFFFU);
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e->offset_high = (uint32_t)((handler >> 32) & 0xFFFFFFFFU);
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e->reserved = 0;
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}
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/* Human-readable names for vectors 0-31 (Intel SDM Vol. 3). */
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static const char *const exception_names[IDT_EXCEPTION_COUNT] = {
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"Divide Error (#DE)", "Debug Exception (#DB)", "NMI",
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"Breakpoint (#BP)", "Overflow (#OF)", "Bound Range (#BR)",
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"Invalid Opcode (#UD)", "Device Not Available (#NM)",
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"Double Fault (#DF)", "Coprocessor Segment Overrun",
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"Invalid TSS (#TS)", "Segment Not Present (#NP)",
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"Stack-Segment Fault (#SS)", "General Protection (#GP)",
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"Page Fault (#PF)", "Reserved (15)",
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"x87 Floating-Point (#MF)", "Alignment Check (#AC)",
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"Machine Check (#MC)", "SIMD Floating-Point (#XM)",
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"Virtualization (#VE)", "Control Protection (#CP)",
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"Reserved (22)", "Reserved (23)", "Reserved (24)", "Reserved (25)",
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"Reserved (26)", "Reserved (27)", "Hypervisor Injection (#HV)",
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"VMM Communication (#VC)", "Security Exception (#SX)", "Reserved (31)",
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};
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void idt_init(void)
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{
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for (uint16_t i = 0; i < IDT_EXCEPTION_COUNT; i++) {
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idt_set_gate((uint8_t)i, isr_stub_table[i], KERNEL_CS, 0,
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IDT_FLAG_PRESENT_INT);
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}
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idtr.limit = (uint16_t)(sizeof(idt) - 1);
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idtr.base = (uint64_t)&idt[0];
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__asm__ volatile("lidt %0" ::"m"(idtr) : "memory");
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}
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void exception_handler(struct interrupt_frame *frame)
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{
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uint64_t vector = frame->vector;
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const char *name = "Unknown Exception";
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if (vector < IDT_EXCEPTION_COUNT) {
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name = exception_names[vector];
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}
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console_puts("\n*** EXCEPTION: ");
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console_puts(name);
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console_puts(" (vector ");
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console_puthex64(vector);
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console_puts(") ***\nerror: ");
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console_puthex64(frame->error);
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console_puts(" rip: ");
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console_puthex64(frame->rip);
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console_puts(" cs: ");
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console_puthex64(frame->cs);
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console_puts(" rflags: ");
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console_puthex64(frame->rflags);
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console_puts("\nSystem halted.\n");
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for (;;) {
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__asm__ volatile("cli; hlt");
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}
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}
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