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https://github.com/Plexi09/Nadir-Kernel.git
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91 lines
3.3 KiB
C
91 lines
3.3 KiB
C
/* Nadir interrupt IDT + CPU exception entry points.
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*
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* Runs in 64-bit long mode at Ring 0 (CPL 0) with the stage-2 GDT.
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* Privileged primitive: `lidt` in idt_init(). Fault behavior: before
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* idt_init() any exception triple-faults (no IDT); after, CPU vectors
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* 0-31 land in the assembly stubs (isr.asm) and then in
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* exception_handler(), which prints and halts. Vectors 32-47 stay
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* not-present until the 8259 PIC is remapped and idt_install_irqs()
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* installs the IRQ gates; then they land in irq_dispatch(), which
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* sends the PIC EOI and calls the per-IRQ handler (if any).
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* Interrupts stay disabled throughout (IF=0); exceptions still fire.
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* IRQs only fire after the integrator enables them with `sti`.
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*/
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#ifndef NADIR_IDT_H
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#define NADIR_IDT_H
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#include <stdint.h>
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/* Number of CPU exception vectors this base installs (0-31). */
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#define IDT_EXCEPTION_COUNT 32
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/* First remapped IRQ vector (IRQ 0 -> vector 32) and IRQ line count. */
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#define IDT_IRQ_BASE 32
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#define IDT_IRQ_COUNT 16
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/* Stack layout on entry to exception_handler().
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*
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* Built by the CPU (RIP/CS/RFLAGS, plus an error code on vectors
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* 8, 10-14, 17, 21) plus isr.asm: the stub normalizes the stack to
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* [vector, error] and isr_common pushes the 15 general-purpose
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* registers. RDI points at this struct (System V first argument).
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* Field order matches the push order in isr_common — keep in sync.
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*/
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struct interrupt_frame {
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uint64_t r15;
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uint64_t r14;
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uint64_t r13;
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uint64_t r12;
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uint64_t r11;
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uint64_t r10;
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uint64_t r9;
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uint64_t r8;
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uint64_t rbp;
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uint64_t rdi;
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uint64_t rsi;
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uint64_t rdx;
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uint64_t rcx;
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uint64_t rbx;
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uint64_t rax;
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/* Pushed by the stub: exception vector 0-31. */
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uint64_t vector;
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/* CPU-pushed error code, or 0 inserted by the stub. */
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uint64_t error;
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/* Pushed by the CPU. */
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uint64_t rip;
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uint64_t cs;
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uint64_t rflags;
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/* Pushed by the CPU only on a privilege change; garbage for
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* kernel-mode faults */
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uint64_t rsp;
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uint64_t ss;
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};
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/* Build the IDT (vectors 0-31 -> isr stubs) and load it with `lidt`.
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* Ring 0 only. Leaves IF cleared; returns with exceptions catchable. */
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void idt_init(void);
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/* C entry point for vectors 0-31, called from isr_common with the
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* frame above. Prints vector/error/RIP and halts; never returns. */
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void exception_handler(struct interrupt_frame *frame);
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/* C entry point for vectors 32-47, called from irq_common with the
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* same frame layout (vector = 32 + irq, error = 0 dummy). Runs at
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* Ring 0 with IF cleared; sends the PIC EOI and calls the handler
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* registered for that IRQ, if any. Spurious vectors outside 32-47
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* are ignored. */
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void irq_dispatch(struct interrupt_frame *frame);
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/* Register `handler` for IRQ line `irq` (0-15); NULL unregisters.
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* Preconditions: Ring 0, `irq` < 16 (out-of-range calls ignored).
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* Failure modes: none; takes effect on the next IRQ after return. */
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void irq_register_handler(uint8_t irq, void (*handler)(void));
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/* Install the 16 IRQ gates (vectors 32-47 -> irq stubs) with selector
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* 0x18 and flags 0x8E (present, DPL 0, 64-bit interrupt gate).
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* Preconditions: Ring 0, idt_init() already ran, PIC already remapped
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* via pic_remap(). Leaves IF cleared. Failure modes: none. */
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void idt_install_irqs(void);
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#endif /* NADIR_IDT_H */
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