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https://github.com/Plexi09/Nadir-Kernel.git
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47 lines
1.6 KiB
C
47 lines
1.6 KiB
C
/* Nadir x86 port I/O primitives (inb/outb/io_wait).
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*
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* Runs in 64-bit long mode at Ring 0 (CPL 0) with the stage-2 GDT.
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* Privileged instructions: `in`/`out` trap with #GP(0) when CPL > IOPL,
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* so these helpers are Ring 0 only and must never be exposed to
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* userspace. Fault behavior: a bad port number cannot fault by itself
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* (unused ports read back 0xFF or are ignored); a fault here means the
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* caller programmed the wrong device, not a CPU trap.
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* Interrupts stay disabled by the caller where timing matters; these
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* helpers do not touch IF themselves.
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*/
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#ifndef NADIR_IO_H
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#define NADIR_IO_H
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#include <stdint.h>
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/* Read one byte from ISA port `port`.
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* Preconditions: CPL 0, port is a valid x86 I/O address (0-0xFFFF).
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* Failure modes: none (returns bus value; 0xFF on unmapped ports). */
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static inline uint8_t inb(uint16_t port)
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{
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uint8_t value;
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__asm__ volatile("inb %1, %0" : "=a"(value) : "Nd"(port));
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return value;
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}
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/* Write byte `value` to ISA port `port`.
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* Preconditions: CPL 0, port is writable for this device.
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* Failure modes: none from the CPU; wrong port = device misbehavior. */
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static inline void outb(uint16_t port, uint8_t value)
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{
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__asm__ volatile("outb %0, %1" ::"a"(value), "Nd"(port));
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}
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/* Tiny delay for legacy ISA devices (writes to unused port 0x80).
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*
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* WHY: the 8259 PIC and other slow devices need ~1us between back to
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* back command bytes; port 0x80 is the conventional throwaway delay.
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* Preconditions: CPL 0. Failure modes: none. */
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static inline void io_wait(void)
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{
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outb(0x80U, 0U);
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}
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#endif /* NADIR_IO_H */
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