Added missing vectors

include/idt.h

@@ -4,9 +4,12 @@
  * Privileged primitive: `lidt` in idt_init(). Fault behavior: before
  * idt_init() any exception triple-faults (no IDT); after, CPU vectors
  * 0-31 land in the assembly stubs (isr.asm) and then in
- * exception_handler(), which prints and halts. Vectors 32-255 are left
- * zero (not present) on purpose because PIC remap + IRQ handling is a later step.
+ * exception_handler(), which prints and halts. Vectors 32-47 stay
+ * not-present until the 8259 PIC is remapped and idt_install_irqs()
+ * installs the IRQ gates; then they land in irq_dispatch(), which
+ * sends the PIC EOI and calls the per-IRQ handler (if any).
  * Interrupts stay disabled throughout (IF=0); exceptions still fire.
+ * IRQs only fire after the integrator enables them with `sti`.
  */
 
 #ifndef NADIR_IDT_H
@@ -17,6 +20,10 @@
 /* Number of CPU exception vectors this base installs (0-31). */
 #define IDT_EXCEPTION_COUNT 32
 
+/* First remapped IRQ vector (IRQ 0 -> vector 32) and IRQ line count. */
+#define IDT_IRQ_BASE 32
+#define IDT_IRQ_COUNT 16
+
 /* Stack layout on entry to exception_handler().
  *
  * Built by the CPU (RIP/CS/RFLAGS, plus an error code on vectors
@@ -63,4 +70,22 @@ void idt_init(void);
  * frame above. Prints vector/error/RIP and halts; never returns. */
 void exception_handler(struct interrupt_frame *frame);
 
+/* C entry point for vectors 32-47, called from irq_common with the
+ * same frame layout (vector = 32 + irq, error = 0 dummy). Runs at
+ * Ring 0 with IF cleared; sends the PIC EOI and calls the handler
+ * registered for that IRQ, if any. Spurious vectors outside 32-47
+ * are ignored. */
+void irq_dispatch(struct interrupt_frame *frame);
+
+/* Register `handler` for IRQ line `irq` (0-15); NULL unregisters.
+ * Preconditions: Ring 0, `irq` < 16 (out-of-range calls ignored).
+ * Failure modes: none; takes effect on the next IRQ after return. */
+void irq_register_handler(uint8_t irq, void (*handler)(void));
+
+/* Install the 16 IRQ gates (vectors 32-47 -> irq stubs) with selector
+ * 0x18 and flags 0x8E (present, DPL 0, 64-bit interrupt gate).
+ * Preconditions: Ring 0, idt_init() already ran, PIC already remapped
+ * via pic_remap(). Leaves IF cleared. Failure modes: none. */
+void idt_install_irqs(void);
+
 #endif /* NADIR_IDT_H */

kernel/arch/x86_64/idt.c

@@ -4,14 +4,17 @@
  * (kernel code selector 0x18). Privileged primitive: `lidt` in
  * idt_init(). Fault behavior: before idt_init() any fault
  * triple-faults; after, vectors 0-31 print diagnostics and halt.
- * Vectors 32-255 stay not-present until the PIC is remapped.
- * IF stays cleared; exceptions fire regardless of IF.
+ * Vectors 32-47 stay not-present until pic_remap() +
+ * idt_install_irqs() install the IRQ gates; vectors 48-255 stay
+ * not-present (no APIC yet). IF stays cleared; exceptions fire
+ * regardless of IF, IRQs only after the integrator runs `sti`.
  */
 
 #include <stdint.h>
 
 #include "console.h"
 #include "idt.h"
+#include "pic.h"
 
 /* 64-bit interrupt gate descriptor (Intel SDM Vol. 3, IDT gate). */
 struct idt_entry {
@@ -42,6 +45,14 @@ static struct idtr idtr;
 /* Stub addresses from isr.asm, one per exception vector 0-31. */
 extern uint64_t isr_stub_table[IDT_EXCEPTION_COUNT];
 
+/* Stub addresses from isr.asm, one per remapped IRQ vector 32-47. */
+extern uint64_t irq_stub_table[IDT_IRQ_COUNT];
+
+/* Per-IRQ handlers for lines 0-15; NULL means "EOI only".
+ * WHY a plain table: one subsystem per file — device drivers own
+ * their logic and only register a callback here. BSS-zeroed. */
+static void (*irq_handlers[IDT_IRQ_COUNT])(void);
+
 /* Install one gate: handler address + segment + IST index + flags. */
 static void idt_set_gate(uint8_t vector, uint64_t handler, uint16_t selector,
                          uint8_t ist, uint8_t flags)
@@ -86,6 +97,41 @@ void idt_init(void)
     __asm__ volatile("lidt %0" ::"m"(idtr) : "memory");
 }
 
+void idt_install_irqs(void)
+{
+    for (uint16_t i = 0; i < IDT_IRQ_COUNT; i++) {
+        idt_set_gate((uint8_t)(IDT_IRQ_BASE + i), irq_stub_table[i],
+                     KERNEL_CS, 0, IDT_FLAG_PRESENT_INT);
+    }
+}
+
+void irq_register_handler(uint8_t irq, void (*handler)(void))
+{
+    if (irq >= IDT_IRQ_COUNT) {
+        return;
+    }
+    irq_handlers[irq] = handler;
+}
+
+void irq_dispatch(struct interrupt_frame *frame)
+{
+    uint64_t vector = frame->vector;
+    uint8_t irq;
+
+    if (vector < IDT_IRQ_BASE || vector >= IDT_IRQ_BASE + IDT_IRQ_COUNT) {
+        return;
+    }
+    irq = (uint8_t)(vector - IDT_IRQ_BASE);
+
+    /* WHY handler before EOI: the EOI re-arms the (edge-triggered) PIC
+     * line, so acking first would let the same IRQ re-enter before the
+     * driver finished. A NULL slot just gets an EOI. */
+    if (irq_handlers[irq] != 0) {
+        irq_handlers[irq]();
+    }
+    pic_eoi(irq);
+}
+
 void exception_handler(struct interrupt_frame *frame)
 {
     uint64_t vector = frame->vector;