mirror of
https://github.com/Plexi09/Nadir-Kernel.git
synced 2026-10-20 15:07:27 +02:00
Merge pull request #2 from Plexi09/feature/idt-base
Installs an exceptions-only IDT base: 32 CPU-exception gates (interrupt gates, DPL 0, selector 0x18) with NASM stubs + a C exception_handler that prints vector/error/RIP/CS/RFLAGS and halts. kmain calls idt_init() early, so faults print diagnostics instead of triple-faulting. PIC remap + IRQs are intentionally left for a follow-up
This commit is contained in:
Pierre-Emmanuel Gob.
GitHub
commit
7ee953925a
5 changed files with 301 additions and 4 deletions
10
Makefile
10
Makefile
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@ -20,7 +20,7 @@ CFLAGS := -std=c17 -ffreestanding -nostdlib -fno-builtin \
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-fno-pic -fno-pie -fno-stack-protector \
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-Wall -Wextra -Werror -O2 -Iinclude
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OBJS := $(BUILD)/entry.o $(BUILD)/kmain.o $(BUILD)/console.o
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OBJS := $(BUILD)/entry.o $(BUILD)/isr.o $(BUILD)/kmain.o $(BUILD)/console.o $(BUILD)/idt.o
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all: $(IMG)
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@ -30,12 +30,18 @@ $(BUILD):
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$(BUILD)/entry.o: $(ARCH_DIR)/entry.asm | $(BUILD)
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$(NASM) -f elf64 $< -o $@
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$(BUILD)/kmain.o: kernel/core/kmain.c include/console.h | $(BUILD)
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$(BUILD)/isr.o: $(ARCH_DIR)/isr.asm | $(BUILD)
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$(NASM) -f elf64 $< -o $@
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$(BUILD)/kmain.o: kernel/core/kmain.c include/console.h include/idt.h | $(BUILD)
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$(CC) $(CFLAGS) -c $< -o $@
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$(BUILD)/console.o: $(ARCH_DIR)/console.c include/console.h | $(BUILD)
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$(CC) $(CFLAGS) -c $< -o $@
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$(BUILD)/idt.o: $(ARCH_DIR)/idt.c include/idt.h include/console.h | $(BUILD)
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$(CC) $(CFLAGS) -c $< -o $@
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$(BUILD)/kernel.elf: $(OBJS) $(ARCH_DIR)/link.ld
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$(LD) -m elf_x86_64 -T $(ARCH_DIR)/link.ld -o $@ $(OBJS)
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66
include/idt.h
Normal file
66
include/idt.h
Normal file
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@ -0,0 +1,66 @@
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/* Nadir interrupt IDT + CPU exception entry points.
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*
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* Runs in 64-bit long mode at Ring 0 (CPL 0) with the stage-2 GDT.
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* Privileged primitive: `lidt` in idt_init(). Fault behavior: before
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* idt_init() any exception triple-faults (no IDT); after, CPU vectors
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* 0-31 land in the assembly stubs (isr.asm) and then in
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* exception_handler(), which prints and halts. Vectors 32-255 are left
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* zero (not present) on purpose because PIC remap + IRQ handling is a later step.
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* Interrupts stay disabled throughout (IF=0); exceptions still fire.
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*/
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#ifndef NADIR_IDT_H
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#define NADIR_IDT_H
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#include <stdint.h>
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/* Number of CPU exception vectors this base installs (0-31). */
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#define IDT_EXCEPTION_COUNT 32
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/* Stack layout on entry to exception_handler().
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*
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* Built by the CPU (RIP/CS/RFLAGS, plus an error code on vectors
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* 8, 10-14, 17, 21) plus isr.asm: the stub normalizes the stack to
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* [vector, error] and isr_common pushes the 15 general-purpose
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* registers. RDI points at this struct (System V first argument).
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* Field order matches the push order in isr_common — keep in sync.
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*/
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struct interrupt_frame {
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uint64_t r15;
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uint64_t r14;
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uint64_t r13;
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uint64_t r12;
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uint64_t r11;
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uint64_t r10;
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uint64_t r9;
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uint64_t r8;
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uint64_t rbp;
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uint64_t rdi;
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uint64_t rsi;
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uint64_t rdx;
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uint64_t rcx;
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uint64_t rbx;
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uint64_t rax;
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/* Pushed by the stub: exception vector 0-31. */
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uint64_t vector;
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/* CPU-pushed error code, or 0 inserted by the stub. */
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uint64_t error;
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/* Pushed by the CPU. */
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uint64_t rip;
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uint64_t cs;
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uint64_t rflags;
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/* Pushed by the CPU only on a privilege change; garbage for
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* kernel-mode faults */
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uint64_t rsp;
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uint64_t ss;
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};
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/* Build the IDT (vectors 0-31 -> isr stubs) and load it with `lidt`.
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* Ring 0 only. Leaves IF cleared; returns with exceptions catchable. */
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void idt_init(void);
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/* C entry point for vectors 0-31, called from isr_common with the
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* frame above. Prints vector/error/RIP and halts; never returns. */
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void exception_handler(struct interrupt_frame *frame);
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#endif /* NADIR_IDT_H */
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115
kernel/arch/x86_64/idt.c
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115
kernel/arch/x86_64/idt.c
Normal file
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@ -0,0 +1,115 @@
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/* Nadir IDT base: 32 CPU-exception gates + fault printer.
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*
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* Runs in 64-bit long mode at Ring 0 (CPL 0) with the stage-2 GDT
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* (kernel code selector 0x18). Privileged primitive: `lidt` in
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* idt_init(). Fault behavior: before idt_init() any fault
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* triple-faults; after, vectors 0-31 print diagnostics and halt.
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* Vectors 32-255 stay not-present until the PIC is remapped.
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* IF stays cleared; exceptions fire regardless of IF.
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*/
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#include <stdint.h>
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#include "console.h"
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#include "idt.h"
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/* 64-bit interrupt gate descriptor (Intel SDM Vol. 3, IDT gate). */
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struct idt_entry {
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uint16_t offset_low;
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uint16_t selector;
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uint8_t ist;
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uint8_t type_attr;
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uint16_t offset_mid;
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uint32_t offset_high;
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uint32_t reserved;
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} __attribute__((packed));
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/* IDTR image for `lidt`. */
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struct idtr {
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uint16_t limit;
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uint64_t base;
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} __attribute__((packed));
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/* Gate flags: present, DPL 0, 64-bit interrupt gate (0xE). */
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#define IDT_FLAG_PRESENT_INT 0x8EU
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/* Kernel code segment from the stage-2 GDT (entry.asm). */
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#define KERNEL_CS 0x18U
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/* Full 256-entry table, 16-byte aligned as the CPU prefers. BSS. */
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static struct idt_entry idt[256] __attribute__((aligned(16)));
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static struct idtr idtr;
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/* Stub addresses from isr.asm, one per exception vector 0-31. */
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extern uint64_t isr_stub_table[IDT_EXCEPTION_COUNT];
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/* Install one gate: handler address + segment + IST index + flags. */
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static void idt_set_gate(uint8_t vector, uint64_t handler, uint16_t selector,
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uint8_t ist, uint8_t flags)
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{
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struct idt_entry *e = &idt[vector];
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e->offset_low = (uint16_t)(handler & 0xFFFFU);
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e->selector = selector;
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e->ist = ist & 0x07U;
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e->type_attr = flags;
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e->offset_mid = (uint16_t)((handler >> 16) & 0xFFFFU);
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e->offset_high = (uint32_t)((handler >> 32) & 0xFFFFFFFFU);
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e->reserved = 0;
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}
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/* Human-readable names for vectors 0-31 (Intel SDM Vol. 3). */
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static const char *const exception_names[IDT_EXCEPTION_COUNT] = {
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"Divide Error (#DE)", "Debug Exception (#DB)", "NMI",
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"Breakpoint (#BP)", "Overflow (#OF)", "Bound Range (#BR)",
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"Invalid Opcode (#UD)", "Device Not Available (#NM)",
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"Double Fault (#DF)", "Coprocessor Segment Overrun",
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"Invalid TSS (#TS)", "Segment Not Present (#NP)",
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"Stack-Segment Fault (#SS)", "General Protection (#GP)",
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"Page Fault (#PF)", "Reserved (15)",
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"x87 Floating-Point (#MF)", "Alignment Check (#AC)",
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"Machine Check (#MC)", "SIMD Floating-Point (#XM)",
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"Virtualization (#VE)", "Control Protection (#CP)",
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"Reserved (22)", "Reserved (23)", "Reserved (24)", "Reserved (25)",
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"Reserved (26)", "Reserved (27)", "Hypervisor Injection (#HV)",
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"VMM Communication (#VC)", "Security Exception (#SX)", "Reserved (31)",
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};
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void idt_init(void)
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{
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for (uint16_t i = 0; i < IDT_EXCEPTION_COUNT; i++) {
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idt_set_gate((uint8_t)i, isr_stub_table[i], KERNEL_CS, 0,
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IDT_FLAG_PRESENT_INT);
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}
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idtr.limit = (uint16_t)(sizeof(idt) - 1);
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idtr.base = (uint64_t)&idt[0];
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__asm__ volatile("lidt %0" ::"m"(idtr) : "memory");
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}
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void exception_handler(struct interrupt_frame *frame)
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{
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uint64_t vector = frame->vector;
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const char *name = "Unknown Exception";
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if (vector < IDT_EXCEPTION_COUNT) {
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name = exception_names[vector];
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}
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console_puts("\n*** EXCEPTION: ");
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console_puts(name);
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console_puts(" (vector ");
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console_puthex64(vector);
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console_puts(") ***\nerror: ");
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console_puthex64(frame->error);
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console_puts(" rip: ");
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console_puthex64(frame->rip);
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console_puts(" cs: ");
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console_puthex64(frame->cs);
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console_puts(" rflags: ");
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console_puthex64(frame->rflags);
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console_puts("\nSystem halted.\n");
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for (;;) {
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__asm__ volatile("cli; hlt");
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}
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}
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107
kernel/arch/x86_64/isr.asm
Normal file
107
kernel/arch/x86_64/isr.asm
Normal file
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@ -0,0 +1,107 @@
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; Nadir exception stubs: vectors 0-31 -> exception_handler.
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;
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; Runs in 64-bit long mode at Ring 0 (CPL 0). Entered by the CPU with
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; IF cleared (interrupt gate); no privilege change, so the CPU pushed
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; RIP/CS/RFLAGS plus an error code only on vectors 8, 10-14, 17, 21.
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; Fault behavior: a fault here (before the IDT is loaded, or inside the
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; handler) triple-faults. Never returns: the C handler halts.
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;
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; Contract with include/idt.h `struct interrupt_frame`: each stub leaves
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; [vector, error] on the stack (pushing a dummy 0 where the CPU did not),
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; then isr_common pushes the 15 GPRs and calls the C handler with RDI
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; pointing at the frame. Field order must stay in sync. Interrupts stay
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; disabled; -mno-red-zone makes the pushes safe.
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bits 64
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section .text
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global isr_stub_table
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extern exception_handler
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; Vectors without a CPU error code: normalize with a dummy 0.
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%macro ISR_NOERR 1
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global isr_stub_%1
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isr_stub_%1:
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push 0
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push %1
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jmp isr_common
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%endmacro
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; Vectors where the CPU already pushed an error code: only push the vector.
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%macro ISR_ERR 1
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global isr_stub_%1
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isr_stub_%1:
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push %1
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jmp isr_common
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%endmacro
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ISR_NOERR 0
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ISR_NOERR 1
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ISR_NOERR 2
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ISR_NOERR 3
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ISR_NOERR 4
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ISR_NOERR 5
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ISR_NOERR 6
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ISR_NOERR 7
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ISR_ERR 8
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ISR_NOERR 9
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ISR_ERR 10
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ISR_ERR 11
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ISR_ERR 12
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ISR_ERR 13
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ISR_ERR 14
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ISR_NOERR 15
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ISR_NOERR 16
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ISR_ERR 17
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ISR_NOERR 18
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ISR_NOERR 19
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ISR_NOERR 20
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ISR_ERR 21
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ISR_NOERR 22
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ISR_NOERR 23
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ISR_NOERR 24
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ISR_NOERR 25
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ISR_NOERR 26
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ISR_NOERR 27
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ISR_NOERR 28
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ISR_NOERR 29
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ISR_NOERR 30
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ISR_NOERR 31
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; Common entry: save GPRs, call void exception_handler(frame in RDI), halt
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; if it ever returns (it must not).
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isr_common:
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push rax
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push rbx
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push rcx
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push rdx
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push rsi
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push rdi
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push rbp
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push r8
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push r9
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push r10
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push r11
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push r12
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push r13
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push r14
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push r15
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mov rdi, rsp
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call exception_handler
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; Unreachable in practice; park the CPU if the handler returns.
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cli
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.hang:
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hlt
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jmp .hang
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section .rodata
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align 8
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isr_stub_table:
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dq isr_stub_0, isr_stub_1, isr_stub_2, isr_stub_3
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dq isr_stub_4, isr_stub_5, isr_stub_6, isr_stub_7
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dq isr_stub_8, isr_stub_9, isr_stub_10, isr_stub_11
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dq isr_stub_12, isr_stub_13, isr_stub_14, isr_stub_15
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dq isr_stub_16, isr_stub_17, isr_stub_18, isr_stub_19
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dq isr_stub_20, isr_stub_21, isr_stub_22, isr_stub_23
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dq isr_stub_24, isr_stub_25, isr_stub_26, isr_stub_27
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dq isr_stub_28, isr_stub_29, isr_stub_30, isr_stub_31
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@ -2,12 +2,13 @@
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*
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* Called once from the stage-2 entry stub after the CPU is in 64-bit long
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* mode with a valid stack, zeroed BSS and identity-mapped memory. Runs at
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* Ring 0 (CPL 0), interrupts disabled, no IDT yet: any fault triple-faults,
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* so this function proves the whole boot chain simply by running.
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* Ring 0 (CPL 0) interrupts disabled. Installs the exception IDT first
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* so from then on a fault prints diagnostics instead of triple-faulting.
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* It never returns; on return the caller halts the CPU.
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*/
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#include "console.h"
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#include "idt.h"
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/* A value that only comes out right if the CPU truly executes 64-bit
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* arithmetic: every nibble survives the shifts above 32 bits. */
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@ -18,6 +19,8 @@ void kmain(void)
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console_clear();
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console_puts("Hello World from Nadir Kernel !\n");
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console_puts("Running C code in 64-bit long mode (Ring 0).\n");
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idt_init();
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console_puts("IDT installed (vectors 0-31).\n");
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console_puts("64-bit proof value: ");
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console_puthex64(PROOF_VALUE);
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console_puts("\nHalting.\n");
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