diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 600b985609..7df229d9f4 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -8,7 +8,7 @@
 include_directories(.)
 
 # Dynarmic
-if (ARCHITECTURE_x86_64 OR ARCHITECTURE_arm64 AND NOT YUZU_STATIC_ROOM)
+if ((ARCHITECTURE_x86_64 OR ARCHITECTURE_arm64 OR ARCHITECTURE_riscv64) AND NOT YUZU_STATIC_ROOM)
     add_subdirectory(dynarmic)
     add_library(dynarmic::dynarmic ALIAS dynarmic)
 endif()
diff --git a/src/core/CMakeLists.txt b/src/core/CMakeLists.txt
index 08a2d0e2db..04a46dd6dc 100644
--- a/src/core/CMakeLists.txt
+++ b/src/core/CMakeLists.txt
@@ -1246,7 +1246,7 @@ if (HAS_NCE)
     target_link_libraries(core PRIVATE merry::oaknut)
 endif()
 
-if (ARCHITECTURE_x86_64 OR ARCHITECTURE_arm64)
+if (ARCHITECTURE_x86_64 OR ARCHITECTURE_arm64 OR ARCHITECTURE_riscv64)
     target_sources(core PRIVATE
         arm/dynarmic/arm_dynarmic.h
         arm/dynarmic/arm_dynarmic_64.cpp
diff --git a/src/core/arm/dynarmic/dynarmic_cp15.cpp b/src/core/arm/dynarmic/dynarmic_cp15.cpp
index 7cb1d58398..28695a1058 100644
--- a/src/core/arm/dynarmic/dynarmic_cp15.cpp
+++ b/src/core/arm/dynarmic/dynarmic_cp15.cpp
@@ -59,14 +59,10 @@ CallbackOrAccessOneWord DynarmicCP15::CompileSendOneWord(bool two, unsigned opc1
 #if defined(_MSC_VER) && defined(ARCHITECTURE_x86_64)
                     _mm_mfence();
                     _mm_lfence();
-#elif defined(ARCHITECTURE_x86_64)
-                    asm volatile("mfence\n\tlfence\n\t" : : : "memory");
 #elif defined(_MSC_VER) && defined(ARCHITECTURE_arm64)
                     _Memory_barrier();
-#elif defined(ARCHITECTURE_arm64)
-                    asm volatile("dsb sy\n\t" : : : "memory");
 #else
-#error Unsupported architecture
+                    __sync_synchronize();
 #endif
                     return 0;
                 },
@@ -78,14 +74,10 @@ CallbackOrAccessOneWord DynarmicCP15::CompileSendOneWord(bool two, unsigned opc1
                 [](void*, std::uint32_t, std::uint32_t) -> std::uint64_t {
 #if defined(_MSC_VER) && defined(ARCHITECTURE_x86_64)
                     _mm_mfence();
-#elif defined(ARCHITECTURE_x86_64)
-                    asm volatile("mfence\n\t" : : : "memory");
 #elif defined(_MSC_VER) && defined(ARCHITECTURE_arm64)
                     _Memory_barrier();
-#elif defined(ARCHITECTURE_arm64)
-                    asm volatile("dmb sy\n\t" : : : "memory");
 #else
-#error Unsupported architecture
+                    __sync_synchronize();
 #endif
                     return 0;
                 },
diff --git a/src/core/arm/nce/interpreter_visitor.cpp b/src/core/arm/nce/interpreter_visitor.cpp
index be6fee8613..077a696cc8 100644
--- a/src/core/arm/nce/interpreter_visitor.cpp
+++ b/src/core/arm/nce/interpreter_visitor.cpp
@@ -773,7 +773,11 @@ std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, m
     bool was_executed = false;
 
     auto decoder = Dynarmic::A64::Decode<VisitorBase>(instruction);
-    was_executed = decoder.get().call(visitor, instruction);
+    if (decoder) {
+        was_executed = decoder->get().call(visitor, instruction);
+    } else {
+        was_executed = false;
+    }
     return was_executed ? std::optional<u64>(pc + 4) : std::nullopt;
 }
 
diff --git a/src/dynarmic/CMakeLists.txt b/src/dynarmic/CMakeLists.txt
index dd1def5273..0d8dcfba7c 100644
--- a/src/dynarmic/CMakeLists.txt
+++ b/src/dynarmic/CMakeLists.txt
@@ -32,7 +32,6 @@ else()
 endif()
 option(DYNARMIC_ENABLE_NO_EXECUTE_SUPPORT "Enables support for systems that require W^X" ${REQUIRE_WX})
 
-option(DYNARMIC_IGNORE_ASSERTS "Ignore asserts" ON)
 option(DYNARMIC_TESTS_USE_UNICORN "Enable fuzzing tests against unicorn" OFF)
 CMAKE_DEPENDENT_OPTION(DYNARMIC_USE_LLVM "Support disassembly of jitted x86_64 code using LLVM" OFF "NOT YUZU_DISABLE_LLVM" OFF)
 
@@ -126,7 +125,7 @@ if ("arm64" IN_LIST ARCHITECTURE OR DYNARMIC_TESTS)
     find_package(oaknut 2.0.1 CONFIG)
 endif()
 
-if ("riscv" IN_LIST ARCHITECTURE)
+if ("riscv64" IN_LIST ARCHITECTURE)
     find_package(biscuit 0.9.1 REQUIRED)
 endif()
 
diff --git a/src/dynarmic/src/dynarmic/CMakeLists.txt b/src/dynarmic/src/dynarmic/CMakeLists.txt
index f79d18c15a..2e3e7eb55e 100644
--- a/src/dynarmic/src/dynarmic/CMakeLists.txt
+++ b/src/dynarmic/src/dynarmic/CMakeLists.txt
@@ -13,10 +13,7 @@ add_library(dynarmic STATIC
     backend/block_range_information.h
     backend/exception_handler.h
     common/always_false.h
-    common/assert.cpp
-    common/assert.h
     common/cast_util.h
-    common/common_types.h
     common/crypto/aes.cpp
     common/crypto/aes.h
     common/crypto/crc32.cpp
@@ -258,7 +255,7 @@ if ("arm64" IN_LIST ARCHITECTURE)
     )
 endif()
 
-if ("riscv" IN_LIST ARCHITECTURE)
+if ("riscv64" IN_LIST ARCHITECTURE)
     target_link_libraries(dynarmic PRIVATE biscuit::biscuit)
 
     target_sources(dynarmic PRIVATE
@@ -281,6 +278,7 @@ if ("riscv" IN_LIST ARCHITECTURE)
         backend/riscv64/emit_riscv64_vector.cpp
         backend/riscv64/emit_riscv64.cpp
         backend/riscv64/emit_riscv64.h
+        backend/riscv64/exclusive_monitor.cpp
         backend/riscv64/reg_alloc.cpp
         backend/riscv64/reg_alloc.h
         backend/riscv64/stack_layout.h
@@ -289,9 +287,12 @@ if ("riscv" IN_LIST ARCHITECTURE)
         backend/riscv64/a32_address_space.h
         backend/riscv64/a32_core.h
         backend/riscv64/a32_interface.cpp
+        backend/riscv64/a64_interface.cpp
         backend/riscv64/code_block.h
+
+        common/spin_lock_riscv64.cpp
     )
-    message(FATAL_ERROR "TODO: Unimplemented frontend for this host architecture")
+    message(WARNING "TODO: Incomplete frontend for this host architecture")
 endif()
 
 if (WIN32)
@@ -359,7 +360,7 @@ set_target_properties(dynarmic PROPERTIES
 target_compile_options(dynarmic PRIVATE ${DYNARMIC_CXX_FLAGS})
 
 target_link_libraries(dynarmic PRIVATE unordered_dense::unordered_dense)
-target_link_libraries(dynarmic PUBLIC fmt::fmt)
+target_link_libraries(dynarmic PUBLIC fmt::fmt common)
 
 if (BOOST_NO_HEADERS)
     target_link_libraries(dynarmic PRIVATE Boost::variant Boost::icl Boost::pool)
@@ -378,9 +379,6 @@ endif()
 if (DYNARMIC_ENABLE_NO_EXECUTE_SUPPORT)
     target_compile_definitions(dynarmic PRIVATE DYNARMIC_ENABLE_NO_EXECUTE_SUPPORT=1)
 endif()
-if (DYNARMIC_IGNORE_ASSERTS)
-    target_compile_definitions(dynarmic PRIVATE MCL_IGNORE_ASSERTS=1)
-endif()
 if (CMAKE_SYSTEM_NAME STREQUAL "Windows")
     target_compile_definitions(dynarmic PRIVATE FMT_USE_WINDOWS_H=0)
 endif()
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/a32_interface.cpp b/src/dynarmic/src/dynarmic/backend/arm64/a32_interface.cpp
index d16a34275b..29b3f8459e 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/a32_interface.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/a32_interface.cpp
@@ -10,8 +10,8 @@
 #include <mutex>
 
 #include <boost/icl/interval_set.hpp>
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 
 #include "dynarmic/backend/arm64/a32_address_space.h"
 #include "dynarmic/backend/arm64/a32_core.h"
@@ -31,7 +31,7 @@ struct Jit::Impl final {
             , core(conf) {}
 
     HaltReason Run() {
-        ASSERT(!jit_interface->is_executing);
+        assert(!jit_interface->is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&halt_reason)));
 
         jit_interface->is_executing = true;
@@ -42,7 +42,7 @@ struct Jit::Impl final {
     }
 
     HaltReason Step() {
-        ASSERT(!jit_interface->is_executing);
+        assert(!jit_interface->is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&halt_reason)));
 
         jit_interface->is_executing = true;
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.cpp b/src/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.cpp
index 0ce51d0e17..dd8a561ccb 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.cpp
@@ -9,7 +9,7 @@
 #include "dynarmic/backend/arm64/a32_jitstate.h"
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Backend::Arm64 {
 
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.h b/src/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.h
index b4fee9a4d0..26513133e3 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <array>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/frontend/A32/a32_location_descriptor.h"
 #include "dynarmic/ir/location_descriptor.h"
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/a64_interface.cpp b/src/dynarmic/src/dynarmic/backend/arm64/a64_interface.cpp
index b230f455c5..8143ec7280 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/a64_interface.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/a64_interface.cpp
@@ -10,8 +10,8 @@
 #include <mutex>
 
 #include <boost/icl/interval_set.hpp>
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 
 #include "dynarmic/backend/arm64/a64_address_space.h"
 #include "dynarmic/backend/arm64/a64_core.h"
@@ -31,7 +31,7 @@ struct Jit::Impl final {
             , core(conf) {}
 
     HaltReason Run() {
-        ASSERT(!is_executing);
+        assert(!is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&halt_reason)));
         is_executing = true;
         HaltReason hr = core.Run(current_address_space, current_state, &halt_reason);
@@ -41,7 +41,7 @@ struct Jit::Impl final {
     }
 
     HaltReason Step() {
-        ASSERT(!is_executing);
+        assert(!is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&halt_reason)));
         is_executing = true;
         HaltReason hr = core.Step(current_address_space, current_state, &halt_reason);
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/a64_jitstate.h b/src/dynarmic/src/dynarmic/backend/arm64/a64_jitstate.h
index 3dd422b6d4..29bc001f2c 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/a64_jitstate.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/a64_jitstate.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <array>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/frontend/A64/a64_location_descriptor.h"
 
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/abi.cpp b/src/dynarmic/src/dynarmic/backend/arm64/abi.cpp
index acff6a89f0..e3918ed8c5 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/abi.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/abi.cpp
@@ -11,7 +11,7 @@
 #include <vector>
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include <oaknut/oaknut.hpp>
 
 namespace Dynarmic::Backend::Arm64 {
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/abi.h b/src/dynarmic/src/dynarmic/backend/arm64/abi.h
index b2e29d49e0..40f21c2ee4 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/abi.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/abi.h
@@ -9,14 +9,11 @@
 #pragma once
 
 #include <initializer_list>
-#include <stdexcept>
-#include <type_traits>
 
-#include "dynarmic/common/common_types.h"
-#include "dynarmic/common/assert.h"
+#include "common/common_types.h"
+#include <cassert>
 #include <oaknut/oaknut.hpp>
 
-#include "dynarmic/common/always_false.h"
 
 namespace Dynarmic::Backend::Arm64 {
 
@@ -29,25 +26,25 @@ constexpr oaknut::XReg Xpagetable{24};
 constexpr oaknut::XReg Xscratch0{16}, Xscratch1{17}, Xscratch2{30};
 constexpr oaknut::WReg Wscratch0{16}, Wscratch1{17}, Wscratch2{30};
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 constexpr auto Rscratch0() {
     if constexpr (bitsize == 32) {
         return Wscratch0;
     } else if constexpr (bitsize == 64) {
         return Xscratch0;
     } else {
-        return Xscratch0; //UNREACHABLE();
+        return Xscratch0; //std::terminate(); //unreachable
     }
 }
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 constexpr auto Rscratch1() {
     if constexpr (bitsize == 32) {
         return Wscratch1;
     } else if constexpr (bitsize == 64) {
         return Xscratch1;
     } else {
-        return Xscratch1; //UNREACHABLE();
+        return Xscratch1; //std::terminate(); //unreachable
     }
 }
 
@@ -60,7 +57,7 @@ constexpr RegisterList ToRegList(oaknut::Reg reg) {
     if (reg.is_vector()) {
         return RegisterList{1} << (reg.index() + 32);
     }
-    ASSERT(reg.index() != 31 && "ZR not allowed in reg list");
+    assert(reg.index() != 31 && "ZR not allowed in reg list");
     if (reg.index() == -1) {
         return RegisterList{1} << 31;
     }
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp b/src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp
index 6b59871b0a..0cb1ca2b91 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp
@@ -31,7 +31,7 @@ AddressSpace::AddressSpace(size_t code_cache_size)
     , code(mem.ptr(), mem.ptr())
     , fastmem_manager(exception_handler)
 {
-    ASSERT(code_cache_size <= 128 * 1024 * 1024 && "code_cache_size > 128 MiB not currently supported");
+    assert(code_cache_size <= 128 * 1024 * 1024 && "code_cache_size > 128 MiB not currently supported");
 
     exception_handler.Register(mem, code_cache_size);
     exception_handler.SetFastmemCallback([this](u64 host_pc) {
@@ -115,9 +115,9 @@ EmittedBlockInfo AddressSpace::Emit(IR::Block block) {
 
     EmittedBlockInfo block_info = EmitArm64(code, std::move(block), GetEmitConfig(), fastmem_manager);
 
-    ASSERT(block_entries.insert({block.Location(), block_info.entry_point}).second);
-    ASSERT(reverse_block_entries.insert({block_info.entry_point, block.Location()}).second);
-    ASSERT(block_infos.insert({block_info.entry_point, block_info}).second);
+    assert(block_entries.insert({block.Location(), block_info.entry_point}).second);
+    assert(reverse_block_entries.insert({block_info.entry_point, block.Location()}).second);
+    assert(block_infos.insert({block_info.entry_point, block_info}).second);
 
     Link(block_info);
     RelinkForDescriptor(block.Location(), block_info.entry_point);
@@ -260,7 +260,7 @@ void AddressSpace::Link(EmittedBlockInfo& block_info) {
             c.BL(prelude_info.get_ticks_remaining);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -294,7 +294,7 @@ void AddressSpace::LinkBlockLinks(const CodePtr entry_point, const CodePtr targe
             }
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 }
@@ -346,7 +346,7 @@ FakeCall AddressSpace::FastmemCallback(u64 host_pc) {
 fail:
     fmt::print("dynarmic: Segfault happened within JITted code at host_pc = {:016x}\n"
         "Segfault wasn't at a fastmem patch location!\n", host_pc);
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 }  // namespace Dynarmic::Backend::Arm64
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/address_space.h b/src/dynarmic/src/dynarmic/backend/arm64/address_space.h
index 9fe9595c65..5039ad1fb8 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/address_space.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/address_space.h
@@ -11,7 +11,7 @@
 #include <map>
 #include <optional>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include <oaknut/code_block.hpp>
 #include <oaknut/oaknut.hpp>
 #include <ankerl/unordered_dense.h>
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/devirtualize.h b/src/dynarmic/src/dynarmic/backend/arm64/devirtualize.h
index 737a6572e3..e1fd66b8f1 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/devirtualize.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/devirtualize.h
@@ -9,7 +9,7 @@
 #pragma once
 
 #include <bit>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include "dynarmic/mcl/function_info.hpp"
 
 namespace Dynarmic::Backend::Arm64 {
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp
index 104d0a452c..ec719ae350 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp
@@ -54,7 +54,7 @@ void EmitIR<IR::Opcode::PushRSB>(oaknut::CodeGenerator& code, EmitContext& ctx,
     }
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[0].IsImmediate());
+    assert(args[0].IsImmediate());
     const IR::LocationDescriptor target{args[0].GetImmediateU64()};
 
     code.LDR(Wscratch2, SP, offsetof(StackLayout, rsb_ptr));
@@ -71,19 +71,19 @@ void EmitIR<IR::Opcode::PushRSB>(oaknut::CodeGenerator& code, EmitContext& ctx,
 template<>
 void EmitIR<IR::Opcode::GetCarryFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    assert(ctx.reg_alloc.WasValueDefined(inst));
 }
 
 template<>
 void EmitIR<IR::Opcode::GetOverflowFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    assert(ctx.reg_alloc.WasValueDefined(inst));
 }
 
 template<>
 void EmitIR<IR::Opcode::GetGEFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    assert(ctx.reg_alloc.WasValueDefined(inst));
 }
 
 template<>
@@ -112,7 +112,7 @@ void EmitIR<IR::Opcode::GetNZCVFromOp>(oaknut::CodeGenerator& code, EmitContext&
         break;
     }
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -142,20 +142,20 @@ void EmitIR<IR::Opcode::GetNZFromOp>(oaknut::CodeGenerator& code, EmitContext& c
         break;
     }
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
 template<>
 void EmitIR<IR::Opcode::GetUpperFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    assert(ctx.reg_alloc.WasValueDefined(inst));
 }
 
 template<>
 void EmitIR<IR::Opcode::GetLowerFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    assert(ctx.reg_alloc.WasValueDefined(inst));
 }
 
 template<>
@@ -206,9 +206,9 @@ EmittedBlockInfo EmitArm64(oaknut::CodeGenerator& code, IR::Block block, const E
     ebi.entry_point = code.xptr<CodePtr>();
 
     if (ctx.block.GetCondition() == IR::Cond::AL) {
-        ASSERT(!ctx.block.HasConditionFailedLocation());
+        assert(!ctx.block.HasConditionFailedLocation());
     } else {
-        ASSERT(ctx.block.HasConditionFailedLocation());
+        assert(ctx.block.HasConditionFailedLocation());
         oaknut::Label pass;
 
         pass = conf.emit_cond(code, ctx, ctx.block.GetCondition());
@@ -239,7 +239,7 @@ EmittedBlockInfo EmitArm64(oaknut::CodeGenerator& code, IR::Block block, const E
 #undef A32OPC
 #undef A64OPC
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
 
         reg_alloc.UpdateAllUses();
@@ -283,7 +283,7 @@ void EmitBlockLinkRelocation(oaknut::CodeGenerator& code, EmitContext& ctx, cons
         code.NOP();
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.h b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.h
index e58f93c4e5..c228e7e637 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -13,7 +13,7 @@
 #include <memory>
 #include <vector>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include <ankerl/unordered_dense.h>
 
 #include "dynarmic/backend/arm64/fastmem.h"
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
index 213403b4ba..8e2797f65e 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
@@ -211,7 +211,7 @@ void EmitIR<IR::Opcode::A32GetRegister>(oaknut::CodeGenerator& code, EmitContext
 template<>
 void EmitIR<IR::Opcode::A32GetExtendedRegister32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsSingleExtReg(reg));
+    assert(A32::IsSingleExtReg(reg));
     const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::S0);
 
     auto Sresult = ctx.reg_alloc.WriteS(inst);
@@ -225,7 +225,7 @@ void EmitIR<IR::Opcode::A32GetExtendedRegister32>(oaknut::CodeGenerator& code, E
 template<>
 void EmitIR<IR::Opcode::A32GetVector>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    assert(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
 
     if (A32::IsDoubleExtReg(reg)) {
         const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::D0);
@@ -243,7 +243,7 @@ void EmitIR<IR::Opcode::A32GetVector>(oaknut::CodeGenerator& code, EmitContext&
 template<>
 void EmitIR<IR::Opcode::A32GetExtendedRegister64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg));
+    assert(A32::IsDoubleExtReg(reg));
     const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::D0);
 
     auto Dresult = ctx.reg_alloc.WriteD(inst);
@@ -271,7 +271,7 @@ void EmitIR<IR::Opcode::A32SetRegister>(oaknut::CodeGenerator& code, EmitContext
 template<>
 void EmitIR<IR::Opcode::A32SetExtendedRegister32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsSingleExtReg(reg));
+    assert(A32::IsSingleExtReg(reg));
     const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::S0);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@@ -286,7 +286,7 @@ void EmitIR<IR::Opcode::A32SetExtendedRegister32>(oaknut::CodeGenerator& code, E
 template<>
 void EmitIR<IR::Opcode::A32SetExtendedRegister64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg));
+    assert(A32::IsDoubleExtReg(reg));
     const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::D0);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@@ -301,7 +301,7 @@ void EmitIR<IR::Opcode::A32SetExtendedRegister64>(oaknut::CodeGenerator& code, E
 template<>
 void EmitIR<IR::Opcode::A32SetVector>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    assert(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
 
     if (A32::IsDoubleExtReg(reg)) {
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp
index 259e161479..7d937ba407 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -24,7 +24,7 @@ using namespace oaknut::util;
 
 static void EmitCoprocessorException() {
     // TODO: Raise coproc except
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 static void CallCoprocCallback(oaknut::CodeGenerator& code, EmitContext& ctx, A32::Coprocessor::Callback callback, IR::Inst* inst = nullptr, std::optional<Argument::copyable_reference> arg0 = {}, std::optional<Argument::copyable_reference> arg1 = {}) {
@@ -107,7 +107,7 @@ void EmitIR<IR::Opcode::A32CoprocSendOneWord>(oaknut::CodeGenerator& code, EmitC
         return;
     }
 
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -151,7 +151,7 @@ void EmitIR<IR::Opcode::A32CoprocSendTwoWords>(oaknut::CodeGenerator& code, Emit
         return;
     }
 
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -193,7 +193,7 @@ void EmitIR<IR::Opcode::A32CoprocGetOneWord>(oaknut::CodeGenerator& code, EmitCo
         return;
     }
 
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -235,7 +235,7 @@ void EmitIR<IR::Opcode::A32CoprocGetTwoWords>(oaknut::CodeGenerator& code, EmitC
         return;
     }
 
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_cryptography.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_cryptography.cpp
index 5366a250c9..f48549d9a0 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_cryptography.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_cryptography.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -120,7 +120,7 @@ void EmitIR<IR::Opcode::SM4AccessSubstitutionBox>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp
index ef21fd45bd..eb7cadebd7 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -11,7 +11,6 @@
 #include <fmt/ostream.h>
 #include <oaknut/oaknut.hpp>
 
-#include "dynarmic/backend/arm64/a32_jitstate.h"
 #include "dynarmic/backend/arm64/abi.h"
 #include "dynarmic/backend/arm64/emit_arm64.h"
 #include "dynarmic/backend/arm64/emit_context.h"
@@ -195,8 +194,8 @@ void EmitIR<IR::Opcode::TestBit>(oaknut::CodeGenerator& code, EmitContext& ctx,
     auto Xresult = ctx.reg_alloc.WriteX(inst);
     auto Xoperand = ctx.reg_alloc.ReadX(args[0]);
     RegAlloc::Realize(Xresult, Xoperand);
-    ASSERT(args[1].IsImmediate());
-    ASSERT(args[1].GetImmediateU8() < 64);
+    assert(args[1].IsImmediate());
+    assert(args[1].GetImmediateU8() < 64);
 
     code.UBFX(Xresult, Xoperand, args[1].GetImmediateU8(), 1);
 }
@@ -642,7 +641,7 @@ void EmitIR<IR::Opcode::ArithmeticShiftRight64>(oaknut::CodeGenerator& code, Emi
 }
 
 template<>
-void EmitIR<IR::Opcode::RotateRight32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
+void EmitIR<IR::Opcode::BitRotateRight32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const auto carry_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetCarryFromOp);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@@ -708,7 +707,7 @@ void EmitIR<IR::Opcode::RotateRight32>(oaknut::CodeGenerator& code, EmitContext&
 }
 
 template<>
-void EmitIR<IR::Opcode::RotateRight64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
+void EmitIR<IR::Opcode::BitRotateRight64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto& operand_arg = args[0];
     auto& shift_arg = args[1];
@@ -894,9 +893,9 @@ static void EmitAddSub(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
 
     if (overflow_inst) {
         // There is a limited set of circumstances where this is required, so assert for this.
-        ASSERT(!sub);
-        ASSERT(!nzcv_inst);
-        ASSERT(args[2].IsImmediate() && args[2].GetImmediateU1() == false);
+        assert(!sub);
+        assert(!nzcv_inst);
+        assert(args[2].IsImmediate() && args[2].GetImmediateU1() == false);
 
         auto Rb = ctx.reg_alloc.ReadReg<bitsize>(args[1]);
         auto Woverflow = ctx.reg_alloc.WriteW(overflow_inst);
@@ -1102,7 +1101,7 @@ void EmitIR<IR::Opcode::SignedDiv64>(oaknut::CodeGenerator& code, EmitContext& c
         [&](auto& Xresult, auto& Xa, auto& Xb) { code.SDIV(Xresult, Xa, Xb); });
 }
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 static bool IsValidBitImm(u64 imm) {
     static_assert(bitsize == 32 || bitsize == 64);
     if constexpr (bitsize == 32) {
@@ -1112,7 +1111,7 @@ static bool IsValidBitImm(u64 imm) {
     }
 }
 
-template<size_t bitsize, typename EmitFn>
+template<std::size_t bitsize, typename EmitFn>
 static void MaybeBitImm(oaknut::CodeGenerator& code, u64 imm, EmitFn emit_fn) {
     static_assert(bitsize == 32 || bitsize == 64);
     if constexpr (bitsize == 32) {
@@ -1135,7 +1134,7 @@ static void EmitBitOp(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* i
     if constexpr (!std::is_same_v<EmitFn2, std::nullptr_t>) {
         const auto nz_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZFromOp);
         const auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp);
-        ASSERT(!(nz_inst && nzcv_inst));
+        assert(!(nz_inst && nzcv_inst));
         const auto flag_inst = nz_inst ? nz_inst : nzcv_inst;
 
         if (flag_inst) {
@@ -1172,7 +1171,7 @@ template<size_t bitsize>
 static void EmitAndNot(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const auto nz_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZFromOp);
     const auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp);
-    ASSERT(!(nz_inst && nzcv_inst));
+    assert(!(nz_inst && nzcv_inst));
     const auto flag_inst = nz_inst ? nz_inst : nzcv_inst;
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@@ -1403,7 +1402,7 @@ void EmitIR<IR::Opcode::CountLeadingZeros64>(oaknut::CodeGenerator& code, EmitCo
 template<>
 void EmitIR<IR::Opcode::ExtractRegister32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[2].IsImmediate());
+    assert(args[2].IsImmediate());
 
     auto Wresult = ctx.reg_alloc.WriteW(inst);
     auto Wop1 = ctx.reg_alloc.ReadW(args[0]);
@@ -1417,7 +1416,7 @@ void EmitIR<IR::Opcode::ExtractRegister32>(oaknut::CodeGenerator& code, EmitCont
 template<>
 void EmitIR<IR::Opcode::ExtractRegister64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[2].IsImmediate());
+    assert(args[2].IsImmediate());
 
     auto Xresult = ctx.reg_alloc.WriteX(inst);
     auto Xop1 = ctx.reg_alloc.ReadX(args[0]);
@@ -1431,7 +1430,7 @@ void EmitIR<IR::Opcode::ExtractRegister64>(oaknut::CodeGenerator& code, EmitCont
 template<>
 void EmitIR<IR::Opcode::ReplicateBit32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
 
     auto Wresult = ctx.reg_alloc.WriteW(inst);
     auto Wvalue = ctx.reg_alloc.ReadW(args[0]);
@@ -1445,7 +1444,7 @@ void EmitIR<IR::Opcode::ReplicateBit32>(oaknut::CodeGenerator& code, EmitContext
 template<>
 void EmitIR<IR::Opcode::ReplicateBit64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
 
     auto Xresult = ctx.reg_alloc.WriteX(inst);
     auto Xvalue = ctx.reg_alloc.ReadX(args[0]);
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp
index 0efb6ce787..ce9d60d83e 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -68,7 +68,7 @@ static void EmitConvert(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst
     RegAlloc::Realize(Vto, Vfrom);
     ctx.fpsr.Load();
 
-    ASSERT(rounding_mode == ctx.FPCR().RMode());
+    assert(rounding_mode == ctx.FPCR().RMode());
 
     emit(Vto, Vfrom);
 }
@@ -106,8 +106,8 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
             }
         }
     } else {
-        ASSERT(fbits == 0);
-        ASSERT(bitsize_to != 16);
+        assert(fbits == 0);
+        assert(bitsize_to != 16);
         if constexpr (is_signed) {
             switch (rounding_mode) {
             case FP::RoundingMode::ToNearest_TieEven:
@@ -126,10 +126,10 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
                 code.FCVTAS(Rto, Vfrom);
                 break;
             case FP::RoundingMode::ToOdd:
-                UNREACHABLE();
+                std::terminate(); //unreachable
                 break;
             default:
-                UNREACHABLE();
+                std::terminate(); //unreachable
             }
         } else {
             switch (rounding_mode) {
@@ -149,10 +149,10 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
                 code.FCVTAU(Rto, Vfrom);
                 break;
             case FP::RoundingMode::ToOdd:
-                UNREACHABLE();
+                std::terminate(); //unreachable
                 break;
             default:
-                UNREACHABLE();
+                std::terminate(); //unreachable
             }
         }
     }
@@ -189,7 +189,7 @@ void EmitIR<IR::Opcode::FPAbs16>(oaknut::CodeGenerator& code, EmitContext& ctx,
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -316,7 +316,7 @@ void EmitIR<IR::Opcode::FPMulAdd16>(oaknut::CodeGenerator& code, EmitContext& ct
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -334,7 +334,7 @@ void EmitIR<IR::Opcode::FPMulSub16>(oaknut::CodeGenerator& code, EmitContext& ct
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -362,7 +362,7 @@ void EmitIR<IR::Opcode::FPNeg16>(oaknut::CodeGenerator& code, EmitContext& ctx,
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -380,7 +380,7 @@ void EmitIR<IR::Opcode::FPRecipEstimate16>(oaknut::CodeGenerator& code, EmitCont
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -398,7 +398,7 @@ void EmitIR<IR::Opcode::FPRecipExponent16>(oaknut::CodeGenerator& code, EmitCont
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -416,7 +416,7 @@ void EmitIR<IR::Opcode::FPRecipStepFused16>(oaknut::CodeGenerator& code, EmitCon
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -434,7 +434,7 @@ void EmitIR<IR::Opcode::FPRoundInt16>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -449,7 +449,7 @@ void EmitIR<IR::Opcode::FPRoundInt32>(oaknut::CodeGenerator& code, EmitContext&
     ctx.fpsr.Load();
 
     if (exact) {
-        ASSERT(ctx.FPCR().RMode() == rounding_mode);
+        assert(ctx.FPCR().RMode() == rounding_mode);
         code.FRINTX(Sresult, Soperand);
     } else {
         switch (rounding_mode) {
@@ -469,7 +469,7 @@ void EmitIR<IR::Opcode::FPRoundInt32>(oaknut::CodeGenerator& code, EmitContext&
             code.FRINTA(Sresult, Soperand);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 }
@@ -486,7 +486,7 @@ void EmitIR<IR::Opcode::FPRoundInt64>(oaknut::CodeGenerator& code, EmitContext&
     ctx.fpsr.Load();
 
     if (exact) {
-        ASSERT(ctx.FPCR().RMode() == rounding_mode);
+        assert(ctx.FPCR().RMode() == rounding_mode);
         code.FRINTX(Dresult, Doperand);
     } else {
         switch (rounding_mode) {
@@ -506,7 +506,7 @@ void EmitIR<IR::Opcode::FPRoundInt64>(oaknut::CodeGenerator& code, EmitContext&
             code.FRINTA(Dresult, Doperand);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 }
@@ -516,7 +516,7 @@ void EmitIR<IR::Opcode::FPRSqrtEstimate16>(oaknut::CodeGenerator& code, EmitCont
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -534,7 +534,7 @@ void EmitIR<IR::Opcode::FPRSqrtStepFused16>(oaknut::CodeGenerator& code, EmitCon
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -648,7 +648,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS16>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -656,7 +656,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS32>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -664,7 +664,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS64>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -672,7 +672,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU16>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -680,7 +680,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU32>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -688,7 +688,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU64>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp
index 67ab61f8a3..b809d30b9e 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp
@@ -10,6 +10,7 @@
 
 #include <optional>
 #include <utility>
+#include <cstddef>
 
 #include <bit>
 #include <oaknut/oaknut.hpp>
@@ -23,7 +24,6 @@
 #include "dynarmic/ir/acc_type.h"
 #include "dynarmic/ir/basic_block.h"
 #include "dynarmic/ir/microinstruction.h"
-#include "dynarmic/ir/opcodes.h"
 
 namespace Dynarmic::Backend::Arm64 {
 
@@ -48,7 +48,7 @@ LinkTarget ReadMemoryLinkTarget(size_t bitsize) {
     case 128:
         return LinkTarget::ReadMemory128;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 LinkTarget WriteMemoryLinkTarget(size_t bitsize) {
@@ -64,7 +64,7 @@ LinkTarget WriteMemoryLinkTarget(size_t bitsize) {
     case 128:
         return LinkTarget::WriteMemory128;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 LinkTarget WrappedReadMemoryLinkTarget(size_t bitsize) {
@@ -80,7 +80,7 @@ LinkTarget WrappedReadMemoryLinkTarget(size_t bitsize) {
     case 128:
         return LinkTarget::WrappedReadMemory128;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 LinkTarget WrappedWriteMemoryLinkTarget(size_t bitsize) {
@@ -96,7 +96,7 @@ LinkTarget WrappedWriteMemoryLinkTarget(size_t bitsize) {
     case 128:
         return LinkTarget::WrappedWriteMemory128;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 LinkTarget ExclusiveReadMemoryLinkTarget(size_t bitsize) {
@@ -112,7 +112,7 @@ LinkTarget ExclusiveReadMemoryLinkTarget(size_t bitsize) {
     case 128:
         return LinkTarget::ExclusiveReadMemory128;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 LinkTarget ExclusiveWriteMemoryLinkTarget(size_t bitsize) {
@@ -128,10 +128,10 @@ LinkTarget ExclusiveWriteMemoryLinkTarget(size_t bitsize) {
     case 128:
         return LinkTarget::ExclusiveWriteMemory128;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 void CallbackOnlyEmitReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     ctx.reg_alloc.PrepareForCall({}, args[1]);
@@ -150,7 +150,7 @@ void CallbackOnlyEmitReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, I
     }
 }
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 void CallbackOnlyEmitExclusiveReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     ctx.reg_alloc.PrepareForCall({}, args[1]);
@@ -171,7 +171,7 @@ void CallbackOnlyEmitExclusiveReadMemory(oaknut::CodeGenerator& code, EmitContex
     }
 }
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 void CallbackOnlyEmitWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     ctx.reg_alloc.PrepareForCall({}, args[1], args[2]);
@@ -186,7 +186,7 @@ void CallbackOnlyEmitWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx,
     }
 }
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 void CallbackOnlyEmitExclusiveWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     ctx.reg_alloc.PrepareForCall({}, args[1], args[2]);
@@ -209,13 +209,13 @@ void CallbackOnlyEmitExclusiveWriteMemory(oaknut::CodeGenerator& code, EmitConte
     ctx.reg_alloc.DefineAsRegister(inst, X0);
 }
 
-constexpr size_t page_bits = 12;
-constexpr size_t page_size = 1 << page_bits;
-constexpr size_t page_mask = (1 << page_bits) - 1;
+constexpr size_t page_table_const_bits = 12;
+constexpr size_t page_table_const_size = 1 << page_table_const_bits;
+constexpr size_t page_table_const_mask = (1 << page_table_const_bits) - 1;
 
 // This function may use Xscratch0 as a scratch register
 // Trashes NZCV
-template<size_t bitsize>
+template<std::size_t bitsize>
 void EmitDetectMisalignedVAddr(oaknut::CodeGenerator& code, EmitContext& ctx, oaknut::XReg Xaddr, const SharedLabel& fallback) {
     static_assert(bitsize == 8 || bitsize == 16 || bitsize == 32 || bitsize == 64 || bitsize == 128);
 
@@ -235,35 +235,35 @@ void EmitDetectMisalignedVAddr(oaknut::CodeGenerator& code, EmitContext& ctx, oa
             case 128:
                 return 0b1111;
             default:
-                UNREACHABLE();
+                std::terminate(); //unreachable
             }
         }();
 
         code.TST(Xaddr, align_mask);
         code.B(NE, *fallback);
     } else {
-        // If (addr & page_mask) > page_size - byte_size, use fallback.
-        code.AND(Xscratch0, Xaddr, page_mask);
-        code.CMP(Xscratch0, page_size - bitsize / 8);
+        // If (addr & page_table_const_mask) > page_table_const_size - byte_size, use fallback.
+        code.AND(Xscratch0, Xaddr, page_table_const_mask);
+        code.CMP(Xscratch0, page_table_const_size - bitsize / 8);
         code.B(HI, *fallback);
     }
 }
 
-// Outputs Xscratch0 = page_table[addr >> page_bits]
+// Outputs Xscratch0 = page_table[addr >> page_table_const_bits]
 // May use Xscratch1 as scratch register
 // Address to read/write = [ret0 + ret1], ret0 is always Xscratch0 and ret1 is either Xaddr or Xscratch1
 // Trashes NZCV
-template<size_t bitsize>
+template<std::size_t bitsize>
 std::pair<oaknut::XReg, oaknut::XReg> InlinePageTableEmitVAddrLookup(oaknut::CodeGenerator& code, EmitContext& ctx, oaknut::XReg Xaddr, const SharedLabel& fallback) {
-    const size_t valid_page_index_bits = ctx.conf.page_table_address_space_bits - page_bits;
+    const size_t valid_page_index_bits = ctx.conf.page_table_address_space_bits - page_table_const_bits;
     const size_t unused_top_bits = 64 - ctx.conf.page_table_address_space_bits;
 
     EmitDetectMisalignedVAddr<bitsize>(code, ctx, Xaddr, fallback);
 
     if (ctx.conf.silently_mirror_page_table || unused_top_bits == 0) {
-        code.UBFX(Xscratch0, Xaddr, page_bits, valid_page_index_bits);
+        code.UBFX(Xscratch0, Xaddr, page_table_const_bits, valid_page_index_bits);
     } else {
-        code.LSR(Xscratch0, Xaddr, page_bits);
+        code.LSR(Xscratch0, Xaddr, page_table_const_bits);
         code.TST(Xscratch0, u64(~u64(0)) << valid_page_index_bits);
         code.B(NE, *fallback);
     }
@@ -283,7 +283,7 @@ std::pair<oaknut::XReg, oaknut::XReg> InlinePageTableEmitVAddrLookup(oaknut::Cod
     if (ctx.conf.absolute_offset_page_table) {
         return std::make_pair(Xscratch0, Xaddr);
     }
-    code.AND(Xscratch1, Xaddr, page_mask);
+    code.AND(Xscratch1, Xaddr, page_table_const_mask);
     return std::make_pair(Xscratch0, Xscratch1);
 }
 
@@ -318,7 +318,7 @@ CodePtr EmitMemoryLdr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
             code.DMB(oaknut::BarrierOp::ISH);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     } else {
         fastmem_location = code.xptr<CodePtr>();
@@ -340,7 +340,7 @@ CodePtr EmitMemoryLdr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
             code.LDR(oaknut::QReg{value_idx}, Xbase, Roffset, index_ext);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -379,7 +379,7 @@ CodePtr EmitMemoryStr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
             code.DMB(oaknut::BarrierOp::ISH);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     } else {
         fastmem_location = code.xptr<CodePtr>();
@@ -401,14 +401,14 @@ CodePtr EmitMemoryStr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
             code.STR(oaknut::QReg{value_idx}, Xbase, Roffset, index_ext);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     return fastmem_location;
 }
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 void InlinePageTableEmitReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto Xaddr = ctx.reg_alloc.ReadX(args[1]);
@@ -448,7 +448,7 @@ void InlinePageTableEmitReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx
     code.l(*end);
 }
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 void InlinePageTableEmitWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto Xaddr = ctx.reg_alloc.ReadX(args[1]);
@@ -511,7 +511,7 @@ inline bool ShouldExt32(EmitContext& ctx) {
 // May use Xscratch0 as scratch register
 // Address to read/write = [ret0 + ret1], ret0 is always Xfastmem and ret1 is either Xaddr or Xscratch0
 // Trashes NZCV
-template<size_t bitsize>
+template<std::size_t bitsize>
 std::pair<oaknut::XReg, oaknut::XReg> FastmemEmitVAddrLookup(oaknut::CodeGenerator& code, EmitContext& ctx, oaknut::XReg Xaddr, const SharedLabel& fallback) {
     if (ctx.conf.fastmem_address_space_bits == 64 || ShouldExt32(ctx)) {
         return std::make_pair(Xfastmem, Xaddr);
@@ -527,7 +527,7 @@ std::pair<oaknut::XReg, oaknut::XReg> FastmemEmitVAddrLookup(oaknut::CodeGenerat
     return std::make_pair(Xfastmem, Xaddr);
 }
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 void FastmemEmitReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, DoNotFastmemMarker marker) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto Xaddr = ctx.reg_alloc.ReadX(args[1]);
@@ -577,7 +577,7 @@ void FastmemEmitReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::In
     code.l(*end);
 }
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 void FastmemEmitWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, DoNotFastmemMarker marker) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto Xaddr = ctx.reg_alloc.ReadX(args[1]);
@@ -633,7 +633,7 @@ void FastmemEmitWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::I
 
 }  // namespace
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 void EmitReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     if (const auto marker = ShouldFastmem(ctx, inst)) {
         FastmemEmitReadMemory<bitsize>(code, ctx, inst, *marker);
@@ -644,12 +644,12 @@ void EmitReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* ins
     }
 }
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 void EmitExclusiveReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     CallbackOnlyEmitExclusiveReadMemory<bitsize>(code, ctx, inst);
 }
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 void EmitWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     if (const auto marker = ShouldFastmem(ctx, inst)) {
         FastmemEmitWriteMemory<bitsize>(code, ctx, inst, *marker);
@@ -660,7 +660,7 @@ void EmitWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* in
     }
 }
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 void EmitExclusiveWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     CallbackOnlyEmitExclusiveWriteMemory<bitsize>(code, ctx, inst);
 }
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.h b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.h
index 3c50194689..25608dbfe3 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -6,7 +6,7 @@
  * SPDX-License-Identifier: 0BSD
  */
 
-#include "dynarmic/common/common_types.h"
+#include <cstddef>
 
 namespace oaknut {
 struct CodeGenerator;
@@ -23,13 +23,13 @@ namespace Dynarmic::Backend::Arm64 {
 struct EmitContext;
 enum class LinkTarget;
 
-template<size_t bitsize>
+template<std::size_t bitsize>
 void EmitReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst);
-template<size_t bitsize>
+template<std::size_t bitsize>
 void EmitExclusiveReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst);
-template<size_t bitsize>
+template<std::size_t bitsize>
 void EmitWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst);
-template<size_t bitsize>
+template<std::size_t bitsize>
 void EmitExclusiveWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst);
 
 }  // namespace Dynarmic::Backend::Arm64
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_packed.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_packed.cpp
index b9f13ac6f2..c3e4d01a29 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_packed.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_packed.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2022 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -244,7 +247,7 @@ static void EmitPackedAddSub(oaknut::CodeGenerator& code, EmitContext& ctx, IR::
     }
 
     if (ge_inst) {
-        ASSERT(!is_halving);
+        assert(!is_halving);
 
         auto Vge = ctx.reg_alloc.WriteD(ge_inst);
         RegAlloc::Realize(Vge);
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp
index f9d1e5d619..c2338c4e58 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -24,7 +24,7 @@ using namespace oaknut::util;
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAddWithFlag32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
-    ASSERT(overflow_inst);
+    assert(overflow_inst);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto Wresult = ctx.reg_alloc.WriteW(inst);
@@ -44,7 +44,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAddWithFlag32>(oaknut::CodeGenerator& cod
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSubWithFlag32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
-    ASSERT(overflow_inst);
+    assert(overflow_inst);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto Wresult = ctx.reg_alloc.WriteW(inst);
@@ -67,7 +67,7 @@ void EmitIR<IR::Opcode::SignedSaturation>(oaknut::CodeGenerator& code, EmitConte
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const size_t N = args[1].GetImmediateU8();
-    ASSERT(N >= 1 && N <= 32);
+    assert(N >= 1 && N <= 32);
 
     if (N == 32) {
         ctx.reg_alloc.DefineAsExisting(inst, args[0]);
@@ -113,7 +113,7 @@ void EmitIR<IR::Opcode::UnsignedSaturation>(oaknut::CodeGenerator& code, EmitCon
     ctx.reg_alloc.SpillFlags();
 
     const size_t N = args[1].GetImmediateU8();
-    ASSERT(N <= 31);
+    assert(N <= 31);
     const u32 saturated_value = (1u << N) - 1;
 
     code.MOV(Wscratch0, saturated_value);
@@ -134,7 +134,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd8>(oaknut::CodeGenerator& code, EmitCo
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -142,7 +142,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd16>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -150,7 +150,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd32>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -158,7 +158,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd64>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -166,7 +166,7 @@ void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh16>(oaknut::Cod
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -174,7 +174,7 @@ void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh32>(oaknut::Cod
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -182,7 +182,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub8>(oaknut::CodeGenerator& code, EmitCo
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -190,7 +190,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub16>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -198,7 +198,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub32>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -206,7 +206,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub64>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -214,7 +214,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd8>(oaknut::CodeGenerator& code, Emit
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -222,7 +222,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd16>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -230,7 +230,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd32>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -238,7 +238,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd64>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -246,7 +246,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub8>(oaknut::CodeGenerator& code, Emit
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -254,7 +254,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub16>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -262,7 +262,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub32>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -270,7 +270,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub64>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 }  // namespace Dynarmic::Backend::Arm64
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp
index c773d5a339..4ffe4c38df 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp
@@ -45,7 +45,7 @@ static void EmitTwoOpArranged(oaknut::CodeGenerator& code, EmitContext& ctx, IR:
         } else if constexpr (size == 64) {
             emit(Qresult->D2(), Qoperand->D2());
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     });
 }
@@ -68,7 +68,7 @@ static void EmitTwoOpArrangedWiden(oaknut::CodeGenerator& code, EmitContext& ctx
         } else if constexpr (size == 32) {
             emit(Qresult->D2(), Qoperand->toD().S2());
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     });
 }
@@ -83,7 +83,7 @@ static void EmitTwoOpArrangedNarrow(oaknut::CodeGenerator& code, EmitContext& ct
         } else if constexpr (size == 64) {
             emit(Qresult->toD().S2(), Qoperand->D2());
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     });
 }
@@ -106,7 +106,7 @@ static void EmitTwoOpArrangedPairWiden(oaknut::CodeGenerator& code, EmitContext&
         } else if constexpr (size == 32) {
             emit(Qresult->D2(), Qoperand->S4());
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     });
 }
@@ -121,7 +121,7 @@ static void EmitTwoOpArrangedLower(oaknut::CodeGenerator& code, EmitContext& ctx
         } else if constexpr (size == 32) {
             emit(Qresult->toD().S2(), Qoperand->toD().S2());
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     });
 }
@@ -149,7 +149,7 @@ static void EmitThreeOpArranged(oaknut::CodeGenerator& code, EmitContext& ctx, I
         } else if constexpr (size == 64) {
             emit(Qresult->D2(), Qa->D2(), Qb->D2());
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     });
 }
@@ -174,7 +174,7 @@ static void EmitThreeOpArrangedWiden(oaknut::CodeGenerator& code, EmitContext& c
         } else if constexpr (size == 64) {
             emit(Qresult->Q1(), Qa->toD().D1(), Qb->toD().D1());
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     });
 }
@@ -197,7 +197,7 @@ static void EmitThreeOpArrangedLower(oaknut::CodeGenerator& code, EmitContext& c
         } else if constexpr (size == 32) {
             emit(Qresult->toD().S2(), Qa->toD().S2(), Qb->toD().S2());
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     });
 }
@@ -219,7 +219,7 @@ static void EmitSaturatedAccumulate(oaknut::CodeGenerator&, EmitContext& ctx, IR
     } else if constexpr (size == 64) {
         emit(Qaccumulator->D2(), Qoperand->D2());
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -240,7 +240,7 @@ static void EmitImmShift(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* ins
     } else if constexpr (size == 64) {
         emit(Qresult->D2(), Qoperand->D2(), shift_amount);
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -268,14 +268,14 @@ static void EmitReduce(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst,
     } else if constexpr (size == 64) {
         emit(Vresult, Qoperand->D2());
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
 template<size_t size, typename EmitFn>
 static void EmitGetElement(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst, EmitFn emit) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     auto Rresult = ctx.reg_alloc.WriteReg<std::max<size_t>(32, size)>(inst);
@@ -310,7 +310,7 @@ void EmitIR<IR::Opcode::VectorGetElement64>(oaknut::CodeGenerator& code, EmitCon
 template<size_t size, typename EmitFn>
 static void EmitSetElement(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst, EmitFn emit) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     auto Qvector = ctx.reg_alloc.ReadWriteQ(args[0], inst);
@@ -640,7 +640,7 @@ void EmitIR<IR::Opcode::VectorEqual128>(oaknut::CodeGenerator& code, EmitContext
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -650,7 +650,7 @@ void EmitIR<IR::Opcode::VectorExtract>(oaknut::CodeGenerator& code, EmitContext&
     auto Qa = ctx.reg_alloc.ReadQ(args[0]);
     auto Qb = ctx.reg_alloc.ReadQ(args[1]);
     const u8 position = args[2].GetImmediateU8();
-    ASSERT(position % 8 == 0);
+    assert(position % 8 == 0);
     RegAlloc::Realize(Qresult, Qa, Qb);
 
     code.EXT(Qresult->B16(), Qa->B16(), Qb->B16(), position / 8);
@@ -663,7 +663,7 @@ void EmitIR<IR::Opcode::VectorExtractLower>(oaknut::CodeGenerator& code, EmitCon
     auto Da = ctx.reg_alloc.ReadD(args[0]);
     auto Db = ctx.reg_alloc.ReadD(args[1]);
     const u8 position = args[2].GetImmediateU8();
-    ASSERT(position % 8 == 0);
+    assert(position % 8 == 0);
     RegAlloc::Realize(Dresult, Da, Db);
 
     code.EXT(Dresult->B8(), Da->B8(), Db->B8(), position / 8);
@@ -869,7 +869,7 @@ void EmitIR<IR::Opcode::VectorMaxS64>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -892,7 +892,7 @@ void EmitIR<IR::Opcode::VectorMaxU64>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -915,7 +915,7 @@ void EmitIR<IR::Opcode::VectorMinS64>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -938,7 +938,7 @@ void EmitIR<IR::Opcode::VectorMinU64>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -958,7 +958,7 @@ void EmitIR<IR::Opcode::VectorMultiply32>(oaknut::CodeGenerator& code, EmitConte
 
 template<>
 void EmitIR<IR::Opcode::VectorMultiply64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    ASSERT(ctx.conf.very_verbose_debugging_output && "VectorMultiply64 is for debugging only");
+    assert(ctx.conf.very_verbose_debugging_output && "VectorMultiply64 is for debugging only");
     EmitThreeOp(code, ctx, inst, [&](auto& Qresult, auto& Qa, auto& Qb) {
         code.FMOV(Xscratch0, Qa->toD());
         code.FMOV(Xscratch1, Qb->toD());
@@ -1289,7 +1289,7 @@ void EmitIR<IR::Opcode::VectorReduceAdd64>(oaknut::CodeGenerator& code, EmitCont
 template<>
 void EmitIR<IR::Opcode::VectorRotateWholeVectorRight>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     EmitImmShift<8>(code, ctx, inst, [&](auto Vresult, auto Voperand, u8 shift_amount) {
-        ASSERT(shift_amount % 8 == 0);
+        assert(shift_amount % 8 == 0);
         const u8 ext_imm = (shift_amount % 128) / 8;
         code.EXT(Vresult, Voperand, Voperand, ext_imm);
     });
@@ -1385,7 +1385,7 @@ void EmitIR<IR::Opcode::VectorSignExtend64>(oaknut::CodeGenerator& code, EmitCon
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -1408,7 +1408,7 @@ void EmitIR<IR::Opcode::VectorSignedMultiply16>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -1416,7 +1416,7 @@ void EmitIR<IR::Opcode::VectorSignedMultiply32>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -1602,12 +1602,12 @@ void EmitIR<IR::Opcode::VectorSub64>(oaknut::CodeGenerator& code, EmitContext& c
 template<>
 void EmitIR<IR::Opcode::VectorTable>(oaknut::CodeGenerator&, EmitContext&, IR::Inst* inst) {
     // Do nothing. We *want* to hold on to the refcount for our arguments, so VectorTableLookup can use our arguments.
-    ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times");
+    assert(inst->UseCount() == 1 && "Table cannot be used multiple times");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorTableLookup64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
+    assert(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst());
@@ -1668,13 +1668,13 @@ void EmitIR<IR::Opcode::VectorTableLookup64>(oaknut::CodeGenerator& code, EmitCo
         }
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorTableLookup128>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
+    assert(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst());
@@ -1732,7 +1732,7 @@ void EmitIR<IR::Opcode::VectorTableLookup128>(oaknut::CodeGenerator& code, EmitC
         }
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -1780,7 +1780,7 @@ void EmitIR<IR::Opcode::VectorUnsignedMultiply16>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -1788,7 +1788,7 @@ void EmitIR<IR::Opcode::VectorUnsignedMultiply32>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
index 557d6284ed..b12f7460b5 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
@@ -75,7 +75,7 @@ static void EmitTwoOpArranged(oaknut::CodeGenerator& code, EmitContext& ctx, IR:
         } else if constexpr (size == 64) {
             emit(Qresult->D2(), Qa->D2());
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     });
 }
@@ -103,7 +103,7 @@ static void EmitThreeOpArranged(oaknut::CodeGenerator& code, EmitContext& ctx, I
         } else if constexpr (size == 64) {
             emit(Qresult->D2(), Qa->D2(), Qb->D2());
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     });
 }
@@ -126,7 +126,7 @@ static void EmitFMA(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* ins
         } else if constexpr (size == 64) {
             emit(Qresult->D2(), Qm->D2(), Qn->D2());
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     });
 }
@@ -139,7 +139,7 @@ static void EmitFromFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Ins
     const u8 fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
     const bool fpcr_controlled = args[3].GetImmediateU1();
-    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    assert(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
     RegAlloc::Realize(Qto, Qfrom);
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
@@ -148,7 +148,7 @@ static void EmitFromFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Ins
         } else if constexpr (size == 64) {
             emit(Qto->D2(), Qfrom->D2(), fbits);
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     });
 }
@@ -170,7 +170,7 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
         } else if constexpr (fsize == 64) {
             return Qto->D2();
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }();
     auto Vfrom = [&] {
@@ -179,7 +179,7 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
         } else if constexpr (fsize == 64) {
             return Qfrom->D2();
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }();
 
@@ -199,7 +199,7 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
                 }
             }
         } else {
-            ASSERT(fbits == 0);
+            assert(fbits == 0);
             if constexpr (is_signed) {
                 switch (rounding_mode) {
                 case FP::RoundingMode::ToNearest_TieEven:
@@ -218,10 +218,10 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
                     code.FCVTAS(Vto, Vfrom);
                     break;
                 case FP::RoundingMode::ToOdd:
-                    UNREACHABLE();
+                    std::terminate(); //unreachable
                     break;
                 default:
-                    UNREACHABLE();
+                    std::terminate(); //unreachable
                 }
             } else {
                 switch (rounding_mode) {
@@ -241,10 +241,10 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
                     code.FCVTAU(Vto, Vfrom);
                     break;
                 case FP::RoundingMode::ToOdd:
-                    UNREACHABLE();
+                    std::terminate(); //unreachable
                     break;
                 default:
-                    UNREACHABLE();
+                    std::terminate(); //unreachable
                 }
             }
         }
@@ -329,7 +329,7 @@ void EmitIR<IR::Opcode::FPVectorEqual16>(oaknut::CodeGenerator& code, EmitContex
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -346,7 +346,7 @@ template<>
 void EmitIR<IR::Opcode::FPVectorFromHalf32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const auto rounding_mode = static_cast<FP::RoundingMode>(args[1].GetImmediateU8());
-    ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
+    assert(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
     const bool fpcr_controlled = args[2].GetImmediateU1();
 
     auto Qresult = ctx.reg_alloc.WriteQ(inst);
@@ -454,7 +454,7 @@ void EmitIR<IR::Opcode::FPVectorMulAdd16>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -482,7 +482,7 @@ void EmitIR<IR::Opcode::FPVectorNeg16>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -527,7 +527,7 @@ void EmitIR<IR::Opcode::FPVectorRecipEstimate16>(oaknut::CodeGenerator& code, Em
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -545,7 +545,7 @@ void EmitIR<IR::Opcode::FPVectorRecipStepFused16>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -599,7 +599,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt16>(oaknut::CodeGenerator& code, EmitCon
             : EmitTwoOpFallback<3>(code, ctx, inst, EmitIRVectorRoundInt16Thunk<FPT, FP::RoundingMode::ToNearest_TieAwayFromZero, false>);
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -617,7 +617,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt32>(oaknut::CodeGenerator& code, EmitCon
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
         if (exact) {
-            ASSERT(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode);
+            assert(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode);
             code.FRINTX(Qresult->S4(), Qoperand->S4());
         } else {
             switch (rounding_mode) {
@@ -637,7 +637,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt32>(oaknut::CodeGenerator& code, EmitCon
                 code.FRINTA(Qresult->S4(), Qoperand->S4());
                 break;
             default:
-                UNREACHABLE();
+                std::terminate(); //unreachable
             }
         }
     });
@@ -657,7 +657,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt64>(oaknut::CodeGenerator& code, EmitCon
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
         if (exact) {
-            ASSERT(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode);
+            assert(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode);
             code.FRINTX(Qresult->D2(), Qoperand->D2());
         } else {
             switch (rounding_mode) {
@@ -677,7 +677,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt64>(oaknut::CodeGenerator& code, EmitCon
                 code.FRINTA(Qresult->D2(), Qoperand->D2());
                 break;
             default:
-                UNREACHABLE();
+                std::terminate(); //unreachable
             }
         }
     });
@@ -688,7 +688,7 @@ void EmitIR<IR::Opcode::FPVectorRSqrtEstimate16>(oaknut::CodeGenerator& code, Em
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -706,7 +706,7 @@ void EmitIR<IR::Opcode::FPVectorRSqrtStepFused16>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -743,7 +743,7 @@ template<>
 void EmitIR<IR::Opcode::FPVectorToHalf32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const auto rounding_mode = static_cast<FP::RoundingMode>(args[1].GetImmediateU8());
-    ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
+    assert(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
     const bool fpcr_controlled = args[2].GetImmediateU1();
 
     auto Dresult = ctx.reg_alloc.WriteD(inst);
@@ -761,7 +761,7 @@ void EmitIR<IR::Opcode::FPVectorToSignedFixed16>(oaknut::CodeGenerator& code, Em
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
@@ -779,7 +779,7 @@ void EmitIR<IR::Opcode::FPVectorToUnsignedFixed16>(oaknut::CodeGenerator& code,
     (void)code;
     (void)ctx;
     (void)inst;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 template<>
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_saturation.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_saturation.cpp
index d63c1d92d0..0fe8dd11bd 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_saturation.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_saturation.cpp
@@ -41,7 +41,7 @@ static void Emit(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst, EmitF
     } else if constexpr (size == 64) {
         emit(Qresult->D2(), Qa->D2(), Qb->D2());
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/exclusive_monitor.cpp b/src/dynarmic/src/dynarmic/backend/arm64/exclusive_monitor.cpp
index b47167bf6f..83926239e1 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/exclusive_monitor.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/exclusive_monitor.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <algorithm>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 namespace Dynarmic {
 
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/fastmem.h b/src/dynarmic/src/dynarmic/backend/arm64/fastmem.h
index 953fc3783e..8f0470c2ab 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/fastmem.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/fastmem.h
@@ -13,7 +13,7 @@
 #include <ankerl/unordered_dense.h>
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include "dynarmic/backend/exception_handler.h"
 #include "dynarmic/ir/location_descriptor.h"
 
@@ -29,7 +29,7 @@ constexpr size_t xmrx(size_t x) noexcept {
 }
 
 struct DoNotFastmemMarkerHash {
-    [[nodiscard]] constexpr size_t operator()(const DoNotFastmemMarker& value) const noexcept {
+    [[nodiscard]] size_t operator()(const DoNotFastmemMarker& value) const noexcept {
         return xmrx(std::get<0>(value).Value() ^ u64(std::get<1>(value)));
     }
 };
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/fpsr_manager.h b/src/dynarmic/src/dynarmic/backend/arm64/fpsr_manager.h
index 3bc5683153..c0aca09bab 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/fpsr_manager.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/fpsr_manager.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,7 +8,7 @@
 
 #pragma once
 
-#include "dynarmic/common/common_types.h"
+#include <cstddef>
 
 namespace oaknut {
 struct CodeGenerator;
@@ -19,7 +19,7 @@ namespace Dynarmic::Backend::Arm64 {
 
 class FpsrManager {
 public:
-    explicit FpsrManager(oaknut::CodeGenerator& code, size_t state_fpsr_offset);
+    explicit FpsrManager(oaknut::CodeGenerator& code, std::size_t state_fpsr_offset);
 
     void Spill();
     void Load();
@@ -29,7 +29,7 @@ public:
 
 private:
     oaknut::CodeGenerator& code;
-    size_t state_fpsr_offset;
+    std::size_t state_fpsr_offset;
     bool fpsr_loaded = false;
 };
 
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp
index 47d83f2362..eff72ee08e 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp
@@ -12,10 +12,10 @@
 #include <array>
 #include <iterator>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
 #include <bit>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/backend/arm64/abi.h"
 #include "dynarmic/backend/arm64/emit_context.h"
@@ -53,19 +53,19 @@ bool Argument::GetImmediateU1() const {
 
 u8 Argument::GetImmediateU8() const {
     const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x100);
+    assert(imm < 0x100);
     return u8(imm);
 }
 
 u16 Argument::GetImmediateU16() const {
     const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x10000);
+    assert(imm < 0x10000);
     return u16(imm);
 }
 
 u32 Argument::GetImmediateU32() const {
     const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x100000000);
+    assert(imm < 0x100000000);
     return u32(imm);
 }
 
@@ -74,12 +74,12 @@ u64 Argument::GetImmediateU64() const {
 }
 
 IR::Cond Argument::GetImmediateCond() const {
-    ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
+    assert(IsImmediate() && GetType() == IR::Type::Cond);
     return value.GetCond();
 }
 
 IR::AccType Argument::GetImmediateAccType() const {
-    ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
+    assert(IsImmediate() && GetType() == IR::Type::AccType);
     return value.GetAccType();
 }
 
@@ -92,12 +92,12 @@ bool HostLocInfo::Contains(const IR::Inst* value) const {
 }
 
 void HostLocInfo::SetupScratchLocation() {
-    ASSERT(IsCompletelyEmpty());
+    assert(IsCompletelyEmpty());
     realized = true;
 }
 
 void HostLocInfo::SetupLocation(const IR::Inst* value) {
-    ASSERT(IsCompletelyEmpty());
+    assert(IsCompletelyEmpty());
     values.clear();
     values.push_back(value);
     realized = true;
@@ -135,7 +135,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
         const IR::Value arg = inst->GetArg(i);
         ret[i].value = arg;
         if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
-            ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
+            assert(ValueLocation(arg.GetInst()) && "argument must already been defined");
             ValueInfo(arg.GetInst()).uses_this_inst++;
         }
     }
@@ -174,11 +174,11 @@ void RegAlloc::PrepareForCall(std::optional<Argument::copyable_reference> arg0,
     for (int i = 0; i < 4; i++) {
         if (args[i]) {
             if (args[i]->get().GetType() == IR::Type::U128) {
-                ASSERT(fprs[nsrn].IsCompletelyEmpty());
+                assert(fprs[nsrn].IsCompletelyEmpty());
                 LoadCopyInto(args[i]->get().value, oaknut::QReg{nsrn});
                 nsrn++;
             } else {
-                ASSERT(gprs[ngrn].IsCompletelyEmpty());
+                assert(gprs[ngrn].IsCompletelyEmpty());
                 LoadCopyInto(args[i]->get().value, oaknut::XReg{ngrn});
                 ngrn++;
             }
@@ -192,7 +192,7 @@ void RegAlloc::PrepareForCall(std::optional<Argument::copyable_reference> arg0,
 
 void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
     defined_insts.insert(inst);
-    ASSERT(!ValueLocation(inst));
+    assert(!ValueLocation(inst));
 
     if (arg.value.IsImmediate()) {
         inst->ReplaceUsesWith(arg.value);
@@ -206,9 +206,9 @@ void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
 
 void RegAlloc::DefineAsRegister(IR::Inst* inst, oaknut::Reg reg) {
     defined_insts.insert(inst);
-    ASSERT(!ValueLocation(inst));
+    assert(!ValueLocation(inst));
     auto& info = reg.is_vector() ? fprs[reg.index()] : gprs[reg.index()];
-    ASSERT(info.IsCompletelyEmpty());
+    assert(info.IsCompletelyEmpty());
     info.values.push_back(inst);
     info.expected_uses += inst->UseCount();
 }
@@ -228,18 +228,18 @@ void RegAlloc::UpdateAllUses() {
 
 void RegAlloc::AssertAllUnlocked() const {
     const auto is_unlocked = [](const auto& i) { return !i.locked && !i.realized; };
-    ASSERT(std::all_of(gprs.begin(), gprs.end(), is_unlocked));
-    ASSERT(std::all_of(fprs.begin(), fprs.end(), is_unlocked));
-    ASSERT(is_unlocked(flags));
-    ASSERT(std::all_of(spills.begin(), spills.end(), is_unlocked));
+    assert(std::all_of(gprs.begin(), gprs.end(), is_unlocked));
+    assert(std::all_of(fprs.begin(), fprs.end(), is_unlocked));
+    assert(is_unlocked(flags));
+    assert(std::all_of(spills.begin(), spills.end(), is_unlocked));
 }
 
 void RegAlloc::AssertNoMoreUses() const {
     const auto is_empty = [](const auto& i) { return i.IsCompletelyEmpty(); };
-    ASSERT(std::all_of(gprs.begin(), gprs.end(), is_empty));
-    ASSERT(std::all_of(fprs.begin(), fprs.end(), is_empty));
-    ASSERT(is_empty(flags));
-    ASSERT(std::all_of(spills.begin(), spills.end(), is_empty));
+    assert(std::all_of(gprs.begin(), gprs.end(), is_empty));
+    assert(std::all_of(fprs.begin(), fprs.end(), is_empty));
+    assert(is_empty(flags));
+    assert(std::all_of(spills.begin(), spills.end(), is_empty));
 }
 
 void RegAlloc::EmitVerboseDebuggingOutput() {
@@ -271,7 +271,7 @@ void RegAlloc::EmitVerboseDebuggingOutput() {
 
 template<HostLoc::Kind kind>
 int RegAlloc::GenerateImmediate(const IR::Value& value) {
-    ASSERT(value.GetType() != IR::Type::U1);
+    assert(value.GetType() != IR::Type::U1);
     if constexpr (kind == HostLoc::Kind::Gpr) {
         const int new_location_index = AllocateRegister(gprs, gpr_order);
         SpillGpr(new_location_index);
@@ -298,7 +298,7 @@ int RegAlloc::GenerateImmediate(const IR::Value& value) {
 
         return 0;
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -309,15 +309,15 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
     }
 
     const auto current_location = ValueLocation(value.GetInst());
-    ASSERT(current_location);
+    assert(current_location);
 
     if (current_location->kind == required_kind) {
         ValueInfo(*current_location).realized = true;
         return current_location->index;
     }
 
-    ASSERT(!ValueInfo(*current_location).realized);
-    ASSERT(ValueInfo(*current_location).locked);
+    assert(!ValueInfo(*current_location).realized);
+    assert(ValueInfo(*current_location).locked);
 
     if constexpr (required_kind == HostLoc::Kind::Gpr) {
         const int new_location_index = AllocateRegister(gprs, gpr_order);
@@ -325,10 +325,10 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
 
         switch (current_location->kind) {
         case HostLoc::Kind::Gpr:
-            UNREACHABLE(); //logic error
+            std::terminate(); //unreachable //logic error
         case HostLoc::Kind::Fpr:
             code.FMOV(oaknut::XReg{new_location_index}, oaknut::DReg{current_location->index});
-            // ASSERT size fits
+            // assert size fits
             break;
         case HostLoc::Kind::Spill:
             code.LDR(oaknut::XReg{new_location_index}, SP, spill_offset + current_location->index * spill_slot_size);
@@ -350,12 +350,12 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
             code.FMOV(oaknut::DReg{new_location_index}, oaknut::XReg{current_location->index});
             break;
         case HostLoc::Kind::Fpr:
-            UNREACHABLE(); //logic error
+            std::terminate(); //unreachable //logic error
         case HostLoc::Kind::Spill:
             code.LDR(oaknut::QReg{new_location_index}, SP, spill_offset + current_location->index * spill_slot_size);
             break;
         case HostLoc::Kind::Flags:
-            ASSERT(false && "Moving from flags into fprs is not currently supported");
+            assert(false && "Moving from flags into fprs is not currently supported");
             break;
         }
 
@@ -363,16 +363,16 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
         fprs[new_location_index].realized = true;
         return new_location_index;
     } else if constexpr (required_kind == HostLoc::Kind::Flags) {
-        UNREACHABLE(); //A simple read from flags is likely a logic error
+        std::terminate(); //unreachable //A simple read from flags is likely a logic error
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
 template<HostLoc::Kind kind>
 int RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
     defined_insts.insert(value);
-    ASSERT(!ValueLocation(value));
+    assert(!ValueLocation(value));
 
     if constexpr (kind == HostLoc::Kind::Gpr) {
         const int new_location_index = AllocateRegister(gprs, gpr_order);
@@ -389,7 +389,7 @@ int RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
         flags.SetupLocation(value);
         return 0;
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -407,9 +407,9 @@ int RegAlloc::RealizeReadWriteImpl(const IR::Value& read_value, const IR::Inst*
         LoadCopyInto(read_value, oaknut::QReg{write_loc});
         return write_loc;
     } else if constexpr (kind == HostLoc::Kind::Flags) {
-        ASSERT(false && "Incorrect function for ReadWrite of flags");
+        assert(false && "Incorrect function for ReadWrite of flags");
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -439,7 +439,7 @@ int RegAlloc::AllocateRegister(const std::array<HostLocInfo, 32>& regs, const st
 }
 
 void RegAlloc::SpillGpr(int index) {
-    ASSERT(!gprs[index].locked && !gprs[index].realized);
+    assert(!gprs[index].locked && !gprs[index].realized);
     if (gprs[index].values.empty()) {
         return;
     }
@@ -449,7 +449,7 @@ void RegAlloc::SpillGpr(int index) {
 }
 
 void RegAlloc::SpillFpr(int index) {
-    ASSERT(!fprs[index].locked && !fprs[index].realized);
+    assert(!fprs[index].locked && !fprs[index].realized);
     if (fprs[index].values.empty()) {
         return;
     }
@@ -461,7 +461,7 @@ void RegAlloc::SpillFpr(int index) {
 void RegAlloc::ReadWriteFlags(Argument& read, IR::Inst* write) {
     defined_insts.insert(write);
     const auto current_location = ValueLocation(read.value.GetInst());
-    ASSERT(current_location);
+    assert(current_location);
 
     if (current_location->kind == HostLoc::Kind::Flags) {
         if (!flags.IsOneRemainingUse()) {
@@ -479,7 +479,7 @@ void RegAlloc::ReadWriteFlags(Argument& read, IR::Inst* write) {
         code.LDR(Wscratch0, SP, spill_offset + current_location->index * spill_slot_size);
         code.MSR(oaknut::SystemReg::NZCV, Xscratch0);
     } else {
-        UNREACHABLE(); //ASSERT(false && "Invalid current location for flags");
+        std::terminate(); //unreachable //assert(false && "Invalid current location for flags");
     }
 
     if (write) {
@@ -489,7 +489,7 @@ void RegAlloc::ReadWriteFlags(Argument& read, IR::Inst* write) {
 }
 
 void RegAlloc::SpillFlags() {
-    ASSERT(!flags.locked && !flags.realized);
+    assert(!flags.locked && !flags.realized);
     if (flags.values.empty()) {
         return;
     }
@@ -501,7 +501,7 @@ void RegAlloc::SpillFlags() {
 
 int RegAlloc::FindFreeSpill() const {
     const auto iter = std::find_if(spills.begin(), spills.end(), [](const HostLocInfo& info) { return info.values.empty(); });
-    ASSERT(iter != spills.end() && "All spill locations are full");
+    assert(iter != spills.end() && "All spill locations are full");
     return static_cast<int>(iter - spills.begin());
 }
 
@@ -512,14 +512,14 @@ void RegAlloc::LoadCopyInto(const IR::Value& value, oaknut::XReg reg) {
     }
 
     const auto current_location = ValueLocation(value.GetInst());
-    ASSERT(current_location);
+    assert(current_location);
     switch (current_location->kind) {
     case HostLoc::Kind::Gpr:
         code.MOV(reg, oaknut::XReg{current_location->index});
         break;
     case HostLoc::Kind::Fpr:
         code.FMOV(reg, oaknut::DReg{current_location->index});
-        // ASSERT size fits
+        // assert size fits
         break;
     case HostLoc::Kind::Spill:
         code.LDR(reg, SP, spill_offset + current_location->index * spill_slot_size);
@@ -538,7 +538,7 @@ void RegAlloc::LoadCopyInto(const IR::Value& value, oaknut::QReg reg) {
     }
 
     const auto current_location = ValueLocation(value.GetInst());
-    ASSERT(current_location);
+    assert(current_location);
     switch (current_location->kind) {
     case HostLoc::Kind::Gpr:
         code.FMOV(reg.toD(), oaknut::XReg{current_location->index});
@@ -551,7 +551,7 @@ void RegAlloc::LoadCopyInto(const IR::Value& value, oaknut::QReg reg) {
         code.LDR(reg, SP, spill_offset + current_location->index * spill_slot_size);
         break;
     case HostLoc::Kind::Flags:
-        UNREACHABLE(); //ASSERT(false && "Moving from flags into fprs is not currently supported");
+        std::terminate(); //unreachable //assert(false && "Moving from flags into fprs is not currently supported");
     }
 }
 
@@ -584,7 +584,7 @@ HostLocInfo& RegAlloc::ValueInfo(HostLoc host_loc) {
     case HostLoc::Kind::Spill:
         return spills[static_cast<size_t>(host_loc.index)];
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
@@ -599,7 +599,7 @@ HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
     } else if (const auto iter = std::find_if(spills.begin(), spills.end(), contains_value); iter != spills.end()) {
         return *iter;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 }  // namespace Dynarmic::Backend::Arm64
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h
index 22ab5af662..79ab9b3d96 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h
@@ -14,8 +14,8 @@
 #include <utility>
 #include <vector>
 
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 #include "dynarmic/mcl/is_instance_of_template.hpp"
 #include <oaknut/oaknut.hpp>
 #include <ankerl/unordered_dense.h>
@@ -186,7 +186,7 @@ public:
         } else if constexpr (size == 32) {
             return ReadW(arg);
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -203,7 +203,7 @@ public:
         } else if constexpr (size == 8) {
             return ReadB(arg);
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -225,7 +225,7 @@ public:
         } else if constexpr (size == 32) {
             return WriteW(inst);
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -242,7 +242,7 @@ public:
         } else if constexpr (size == 8) {
             return WriteB(inst);
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -262,7 +262,7 @@ public:
         } else if constexpr (size == 32) {
             return ReadWriteW(arg, inst);
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -279,7 +279,7 @@ public:
         } else if constexpr (size == 8) {
             return ReadWriteB(arg, inst);
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -370,7 +370,7 @@ void RAReg<T>::Realize() {
         reg = T{reg_alloc.RealizeReadWriteImpl<kind>(read_value, write_value)};
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/stack_layout.h b/src/dynarmic/src/dynarmic/backend/arm64/stack_layout.h
index 801b07c008..ce900081a3 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/stack_layout.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/stack_layout.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <array>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Backend::Arm64 {
 
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/verbose_debugging_output.h b/src/dynarmic/src/dynarmic/backend/arm64/verbose_debugging_output.h
index b5187f6375..75ad34d7e4 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/verbose_debugging_output.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/verbose_debugging_output.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <array>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/backend/arm64/stack_layout.h"
 
diff --git a/src/dynarmic/src/dynarmic/backend/block_range_information.cpp b/src/dynarmic/src/dynarmic/backend/block_range_information.cpp
index aa951d7708..bd7310194f 100644
--- a/src/dynarmic/src/dynarmic/backend/block_range_information.cpp
+++ b/src/dynarmic/src/dynarmic/backend/block_range_information.cpp
@@ -10,7 +10,7 @@
 
 #include <boost/icl/interval_map.hpp>
 #include <boost/icl/interval_set.hpp>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include <ankerl/unordered_dense.h>
 
 namespace Dynarmic::Backend {
diff --git a/src/dynarmic/src/dynarmic/backend/exception_handler.h b/src/dynarmic/src/dynarmic/backend/exception_handler.h
index ff116c5775..b62bd7ab71 100644
--- a/src/dynarmic/src/dynarmic/backend/exception_handler.h
+++ b/src/dynarmic/src/dynarmic/backend/exception_handler.h
@@ -12,7 +12,7 @@
 #include <memory>
 #include <optional>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #if defined(ARCHITECTURE_x86_64)
 namespace Dynarmic::Backend::X64 {
@@ -43,6 +43,7 @@ struct FakeCall {
 };
 #elif defined(ARCHITECTURE_riscv64)
 struct FakeCall {
+    u64 call_sepc;
 };
 #else
 #    error "Invalid architecture"
diff --git a/src/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp b/src/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp
index be44207f0a..edd7075846 100644
--- a/src/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp
+++ b/src/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp
@@ -19,8 +19,8 @@
 #include <bit>
 
 #include <fmt/format.h>
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 
 #include "dynarmic/backend/exception_handler.h"
 
@@ -87,7 +87,7 @@ private:
 };
 
 MachHandler::MachHandler() {
-#define KCHECK(x) ASSERT((x) == KERN_SUCCESS && "init failure at " #x)
+#define KCHECK(x) assert((x) == KERN_SUCCESS && "init failure at " #x)
     KCHECK(mach_port_allocate(mach_task_self(), MACH_PORT_RIGHT_RECEIVE, &server_port));
     KCHECK(mach_port_insert_right(mach_task_self(), server_port, server_port, MACH_MSG_TYPE_MAKE_SEND));
     KCHECK(task_set_exception_ports(mach_task_self(), EXC_MASK_BAD_ACCESS, server_port, EXCEPTION_STATE | MACH_EXCEPTION_CODES, THREAD_STATE));
diff --git a/src/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp b/src/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp
index 9f508f72e5..b563f33b86 100644
--- a/src/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp
+++ b/src/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,6 +8,7 @@
 
 #include <cstring>
 #include <functional>
+#include <algorithm>
 #include <memory>
 #include <mutex>
 #include <shared_mutex>
@@ -16,9 +17,9 @@
 #include <fmt/format.h>
 #include <ankerl/unordered_dense.h>
 #include "dynarmic/backend/exception_handler.h"
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/common/context.h"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #if defined(ARCHITECTURE_x86_64)
 #    include "dynarmic/backend/x64/block_of_code.h"
 #elif defined(ARCHITECTURE_arm64)
@@ -115,7 +116,7 @@ void RegisterHandler() {
 }
 
 void SigHandler::SigAction(int sig, siginfo_t* info, void* raw_context) {
-    DEBUG_ASSERT(sig == SIGSEGV || sig == SIGBUS);
+    assert(sig == SIGSEGV || sig == SIGBUS);
     CTX_DECLARE(raw_context);
 #if defined(ARCHITECTURE_x86_64)
     {
@@ -140,7 +141,15 @@ void SigHandler::SigAction(int sig, siginfo_t* info, void* raw_context) {
     }
     fmt::print(stderr, "Unhandled {} at pc {:#018x}\n", sig == SIGSEGV ? "SIGSEGV" : "SIGBUS", CTX_PC);
 #elif defined(ARCHITECTURE_riscv64)
-    UNREACHABLE();
+    {
+        std::shared_lock guard(sig_handler->code_block_infos_mutex);
+        if (const auto iter = sig_handler->FindCodeBlockInfo(CTX_SEPC); iter != sig_handler->code_block_infos.end()) {
+            FakeCall fc = iter->second.cb(CTX_SEPC);
+            CTX_SEPC = fc.call_sepc;
+            return;
+        }
+    }
+    fmt::print(stderr, "Unhandled {} at pc {:#018x}\n", sig == SIGSEGV ? "SIGSEGV" : "SIGBUS", CTX_SEPC);
 #else
 #    error "Invalid architecture"
 #endif
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp
index edb24761f6..575e6997ec 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp
@@ -8,7 +8,7 @@
 
 #include "dynarmic/backend/riscv64/a32_address_space.h"
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 #include "dynarmic/backend/riscv64/abi.h"
 #include "dynarmic/backend/riscv64/emit_riscv64.h"
@@ -94,7 +94,7 @@ void A32AddressSpace::EmitPrelude() {
 
 void A32AddressSpace::SetCursorPtr(CodePtr ptr) {
     ptrdiff_t offset = ptr - GetMemPtr<CodePtr>();
-    ASSERT(offset >= 0);
+    assert(offset >= 0);
     as.RewindBuffer(offset);
 }
 
@@ -128,7 +128,7 @@ void A32AddressSpace::Link(EmittedBlockInfo& block_info) {
             break;
         }
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 }
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp
index 3f395bfafb..f8f66fbf2b 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp
@@ -10,8 +10,8 @@
 #include <mutex>
 
 #include <boost/icl/interval_set.hpp>
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 
 #include "dynarmic/backend/riscv64/a32_address_space.h"
 #include "dynarmic/backend/riscv64/a32_core.h"
@@ -31,7 +31,7 @@ struct Jit::Impl final {
             , core(conf) {}
 
     HaltReason Run() {
-        ASSERT(!jit_interface->is_executing);
+        assert(!jit_interface->is_executing);
         jit_interface->is_executing = true;
         HaltReason hr = core.Run(current_address_space, current_state, &halt_reason);
         RequestCacheInvalidation();
@@ -40,9 +40,9 @@ struct Jit::Impl final {
     }
 
     HaltReason Step() {
-        ASSERT(!jit_interface->is_executing);
+        assert(!jit_interface->is_executing);
         jit_interface->is_executing = true;
-        UNIMPLEMENTED();
+        std::terminate(); //unimplemented
         RequestCacheInvalidation();
         jit_interface->is_executing = false;
         return HaltReason{};
@@ -110,7 +110,7 @@ struct Jit::Impl final {
 
 private:
     void RequestCacheInvalidation() {
-        // UNREACHABLE();
+        // std::terminate(); //unreachable
 
         invalidate_entire_cache = false;
         invalid_cache_ranges.clear();
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.cpp
index 70cd6bf0f1..3e9c8ecca1 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.cpp
@@ -9,7 +9,7 @@
 #include "dynarmic/backend/riscv64/a32_jitstate.h"
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Backend::RV64 {
 
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.h b/src/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.h
index 2fbb5819d9..ea0bce5fe3 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.h
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <array>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/frontend/A32/a32_location_descriptor.h"
 #include "dynarmic/ir/location_descriptor.h"
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/a64_interface.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/a64_interface.cpp
new file mode 100644
index 0000000000..cee46bd02b
--- /dev/null
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/a64_interface.cpp
@@ -0,0 +1,295 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+#include <memory>
+#include <mutex>
+
+#include <boost/icl/interval_set.hpp>
+#include <cassert>
+#include "common/common_types.h"
+
+#include "dynarmic/frontend/A64/a64_location_descriptor.h"
+#include "dynarmic/frontend/A64/translate/a64_translate.h"
+#include "dynarmic/interface/A64/config.h"
+#include "dynarmic/backend/riscv64/a32_core.h"
+#include "dynarmic/common/atomic.h"
+#include "dynarmic/ir/opt_passes.h"
+#include "dynarmic/interface/A64/a64.h"
+
+namespace Dynarmic::A64 {
+
+using namespace Dynarmic::Backend::RV64;
+using CodePtr = std::uint32_t*;
+
+struct Jit::Impl final {
+    Impl(Jit* jit_interface, A64::UserConfig conf)
+        : conf(conf)
+        //, current_address_space(conf)
+        , jit_interface(jit_interface) {}
+
+    HaltReason Run() {
+        assert(false);
+        return HaltReason{};
+    }
+
+    HaltReason Step() {
+        assert(false);
+        return HaltReason{};
+    }
+
+    void ClearCache() {
+        std::unique_lock lock{invalidation_mutex};
+        invalidate_entire_cache = true;
+        HaltExecution(HaltReason::CacheInvalidation);
+    }
+
+    void InvalidateCacheRange(u64 start_address, size_t length) {
+        std::unique_lock lock{invalidation_mutex};
+        const auto end_address = u64(start_address + length - 1);
+        invalid_cache_ranges.add(boost::icl::discrete_interval<u64>::closed(start_address, end_address));
+        HaltExecution(HaltReason::CacheInvalidation);
+    }
+
+    void Reset() {
+        assert(!is_executing);
+        //jit_state = {};
+    }
+
+    void HaltExecution(HaltReason hr) {
+        //Atomic::Or(&jit_state.halt_reason, u32(hr));
+    }
+
+    void ClearHalt(HaltReason hr) {
+        //Atomic::And(&jit_state.halt_reason, ~u32(hr));
+    }
+
+    u64 GetSP() const {
+        return 0;//jit_state.sp;
+    }
+
+    void SetSP(u64 value) {
+        //jit_state.sp = value;
+    }
+
+    u64 GetPC() const {
+        return 0;//jit_state.pc;
+    }
+
+    void SetPC(u64 value) {
+        //jit_state.pc = value;
+    }
+
+    u64 GetRegister(size_t index) const {
+        return 0;//index == 31 ? GetSP() : jit_state.regs.at(index);
+    }
+
+    void SetRegister(size_t index, u64 value) {
+        if (index == 31)
+            return SetSP(value);
+        //jit_state.regs.at(index) = value;
+    }
+
+    std::array<u64, 31> GetRegisters() const {
+        return {};//jit_state.regs;
+    }
+
+    void SetRegisters(const std::array<u64, 31>& value) {
+        //jit_state.regs = value;
+    }
+
+    Vector GetVector(size_t index) const {
+        //return {jit_state.vec.at(index * 2), jit_state.vec.at(index * 2 + 1)};
+        return Vector{};
+    }
+
+    void SetVector(size_t index, Vector value) {
+        //jit_state.vec.at(index * 2) = value[0];
+        //jit_state.vec.at(index * 2 + 1) = value[1];
+    }
+
+    std::array<Vector, 32> GetVectors() const {
+        std::array<Vector, 32> ret;
+        //static_assert(sizeof(ret) == sizeof(jit_state.vec));
+        //std::memcpy(ret.data(), jit_state.vec.data(), sizeof(jit_state.vec));
+        return ret;
+    }
+
+    void SetVectors(const std::array<Vector, 32>& value) {
+        //static_assert(sizeof(value) == sizeof(jit_state.vec));
+        //std::memcpy(jit_state.vec.data(), value.data(), sizeof(jit_state.vec));
+    }
+
+    u32 GetFpcr() const {
+        return 0;//jit_state.fpcr;
+    }
+
+    void SetFpcr(u32 value) {
+        //jit_state.fpcr = value;
+    }
+
+    u32 GetFpsr() const {
+        return 0;//jit_state.fpsr;
+    }
+
+    void SetFpsr(u32 value) {
+        //jit_state.fpsr = value;
+    }
+
+    u32 GetPstate() const {
+        return 0;//jit_state.pstate;
+    }
+
+    void SetPstate(u32 value) {
+        //jit_state.pstate = value;
+    }
+
+    void ClearExclusiveState() {
+        //jit_state.exclusive_state = 0;
+    }
+
+    bool IsExecuting() const {
+        return is_executing;
+    }
+
+    std::string Disassemble() const {
+        // const size_t size = reinterpret_cast<const char*>(block_of_code.getCurr()) - reinterpret_cast<const char*>(block_of_code.GetCodeBegin());
+        // auto const* p = reinterpret_cast<const char*>(block_of_code.GetCodeBegin());
+        // return Common::DisassemblePPC64(p, p + size);
+        return {};
+    }
+
+private:
+    void RequestCacheInvalidation() {
+        // std::terminate(); //unreachable
+        invalidate_entire_cache = false;
+        invalid_cache_ranges.clear();
+    }
+
+    A64::UserConfig conf;
+    //A64JitState jit_state{};
+    //A64AddressSpace current_address_space;
+    Jit* jit_interface;
+    volatile u32 halt_reason = 0;
+    bool is_executing = false;
+
+    boost::icl::interval_set<u64> invalid_cache_ranges;
+    bool invalidate_entire_cache = false;
+    std::mutex invalidation_mutex;
+};
+
+Jit::Jit(UserConfig conf) : impl(std::make_unique<Jit::Impl>(this, conf)) {}
+Jit::~Jit() = default;
+
+HaltReason Jit::Run() {
+    return impl->Run();
+}
+
+HaltReason Jit::Step() {
+    return impl->Step();
+}
+
+void Jit::ClearCache() {
+    impl->ClearCache();
+}
+
+void Jit::InvalidateCacheRange(u64 start_address, size_t length) {
+    impl->InvalidateCacheRange(start_address, length);
+}
+
+void Jit::Reset() {
+    impl->Reset();
+}
+
+void Jit::HaltExecution(HaltReason hr) {
+    impl->HaltExecution(hr);
+}
+
+void Jit::ClearHalt(HaltReason hr) {
+    impl->ClearHalt(hr);
+}
+
+u64 Jit::GetSP() const {
+    return impl->GetSP();
+}
+
+void Jit::SetSP(u64 value) {
+    impl->SetSP(value);
+}
+
+u64 Jit::GetPC() const {
+    return impl->GetPC();
+}
+
+void Jit::SetPC(u64 value) {
+    impl->SetPC(value);
+}
+
+u64 Jit::GetRegister(size_t index) const {
+    return impl->GetRegister(index);
+}
+
+void Jit::SetRegister(size_t index, u64 value) {
+    impl->SetRegister(index, value);
+}
+
+std::array<u64, 31> Jit::GetRegisters() const {
+    return impl->GetRegisters();
+}
+
+void Jit::SetRegisters(const std::array<u64, 31>& value) {
+    impl->SetRegisters(value);
+}
+
+Vector Jit::GetVector(size_t index) const {
+    return impl->GetVector(index);
+}
+
+void Jit::SetVector(size_t index, Vector value) {
+    impl->SetVector(index, value);
+}
+
+std::array<Vector, 32> Jit::GetVectors() const {
+    return impl->GetVectors();
+}
+
+void Jit::SetVectors(const std::array<Vector, 32>& value) {
+    impl->SetVectors(value);
+}
+
+u32 Jit::GetFpcr() const {
+    return impl->GetFpcr();
+}
+
+void Jit::SetFpcr(u32 value) {
+    impl->SetFpcr(value);
+}
+
+u32 Jit::GetFpsr() const {
+    return impl->GetFpsr();
+}
+
+void Jit::SetFpsr(u32 value) {
+    impl->SetFpsr(value);
+}
+
+u32 Jit::GetPstate() const {
+    return impl->GetPstate();
+}
+
+void Jit::SetPstate(u32 value) {
+    impl->SetPstate(value);
+}
+
+void Jit::ClearExclusiveState() {
+    impl->ClearExclusiveState();
+}
+
+bool Jit::IsExecuting() const {
+    return impl->IsExecuting();
+}
+
+std::string Jit::Disassemble() const {
+    return impl->Disassemble();
+}
+
+}  // namespace Dynarmic::A64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/code_block.h b/src/dynarmic/src/dynarmic/backend/riscv64/code_block.h
index 02bfa44eec..163063f187 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/code_block.h
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/code_block.h
@@ -13,13 +13,16 @@
 
 #include <sys/mman.h>
 
+#include <cassert>
+#include "common/common_types.h"
+
 namespace Dynarmic::Backend::RV64 {
 
 class CodeBlock {
 public:
     explicit CodeBlock(std::size_t size) noexcept : memsize(size) {
         mem = (u8*)mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, -1, 0);
-        ASSERT(mem != nullptr);
+        assert(mem != nullptr);
     }
 
     ~CodeBlock() noexcept {
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp
index 5ce7dee1e1..e4a7d8d7c3 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp
@@ -35,39 +35,39 @@ void EmitIR<IR::Opcode::Identity>(biscuit::Assembler&, EmitContext& ctx, IR::Ins
 
 template<>
 void EmitIR<IR::Opcode::Breakpoint>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::CallHostFunction>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PushRSB>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::GetCarryFromOp>(biscuit::Assembler&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.IsValueLive(inst));
+    assert(ctx.reg_alloc.IsValueLive(inst));
 }
 
 template<>
 void EmitIR<IR::Opcode::GetOverflowFromOp>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::GetGEFromOp>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::GetNZCVFromOp>(biscuit::Assembler&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.IsValueLive(inst));
+    assert(ctx.reg_alloc.IsValueLive(inst));
 }
 
 template<>
@@ -87,12 +87,12 @@ void EmitIR<IR::Opcode::GetNZFromOp>(biscuit::Assembler& as, EmitContext& ctx, I
 
 template<>
 void EmitIR<IR::Opcode::GetUpperFromOp>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::GetLowerFromOp>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
@@ -109,7 +109,7 @@ void EmitIR<IR::Opcode::GetCFlagFromNZCV>(biscuit::Assembler& as, EmitContext& c
 
 template<>
 void EmitIR<IR::Opcode::NZCVFromPackedFlags>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 EmittedBlockInfo EmitRV64(biscuit::Assembler& as, IR::Block block, const EmitConfig& emit_conf) {
@@ -143,7 +143,7 @@ EmittedBlockInfo EmitRV64(biscuit::Assembler& as, IR::Block block, const EmitCon
 #undef A32OPC
 #undef A64OPC
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.h b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.h
index 68d30d5e15..7c49ce2afa 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.h
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -11,7 +11,7 @@
 #include <vector>
 
 #include <biscuit/label.hpp>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace biscuit {
 class Assembler;
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp
index 572f197955..18d3469123 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp
@@ -108,7 +108,7 @@ void EmitA32Cond(biscuit::Assembler& as, EmitContext&, IR::Cond cond, biscuit::L
         as.BNEZ(Xscratch0, label);
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -205,7 +205,7 @@ void EmitA32Terminal(biscuit::Assembler& as, EmitContext& ctx) {
 
 template<>
 void EmitIR<IR::Opcode::A32SetCheckBit>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
@@ -220,17 +220,17 @@ void EmitIR<IR::Opcode::A32GetRegister>(biscuit::Assembler& as, EmitContext& ctx
 
 template<>
 void EmitIR<IR::Opcode::A32GetExtendedRegister32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32GetExtendedRegister64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32GetVector>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
@@ -249,27 +249,27 @@ void EmitIR<IR::Opcode::A32SetRegister>(biscuit::Assembler& as, EmitContext& ctx
 
 template<>
 void EmitIR<IR::Opcode::A32SetExtendedRegister32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetExtendedRegister64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetVector>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32GetCpsr>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetCpsr>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
@@ -284,17 +284,17 @@ void EmitIR<IR::Opcode::A32SetCpsrNZCV>(biscuit::Assembler& as, EmitContext& ctx
 
 template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZCVRaw>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZCVQ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
@@ -302,7 +302,7 @@ void EmitIR<IR::Opcode::A32SetCpsrNZC>(biscuit::Assembler& as, EmitContext& ctx,
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
 
     // TODO: Add full implementation
-    ASSERT(!args[0].IsImmediate() && !args[1].IsImmediate());
+    assert(!args[0].IsImmediate() && !args[1].IsImmediate());
 
     auto Xnz = ctx.reg_alloc.ReadX(args[0]);
     auto Xc = ctx.reg_alloc.ReadX(args[1]);
@@ -318,82 +318,82 @@ void EmitIR<IR::Opcode::A32SetCpsrNZC>(biscuit::Assembler& as, EmitContext& ctx,
 
 template<>
 void EmitIR<IR::Opcode::A32GetCFlag>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32OrQFlag>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32GetGEFlags>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetGEFlags>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetGEFlagsCompressed>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32BXWritePC>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32UpdateUpperLocationDescriptor>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CallSupervisor>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExceptionRaised>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32DataSynchronizationBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32DataMemoryBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32InstructionSynchronizationBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32GetFpscr>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetFpscr>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32GetFpscrNZCV>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetFpscrNZCV>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_coprocessor.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_coprocessor.cpp
index a014d57fc3..bd5ff215e6 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_coprocessor.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_coprocessor.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2024 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -19,37 +22,37 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocInternalOperation>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocSendOneWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocSendTwoWords>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocGetOneWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocGetTwoWords>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocLoadWords>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocStoreWords>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_memory.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_memory.cpp
index f9a3aabf6b..cdcd46231c 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_memory.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_memory.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2024 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -19,87 +22,87 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::A32ClearExclusive>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ReadMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ReadMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ReadMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ReadMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveReadMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveReadMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveReadMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveReadMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32WriteMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32WriteMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32WriteMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32WriteMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveWriteMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveWriteMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveWriteMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveWriteMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64.cpp
index 38ea167ff7..18f60833a2 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2024 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -19,182 +22,182 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::A64SetCheckBit>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetCFlag>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetNZCVRaw>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetNZCVRaw>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetNZCV>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetW>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetX>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetS>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetD>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetQ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetSP>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetFPCR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetFPSR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetW>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetX>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetS>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetD>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetQ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetSP>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetFPCR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetFPSR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetPC>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64CallSupervisor>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExceptionRaised>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64DataCacheOperationRaised>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64InstructionCacheOperationRaised>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64DataSynchronizationBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64DataMemoryBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64InstructionSynchronizationBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetCNTFRQ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetCNTPCT>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetCTR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetDCZID>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetTPIDR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetTPIDRRO>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetTPIDR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64_memory.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64_memory.cpp
index a5c0c1b8d3..3d09e8ab62 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64_memory.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64_memory.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2024 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -19,107 +22,107 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::A64ClearExclusive>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ReadMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ReadMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ReadMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ReadMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ReadMemory128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64WriteMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64WriteMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64WriteMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64WriteMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64WriteMemory128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_cryptography.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_cryptography.cpp
index c1d3fa0e26..e7aa5fe8e4 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_cryptography.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_cryptography.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2024 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -19,82 +22,82 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::CRC32Castagnoli8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32Castagnoli16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32Castagnoli32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32Castagnoli64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32ISO8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32ISO16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32ISO32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32ISO64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::AESDecryptSingleRound>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::AESEncryptSingleRound>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::AESInverseMixColumns>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::AESMixColumns>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SM4AccessSubstitutionBox>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SHA256Hash>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SHA256MessageSchedule0>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SHA256MessageSchedule1>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_data_processing.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_data_processing.cpp
index 51ed027a05..e92d5e78d8 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_data_processing.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_data_processing.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2024 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -19,67 +22,67 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::Pack2x32To1x64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::Pack2x64To1x128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::LeastSignificantWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::LeastSignificantHalf>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::LeastSignificantByte>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::MostSignificantWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::MostSignificantBit>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::IsZero32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::IsZero64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::TestBit>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ConditionalSelect32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ConditionalSelect64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ConditionalSelectNZCV>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
@@ -92,8 +95,8 @@ void EmitIR<IR::Opcode::LogicalShiftLeft32>(biscuit::Assembler& as, EmitContext&
     auto& carry_arg = args[2];
 
     // TODO: Add full implementation
-    ASSERT(carry_inst != nullptr);
-    ASSERT(shift_arg.IsImmediate());
+    assert(carry_inst != nullptr);
+    assert(shift_arg.IsImmediate());
 
     auto Xresult = ctx.reg_alloc.WriteX(inst);
     auto Xcarry_out = ctx.reg_alloc.WriteX(carry_inst);
@@ -121,7 +124,7 @@ void EmitIR<IR::Opcode::LogicalShiftLeft32>(biscuit::Assembler& as, EmitContext&
 
 template<>
 void EmitIR<IR::Opcode::LogicalShiftLeft64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
@@ -133,8 +136,8 @@ void EmitIR<IR::Opcode::LogicalShiftRight32>(biscuit::Assembler& as, EmitContext
     auto& shift_arg = args[1];
 
     // TODO: Add full implementation
-    ASSERT(carry_inst == nullptr);
-    ASSERT(shift_arg.IsImmediate());
+    assert(carry_inst == nullptr);
+    assert(shift_arg.IsImmediate());
 
     const u8 shift = shift_arg.GetImmediateU8();
     auto Xresult = ctx.reg_alloc.WriteX(inst);
@@ -150,72 +153,72 @@ void EmitIR<IR::Opcode::LogicalShiftRight32>(biscuit::Assembler& as, EmitContext
 
 template<>
 void EmitIR<IR::Opcode::LogicalShiftRight64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ArithmeticShiftRight32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ArithmeticShiftRight64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
-void EmitIR<IR::Opcode::RotateRight32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+void EmitIR<IR::Opcode::BitRotateRight32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
+    std::terminate(); //unimplemented
 }
 
 template<>
-void EmitIR<IR::Opcode::RotateRight64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+void EmitIR<IR::Opcode::BitRotateRight64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::RotateRightExtended>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::LogicalShiftLeftMasked32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::LogicalShiftLeftMasked64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::LogicalShiftRightMasked32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::LogicalShiftRightMasked64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ArithmeticShiftRightMasked32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ArithmeticShiftRightMasked64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::RotateRightMasked32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::RotateRightMasked64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<size_t bitsize>
@@ -261,7 +264,7 @@ static void AddImmWithFlags(biscuit::Assembler& as, biscuit::GPR rd, biscuit::GP
         as.SLLI(Xscratch1, Xscratch1, 28);
         as.OR(flags, flags, Xscratch1);
     } else {
-        UNIMPLEMENTED();
+        std::terminate(); //unimplemented
     }
 }
 
@@ -276,7 +279,7 @@ static void EmitAddSub(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst)
     auto Xa = ctx.reg_alloc.ReadX(args[0]);
 
     if (overflow_inst) {
-        UNIMPLEMENTED();
+        std::terminate(); //unimplemented
     } else if (nzcv_inst) {
         if (args[1].IsImmediate()) {
             const u64 imm = args[1].GetImmediateU64();
@@ -291,17 +294,17 @@ static void EmitAddSub(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst)
                     AddImmWithFlags<bitsize>(as, *Xresult, *Xa, sub ? -imm : imm, *Xflags);
                 }
             } else {
-                UNIMPLEMENTED();
+                std::terminate(); //unimplemented
             }
         } else {
-            UNIMPLEMENTED();
+            std::terminate(); //unimplemented
         }
     } else {
         if (args[1].IsImmediate()) {
             const u64 imm = args[1].GetImmediateU64();
 
             if (args[2].IsImmediate()) {
-                UNIMPLEMENTED();
+                std::terminate(); //unimplemented
             } else {
                 auto Xnzcv = ctx.reg_alloc.ReadX(args[2]);
                 RegAlloc::Realize(Xresult, Xa, Xnzcv);
@@ -314,7 +317,7 @@ static void EmitAddSub(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst)
                 as.ADDW(Xresult, Xa, Xscratch0);
             }
         } else {
-            UNIMPLEMENTED();
+            std::terminate(); //unimplemented
         }
     }
 }
@@ -326,7 +329,7 @@ void EmitIR<IR::Opcode::Add32>(biscuit::Assembler& as, EmitContext& ctx, IR::Ins
 
 template<>
 void EmitIR<IR::Opcode::Add64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
@@ -336,237 +339,237 @@ void EmitIR<IR::Opcode::Sub32>(biscuit::Assembler& as, EmitContext& ctx, IR::Ins
 
 template<>
 void EmitIR<IR::Opcode::Sub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::Mul32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::Mul64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedMultiplyHigh64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedMultiplyHigh64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedDiv32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedDiv64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedDiv32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedDiv64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::And32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::And64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::AndNot32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::AndNot64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::Eor32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::Eor64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::Or32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::Or64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::Not32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::Not64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignExtendByteToWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignExtendHalfToWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignExtendByteToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignExtendHalfToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignExtendWordToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ZeroExtendByteToWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ZeroExtendHalfToWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ZeroExtendByteToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ZeroExtendHalfToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ZeroExtendWordToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ZeroExtendLongToQuad>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ByteReverseWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ByteReverseHalf>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ByteReverseDual>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::CountLeadingZeros32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::CountLeadingZeros64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ExtractRegister32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ExtractRegister64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ReplicateBit32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ReplicateBit64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::MaxSigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::MaxSigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::MaxUnsigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::MaxUnsigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::MinSigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::MinSigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::MinUnsigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::MinUnsigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_floating_point.cpp
index 94fa474e38..2c16b7052c 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_floating_point.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_floating_point.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2024 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -19,442 +22,442 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::FPAbs16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPAbs32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPAbs64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPCompare32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPCompare64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDiv32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDiv64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMax32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMax64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMaxNumeric32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMaxNumeric64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMin32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMin64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMinNumeric32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMinNumeric64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMul32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMul64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulX32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulX64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPNeg16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPNeg32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPNeg64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipEstimate16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipEstimate32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipEstimate64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipExponent16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipExponent32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipExponent64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipStepFused16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipStepFused32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipStepFused64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRoundInt16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRoundInt32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRoundInt64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRSqrtEstimate16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRSqrtEstimate32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRSqrtEstimate64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRSqrtStepFused16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRSqrtStepFused32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRSqrtStepFused64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSqrt32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSqrt64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToHalf>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToHalf>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedS64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedU64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedS64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedU64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedS64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedU64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedU16ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedS16ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedU16ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedS16ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedU32ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedS32ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedU32ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedS32ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedU64ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedU64ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedS64ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedS64ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_packed.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_packed.cpp
index 5272dbb114..6c7a575907 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_packed.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_packed.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2024 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -19,172 +22,172 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::PackedAddU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedAddS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSubU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSubS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedAddSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedAddSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSubAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSubAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedAddU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedAddS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedSubU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedSubS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedAbsDiffSumU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSelect>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_saturation.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_saturation.cpp
index 3bceeb080d..fc8fd5103c 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_saturation.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_saturation.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2024 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -19,112 +22,112 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAddWithFlag32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSubWithFlag32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturation>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturation>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSub8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedSub8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector.cpp
index 31cfd65cdf..5c8d79b5a4 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2024 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -19,1377 +22,1377 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::VectorGetElement8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorGetElement16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorGetElement32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorGetElement64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSetElement8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSetElement16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSetElement32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSetElement64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorAbs8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorAbs16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorAbs32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorAbs64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorAnd>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorAndNot>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorArithmeticShiftRight8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorArithmeticShiftRight16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorArithmeticShiftRight32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorArithmeticShiftRight64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorArithmeticVShift8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorArithmeticVShift16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorArithmeticVShift32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorArithmeticVShift64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcastLower8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcastLower16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcastLower32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcast8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcast16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcast32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcast64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcastElementLower8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcastElementLower16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcastElementLower32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcastElement8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcastElement16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcastElement32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorBroadcastElement64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorCountLeadingZeros8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorCountLeadingZeros16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorCountLeadingZeros32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveEven8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveEven16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveEven32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveEven64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveEvenLower8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveEvenLower16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveEvenLower32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveOdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveOdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveOdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveOdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveOddLower8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveOddLower16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorDeinterleaveOddLower32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorEor>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorEqual8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorEqual16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorEqual32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorEqual64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorEqual128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorExtract>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorExtractLower>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorGreaterS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorGreaterS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorGreaterS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorGreaterS64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorHalvingAddS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorHalvingAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorHalvingAddS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorHalvingAddU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorHalvingAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorHalvingAddU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorHalvingSubS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorHalvingSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorHalvingSubS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorHalvingSubU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorHalvingSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorHalvingSubU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorInterleaveLower8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorInterleaveLower16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorInterleaveLower32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorInterleaveLower64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorInterleaveUpper8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorInterleaveUpper16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorInterleaveUpper32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorInterleaveUpper64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorLogicalShiftLeft8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorLogicalShiftLeft16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorLogicalShiftLeft32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorLogicalShiftLeft64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorLogicalShiftRight8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorLogicalShiftRight16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorLogicalShiftRight32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorLogicalShiftRight64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorLogicalVShift8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorLogicalVShift16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorLogicalVShift32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorLogicalVShift64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMaxS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMaxS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMaxS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMaxS64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMaxU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMaxU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMaxU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMaxU64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMinS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMinS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMinS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMinS64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMinU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMinU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMinU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMinU64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMultiply8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMultiply16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMultiply32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMultiply64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMultiplySignedWiden8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMultiplySignedWiden16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMultiplySignedWiden32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMultiplyUnsignedWiden8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMultiplyUnsignedWiden16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorMultiplyUnsignedWiden32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorNarrow16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorNarrow32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorNarrow64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorNot>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorOr>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedAddLower8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedAddLower16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedAddLower32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedAddSignedWiden8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedAddSignedWiden16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedAddSignedWiden32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedAddUnsignedWiden8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedAddUnsignedWiden16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedAddUnsignedWiden32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMaxS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMaxS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMaxS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMaxU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMaxU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMaxU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMinS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMinS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMinS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMinU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMinU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMinU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMaxLowerS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMaxLowerS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMaxLowerS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMaxLowerU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMaxLowerU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMaxLowerU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMinLowerS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMinLowerS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMinLowerS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMinLowerU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMinLowerU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPairedMinLowerU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPolynomialMultiply8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPolynomialMultiplyLong8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPolynomialMultiplyLong64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorPopulationCount>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorReverseBits>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorReverseElementsInHalfGroups8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorReverseElementsInWordGroups8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorReverseElementsInWordGroups16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorReverseElementsInLongGroups8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorReverseElementsInLongGroups16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorReverseElementsInLongGroups32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorReduceAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorReduceAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorReduceAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorReduceAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRotateWholeVectorRight>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingHalvingAddS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingHalvingAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingHalvingAddS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingHalvingAddU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingHalvingAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingHalvingAddU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingShiftLeftS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingShiftLeftS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingShiftLeftS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingShiftLeftS64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingShiftLeftU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingShiftLeftU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingShiftLeftU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorRoundingShiftLeftU64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignExtend8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignExtend16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignExtend32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignExtend64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedAbsoluteDifference8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedAbsoluteDifference16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedAbsoluteDifference32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedMultiply16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedMultiply32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAbs8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAbs16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAbs32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAbs64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAccumulateUnsigned8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAccumulateUnsigned16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAccumulateUnsigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAccumulateUnsigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedDoublingMultiplyHigh16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedDoublingMultiplyHigh32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedDoublingMultiplyHighRounding16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedDoublingMultiplyHighRounding32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedDoublingMultiplyLong16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedDoublingMultiplyLong32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedNarrowToSigned16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedNarrowToSigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedNarrowToSigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedNarrowToUnsigned16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedNarrowToUnsigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedNarrowToUnsigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedNeg8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedNeg16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedNeg32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedNeg64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedShiftLeft8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedShiftLeft16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedShiftLeft32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedShiftLeft64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedShiftLeftUnsigned8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedShiftLeftUnsigned16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedShiftLeftUnsigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedShiftLeftUnsigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSub8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorTable>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorTableLookup64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorTableLookup128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorTranspose8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorTranspose16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorTranspose32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorTranspose64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedAbsoluteDifference8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedAbsoluteDifference16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedAbsoluteDifference32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedMultiply16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedMultiply32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedRecipEstimate>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedRecipSqrtEstimate>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAccumulateSigned8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAccumulateSigned16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAccumulateSigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAccumulateSigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedNarrow16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedNarrow32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedNarrow64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedShiftLeft8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedShiftLeft16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedShiftLeft32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedShiftLeft64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorZeroExtend8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorZeroExtend16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorZeroExtend32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorZeroExtend64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorZeroUpper>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::ZeroVector>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_floating_point.cpp
index c3bf9708d3..ff2731050a 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_floating_point.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_floating_point.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2024 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -19,337 +22,337 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::FPVectorAbs16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorAbs32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorAbs64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorDiv32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorDiv64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorEqual16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorEqual32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorEqual64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorFromHalf32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorFromSignedFixed32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorFromSignedFixed64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorFromUnsignedFixed32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorFromUnsignedFixed64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorGreater32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorGreater64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorGreaterEqual32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorGreaterEqual64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMax32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMax64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMaxNumeric32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMaxNumeric64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMin32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMin64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMinNumeric32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMinNumeric64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMul32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMul64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMulAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMulAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMulAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMulX32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMulX64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorNeg16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorNeg32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorNeg64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorPairedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorPairedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorPairedAddLower32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorPairedAddLower64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRecipEstimate16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRecipEstimate32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRecipEstimate64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRecipStepFused16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRecipStepFused32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRecipStepFused64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRoundInt16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRoundInt32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRoundInt64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtEstimate16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtEstimate32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtEstimate64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtStepFused16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtStepFused32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtStepFused64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorSqrt32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorSqrt64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToHalf32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToSignedFixed16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToSignedFixed32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToSignedFixed64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToUnsignedFixed16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToUnsignedFixed32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToUnsignedFixed64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_saturation.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_saturation.cpp
index 0d3868ec83..28330ddca5 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_saturation.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_saturation.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2024 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -19,82 +22,82 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedSub8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedSub8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    UNIMPLEMENTED();
+    std::terminate(); //unimplemented
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/exclusive_monitor.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/exclusive_monitor.cpp
new file mode 100644
index 0000000000..b3585c64ea
--- /dev/null
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/exclusive_monitor.cpp
@@ -0,0 +1,54 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+#include "dynarmic/interface/exclusive_monitor.h"
+
+#include <algorithm>
+
+namespace Dynarmic {
+
+ExclusiveMonitor::ExclusiveMonitor(std::size_t processor_count)
+        : exclusive_addresses(processor_count, INVALID_EXCLUSIVE_ADDRESS), exclusive_values(processor_count) {}
+
+size_t ExclusiveMonitor::GetProcessorCount() const {
+    return exclusive_addresses.size();
+}
+
+void ExclusiveMonitor::Lock() {
+    lock.Lock();
+}
+
+void ExclusiveMonitor::Unlock() {
+    lock.Unlock();
+}
+
+bool ExclusiveMonitor::CheckAndClear(size_t processor_id, VAddr address) {
+    const VAddr masked_address = address & RESERVATION_GRANULE_MASK;
+
+    Lock();
+    if (exclusive_addresses[processor_id] != masked_address) {
+        Unlock();
+        return false;
+    }
+
+    for (VAddr& other_address : exclusive_addresses) {
+        if (other_address == masked_address) {
+            other_address = INVALID_EXCLUSIVE_ADDRESS;
+        }
+    }
+    return true;
+}
+
+void ExclusiveMonitor::Clear() {
+    Lock();
+    std::fill(exclusive_addresses.begin(), exclusive_addresses.end(), INVALID_EXCLUSIVE_ADDRESS);
+    Unlock();
+}
+
+void ExclusiveMonitor::ClearProcessor(size_t processor_id) {
+    Lock();
+    exclusive_addresses[processor_id] = INVALID_EXCLUSIVE_ADDRESS;
+    Unlock();
+}
+
+}  // namespace Dynarmic
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp
index 4ab5d43db8..282ff06a7f 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp
@@ -11,8 +11,8 @@
 #include <algorithm>
 #include <array>
 
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 
 #include "dynarmic/common/always_false.h"
 
@@ -44,19 +44,19 @@ bool Argument::GetImmediateU1() const {
 
 u8 Argument::GetImmediateU8() const {
     const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x100);
+    assert(imm < 0x100);
     return u8(imm);
 }
 
 u16 Argument::GetImmediateU16() const {
     const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x10000);
+    assert(imm < 0x10000);
     return u16(imm);
 }
 
 u32 Argument::GetImmediateU32() const {
     const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x100000000);
+    assert(imm < 0x100000000);
     return u32(imm);
 }
 
@@ -65,12 +65,12 @@ u64 Argument::GetImmediateU64() const {
 }
 
 IR::Cond Argument::GetImmediateCond() const {
-    ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
+    assert(IsImmediate() && GetType() == IR::Type::Cond);
     return value.GetCond();
 }
 
 IR::AccType Argument::GetImmediateAccType() const {
-    ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
+    assert(IsImmediate() && GetType() == IR::Type::AccType);
     return value.GetAccType();
 }
 
@@ -79,7 +79,7 @@ bool HostLocInfo::Contains(const IR::Inst* value) const {
 }
 
 void HostLocInfo::SetupScratchLocation() {
-    ASSERT(IsCompletelyEmpty());
+    assert(IsCompletelyEmpty());
     realized = true;
 }
 
@@ -104,7 +104,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
         const IR::Value arg = inst->GetArg(i);
         ret[i].value = arg;
         if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
-            ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
+            assert(ValueLocation(arg.GetInst()) && "argument must already been defined");
             ValueInfo(arg.GetInst()).uses_this_inst++;
         }
     }
@@ -128,7 +128,7 @@ void RegAlloc::UpdateAllUses() {
 }
 
 void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
-    ASSERT(!ValueLocation(inst));
+    assert(!ValueLocation(inst));
 
     if (arg.value.IsImmediate()) {
         inst->ReplaceUsesWith(arg.value);
@@ -142,15 +142,15 @@ void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
 
 void RegAlloc::AssertNoMoreUses() const {
     const auto is_empty = [](const auto& i) { return i.IsCompletelyEmpty(); };
-    ASSERT(std::all_of(gprs.begin(), gprs.end(), is_empty));
-    ASSERT(std::all_of(fprs.begin(), fprs.end(), is_empty));
-    ASSERT(std::all_of(spills.begin(), spills.end(), is_empty));
+    assert(std::all_of(gprs.begin(), gprs.end(), is_empty));
+    assert(std::all_of(fprs.begin(), fprs.end(), is_empty));
+    assert(std::all_of(spills.begin(), spills.end(), is_empty));
 }
 
 template<HostLoc::Kind kind>
 u32 RegAlloc::GenerateImmediate(const IR::Value& value) {
     // TODO
-    // ASSERT(value.GetType() != IR::Type::U1);
+    // assert(value.GetType() != IR::Type::U1);
 
     if constexpr (kind == HostLoc::Kind::Gpr) {
         const u32 new_location_index = AllocateRegister(gprs, gpr_order);
@@ -161,9 +161,9 @@ u32 RegAlloc::GenerateImmediate(const IR::Value& value) {
 
         return new_location_index;
     } else if constexpr (kind == HostLoc::Kind::Fpr) {
-        UNIMPLEMENTED();
+        std::terminate(); //unimplemented
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
     return 0;
 }
@@ -175,15 +175,15 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
     }
 
     const auto current_location = ValueLocation(value.GetInst());
-    ASSERT(current_location);
+    assert(current_location);
 
     if (current_location->kind == required_kind) {
         ValueInfo(*current_location).realized = true;
         return current_location->index;
     }
 
-    ASSERT(!ValueInfo(*current_location).realized);
-    ASSERT(!ValueInfo(*current_location).locked);
+    assert(!ValueInfo(*current_location).realized);
+    assert(!ValueInfo(*current_location).locked);
 
     if constexpr (required_kind == HostLoc::Kind::Gpr) {
         const u32 new_location_index = AllocateRegister(gprs, gpr_order);
@@ -191,10 +191,10 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
 
         switch (current_location->kind) {
         case HostLoc::Kind::Gpr:
-            UNREACHABLE(); //logic error
+            std::terminate(); //unreachable //logic error
         case HostLoc::Kind::Fpr:
             as.FMV_X_D(biscuit::GPR(new_location_index), biscuit::FPR{current_location->index});
-            // ASSERT size fits
+            // assert size fits
             break;
         case HostLoc::Kind::Spill:
             as.LD(biscuit::GPR{new_location_index}, spill_offset + current_location->index * spill_slot_size, biscuit::sp);
@@ -213,7 +213,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
             as.FMV_D_X(biscuit::FPR{new_location_index}, biscuit::GPR(current_location->index));
             break;
         case HostLoc::Kind::Fpr:
-            UNREACHABLE(); //logic error
+            std::terminate(); //unreachable //logic error
         case HostLoc::Kind::Spill:
             as.FLD(biscuit::FPR{new_location_index}, spill_offset + current_location->index * spill_slot_size, biscuit::sp);
             break;
@@ -223,13 +223,13 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
         fprs[new_location_index].realized = true;
         return new_location_index;
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
 template<HostLoc::Kind required_kind>
 u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
-    ASSERT(!ValueLocation(value));
+    assert(!ValueLocation(value));
 
     const auto setup_location = [&](HostLocInfo& info) {
         info = {};
@@ -250,7 +250,7 @@ u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
         setup_location(fprs[new_location_index]);
         return new_location_index;
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -274,7 +274,7 @@ u32 RegAlloc::AllocateRegister(const std::array<HostLocInfo, 32>& regs, const st
 }
 
 void RegAlloc::SpillGpr(u32 index) {
-    ASSERT(!gprs[index].locked && !gprs[index].realized);
+    assert(!gprs[index].locked && !gprs[index].realized);
     if (gprs[index].values.empty()) {
         return;
     }
@@ -284,7 +284,7 @@ void RegAlloc::SpillGpr(u32 index) {
 }
 
 void RegAlloc::SpillFpr(u32 index) {
-    ASSERT(!fprs[index].locked && !fprs[index].realized);
+    assert(!fprs[index].locked && !fprs[index].realized);
     if (fprs[index].values.empty()) {
         return;
     }
@@ -295,7 +295,7 @@ void RegAlloc::SpillFpr(u32 index) {
 
 u32 RegAlloc::FindFreeSpill() const {
     const auto iter = std::find_if(spills.begin(), spills.end(), [](const HostLocInfo& info) { return info.values.empty(); });
-    ASSERT(iter != spills.end() && "All spill locations are full");
+    assert(iter != spills.end() && "All spill locations are full");
     return static_cast<u32>(iter - spills.begin());
 }
 
@@ -322,7 +322,7 @@ HostLocInfo& RegAlloc::ValueInfo(HostLoc host_loc) {
     case HostLoc::Kind::Spill:
         return spills[size_t(host_loc.index)];
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
@@ -336,7 +336,7 @@ HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
     } else if (const auto iter = std::find_if(spills.begin(), spills.end(), contains_value); iter != gprs.end()) {
         return *iter;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 }  // namespace Dynarmic::Backend::RV64
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.h b/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.h
index be826e63f6..7a5feef5ca 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.h
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.h
@@ -16,8 +16,8 @@
 
 #include <biscuit/assembler.hpp>
 #include <biscuit/registers.hpp>
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 #include "dynarmic/mcl/is_instance_of_template.hpp"
 #include <ankerl/unordered_dense.h>
 
diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/stack_layout.h b/src/dynarmic/src/dynarmic/backend/riscv64/stack_layout.h
index 082e68aa6d..ca381520ea 100644
--- a/src/dynarmic/src/dynarmic/backend/riscv64/stack_layout.h
+++ b/src/dynarmic/src/dynarmic/backend/riscv64/stack_layout.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <array>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Backend::RV64 {
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp b/src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp
index 80f0f9cc2f..f7e6f06a64 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp
@@ -14,9 +14,9 @@
 
 #include <fmt/format.h>
 #include <fmt/ostream.h>
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include <boost/container/static_vector.hpp>
 
 #include "dynarmic/backend/x64/a32_jitstate.h"
@@ -56,7 +56,7 @@ static Xbyak::Address MJitStateExtReg(A32::ExtReg reg) {
         const size_t index = size_t(reg) - size_t(A32::ExtReg::Q0);
         return xword[BlockOfCode::ABI_JIT_PTR + offsetof(A32JitState, ExtReg) + 2 * sizeof(u64) * index];
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 A32EmitContext::A32EmitContext(const A32::UserConfig& conf, RegAlloc& reg_alloc, IR::Block& block)
@@ -135,7 +135,7 @@ A32EmitX64::BlockDescriptor A32EmitX64::Emit(IR::Block& block) {
 #undef A32OPC
 #undef A64OPC
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
         reg_alloc.EndOfAllocScope();
 #ifndef NDEBUG
@@ -183,11 +183,11 @@ void A32EmitX64::InvalidateCacheRanges(const boost::icl::interval_set<u32>& rang
 
 void A32EmitX64::EmitCondPrelude(const A32EmitContext& ctx) {
     if (ctx.block.GetCondition() == IR::Cond::AL) {
-        ASSERT(!ctx.block.HasConditionFailedLocation());
+        assert(!ctx.block.HasConditionFailedLocation());
         return;
     }
 
-    ASSERT(ctx.block.HasConditionFailedLocation());
+    assert(ctx.block.HasConditionFailedLocation());
 
     Xbyak::Label pass = EmitCond(ctx.block.GetCondition());
     if (conf.enable_cycle_counting) {
@@ -285,7 +285,7 @@ void A32EmitX64::EmitA32GetRegister(A32EmitContext& ctx, IR::Inst* inst) {
 
 void A32EmitX64::EmitA32GetExtendedRegister32(A32EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsSingleExtReg(reg));
+    assert(A32::IsSingleExtReg(reg));
 
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     code.movss(result, MJitStateExtReg(reg));
@@ -294,7 +294,7 @@ void A32EmitX64::EmitA32GetExtendedRegister32(A32EmitContext& ctx, IR::Inst* ins
 
 void A32EmitX64::EmitA32GetExtendedRegister64(A32EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg));
+    assert(A32::IsDoubleExtReg(reg));
 
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     code.movsd(result, MJitStateExtReg(reg));
@@ -303,7 +303,7 @@ void A32EmitX64::EmitA32GetExtendedRegister64(A32EmitContext& ctx, IR::Inst* ins
 
 void A32EmitX64::EmitA32GetVector(A32EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    assert(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
 
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     if (A32::IsDoubleExtReg(reg)) {
@@ -332,7 +332,7 @@ void A32EmitX64::EmitA32SetRegister(A32EmitContext& ctx, IR::Inst* inst) {
 void A32EmitX64::EmitA32SetExtendedRegister32(A32EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsSingleExtReg(reg));
+    assert(A32::IsSingleExtReg(reg));
 
     if (args[1].IsInXmm(ctx.reg_alloc)) {
         Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[1]);
@@ -346,7 +346,7 @@ void A32EmitX64::EmitA32SetExtendedRegister32(A32EmitContext& ctx, IR::Inst* ins
 void A32EmitX64::EmitA32SetExtendedRegister64(A32EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg));
+    assert(A32::IsDoubleExtReg(reg));
 
     if (args[1].IsInXmm(ctx.reg_alloc)) {
         const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[1]);
@@ -360,7 +360,7 @@ void A32EmitX64::EmitA32SetExtendedRegister64(A32EmitContext& ctx, IR::Inst* ins
 void A32EmitX64::EmitA32SetVector(A32EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    assert(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
 
     const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[1]);
     if (A32::IsDoubleExtReg(reg)) {
@@ -621,7 +621,7 @@ void A32EmitX64::EmitA32GetGEFlags(A32EmitContext& ctx, IR::Inst* inst) {
 
 void A32EmitX64::EmitA32SetGEFlags(A32EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(!args[0].IsImmediate());
+    assert(!args[0].IsImmediate());
 
     if (args[0].IsInXmm(ctx.reg_alloc)) {
         const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[0]);
@@ -762,7 +762,7 @@ void A32EmitX64::EmitA32ExceptionRaised(A32EmitContext& ctx, IR::Inst* inst) {
     ctx.reg_alloc.EndOfAllocScope();
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[0].IsImmediate() && args[1].IsImmediate());
+    assert(args[0].IsImmediate() && args[1].IsImmediate());
     const u32 pc = args[0].GetImmediateU32();
     const u64 exception = args[1].GetImmediateU64();
     Devirtualize<&A32::UserCallbacks::ExceptionRaised>(conf.callbacks).EmitCall(code, [&](RegList param) {
@@ -833,7 +833,7 @@ void A32EmitX64::EmitA32SetFpscrNZCV(A32EmitContext& ctx, IR::Inst* inst) {
 }
 
 static void EmitCoprocessorException() {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 static void CallCoprocCallback(BlockOfCode& code, RegAlloc& reg_alloc, A32::Coprocessor::Callback callback, IR::Inst* inst = nullptr, std::optional<Argument::copyable_reference> arg0 = {}, std::optional<Argument::copyable_reference> arg1 = {}) {
@@ -909,7 +909,7 @@ void A32EmitX64::EmitA32CoprocSendOneWord(A32EmitContext& ctx, IR::Inst* inst) {
         return;
     }
 
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void A32EmitX64::EmitA32CoprocSendTwoWords(A32EmitContext& ctx, IR::Inst* inst) {
@@ -952,7 +952,7 @@ void A32EmitX64::EmitA32CoprocSendTwoWords(A32EmitContext& ctx, IR::Inst* inst)
         return;
     }
 
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void A32EmitX64::EmitA32CoprocGetOneWord(A32EmitContext& ctx, IR::Inst* inst) {
@@ -995,7 +995,7 @@ void A32EmitX64::EmitA32CoprocGetOneWord(A32EmitContext& ctx, IR::Inst* inst) {
         return;
     }
 
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void A32EmitX64::EmitA32CoprocGetTwoWords(A32EmitContext& ctx, IR::Inst* inst) {
@@ -1040,7 +1040,7 @@ void A32EmitX64::EmitA32CoprocGetTwoWords(A32EmitContext& ctx, IR::Inst* inst) {
         return;
     }
 
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void A32EmitX64::EmitA32CoprocLoadWords(A32EmitContext& ctx, IR::Inst* inst) {
@@ -1216,7 +1216,7 @@ void EmitTerminalImpl(A32EmitX64& e, IR::Term::CheckHalt terminal, IR::LocationD
 }
 
 void EmitTerminalImpl(A32EmitX64&, IR::Term::Invalid, IR::LocationDescriptor, bool) {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/a32_interface.cpp b/src/dynarmic/src/dynarmic/backend/x64/a32_interface.cpp
index b48dcf9046..549eabac99 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/a32_interface.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/a32_interface.cpp
@@ -12,9 +12,9 @@
 
 #include <boost/icl/interval_set.hpp>
 #include <fmt/format.h>
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include <bit>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include "dynarmic/common/llvm_disassemble.h"
 
 #include "dynarmic/backend/x64/a32_emit_x64.h"
@@ -74,7 +74,7 @@ struct Jit::Impl {
     ~Impl() = default;
 
     HaltReason Run() {
-        ASSERT(!jit_interface->is_executing);
+        assert(!jit_interface->is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
         jit_interface->is_executing = true;
         const CodePtr current_codeptr = [this] {
@@ -94,7 +94,7 @@ struct Jit::Impl {
     }
 
     HaltReason Step() {
-        ASSERT(!jit_interface->is_executing);
+        assert(!jit_interface->is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
         jit_interface->is_executing = true;
         const HaltReason hr = block_of_code.StepCode(&jit_state, GetCurrentSingleStep());
@@ -116,7 +116,7 @@ struct Jit::Impl {
     }
 
     void Reset() {
-        ASSERT(!jit_interface->is_executing);
+        assert(!jit_interface->is_executing);
         jit_state = {};
     }
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp b/src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp
index 066b931350..028509e7c0 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp
@@ -8,9 +8,9 @@
 
 #include "dynarmic/backend/x64/a32_jitstate.h"
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/backend/x64/block_of_code.h"
 #include "dynarmic/backend/x64/nzcv_util.h"
@@ -51,8 +51,8 @@ namespace Dynarmic::Backend::X64 {
  */
 
 u32 A32JitState::Cpsr() const {
-    DEBUG_ASSERT((cpsr_q & ~1) == 0);
-    DEBUG_ASSERT((cpsr_jaifm & ~0x010001DF) == 0);
+    assert((cpsr_q & ~1) == 0);
+    assert((cpsr_jaifm & ~0x010001DF) == 0);
 
     u32 cpsr = 0;
 
@@ -167,7 +167,7 @@ constexpr u32 FPSCR_MODE_MASK = A32::LocationDescriptor::FPSCR_MODE_MASK;
 constexpr u32 FPSCR_NZCV_MASK = 0xF0000000;
 
 u32 A32JitState::Fpscr() const {
-    DEBUG_ASSERT((fpsr_nzcv & ~FPSCR_NZCV_MASK) == 0);
+    assert((fpsr_nzcv & ~FPSCR_NZCV_MASK) == 0);
 
     const u32 fpcr_mode = static_cast<u32>(upper_location_descriptor) & FPSCR_MODE_MASK;
     const u32 mxcsr = guest_MXCSR | asimd_MXCSR;
diff --git a/src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.h b/src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.h
index 99510c91cf..c276ab0b8b 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -9,8 +9,9 @@
 #pragma once
 
 #include <array>
+#include <cstddef>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Backend::X64 {
 
@@ -48,8 +49,8 @@ struct A32JitState {
     // Exclusive state
     u32 exclusive_state = 0;
 
-    static constexpr size_t RSBSize = 8;  // MUST be a power of 2.
-    static constexpr size_t RSBPtrMask = RSBSize - 1;
+    static constexpr std::size_t RSBSize = 8;  // MUST be a power of 2.
+    static constexpr std::size_t RSBPtrMask = RSBSize - 1;
     u32 rsb_ptr = 0;
     std::array<u64, RSBSize> rsb_location_descriptors;
     std::array<u64, RSBSize> rsb_codeptrs;
diff --git a/src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp b/src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp
index 832cfdcce2..4b16176b6b 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp
@@ -10,8 +10,8 @@
 
 #include <fmt/format.h>
 #include <fmt/ostream.h>
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 #include "dynarmic/mcl/integer_of_size.hpp"
 #include <boost/container/static_vector.hpp>
 
@@ -89,7 +89,7 @@ A64EmitX64::BlockDescriptor A64EmitX64::Emit(IR::Block& block) noexcept {
     code.align();
     const auto* const entrypoint = code.getCurr();
 
-    DEBUG_ASSERT(block.GetCondition() == IR::Cond::AL);
+    assert(block.GetCondition() == IR::Cond::AL);
     typedef void (EmitX64::*EmitHandlerFn)(EmitContext& context, IR::Inst* inst);
     constexpr EmitHandlerFn opcode_handlers[] = {
 #define OPCODE(name, type, ...) &EmitX64::Emit##name,
@@ -123,7 +123,7 @@ A64EmitX64::BlockDescriptor A64EmitX64::Emit(IR::Block& block) noexcept {
 #undef A32OPC
 #undef A64OPC
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
 opcode_branch:
         (this->*opcode_handlers[size_t(opcode)])(ctx, &inst);
@@ -497,7 +497,7 @@ void A64EmitX64::EmitA64SetPC(A64EmitContext& ctx, IR::Inst* inst) {
 void A64EmitX64::EmitA64CallSupervisor(A64EmitContext& ctx, IR::Inst* inst) {
     ctx.reg_alloc.HostCall(code, nullptr);
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[0].IsImmediate());
+    assert(args[0].IsImmediate());
     const u32 imm = args[0].GetImmediateU32();
     Devirtualize<&A64::UserCallbacks::CallSVC>(conf.callbacks).EmitCall(code, [&](RegList param) {
         code.mov(param[0], imm);
@@ -509,7 +509,7 @@ void A64EmitX64::EmitA64CallSupervisor(A64EmitContext& ctx, IR::Inst* inst) {
 void A64EmitX64::EmitA64ExceptionRaised(A64EmitContext& ctx, IR::Inst* inst) {
     ctx.reg_alloc.HostCall(code, nullptr);
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[0].IsImmediate() && args[1].IsImmediate());
+    assert(args[0].IsImmediate() && args[1].IsImmediate());
     const u64 pc = args[0].GetImmediateU64();
     const u64 exception = args[1].GetImmediateU64();
     Devirtualize<&A64::UserCallbacks::ExceptionRaised>(conf.callbacks).EmitCall(code, [&](RegList param) {
@@ -710,7 +710,7 @@ void EmitTerminalImpl(A64EmitX64& e, IR::Term::CheckHalt terminal, IR::LocationD
 }
 
 void EmitTerminalImpl(A64EmitX64&, IR::Term::Invalid, IR::LocationDescriptor, bool) {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/a64_interface.cpp b/src/dynarmic/src/dynarmic/backend/x64/a64_interface.cpp
index 96440d273e..df997b74fc 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/a64_interface.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/a64_interface.cpp
@@ -11,7 +11,7 @@
 #include <mutex>
 
 #include <boost/icl/interval_set.hpp>
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/common/fp/fpcr.h"
 #include "dynarmic/common/llvm_disassemble.h"
 #include <bit>
@@ -66,13 +66,13 @@ public:
         , emitter(block_of_code, conf, jit)
         , polyfill_options(GenPolyfillOptions(block_of_code))
     {
-        ASSERT(conf.page_table_address_space_bits >= 12 && conf.page_table_address_space_bits <= 64);
+        assert(conf.page_table_address_space_bits >= 12 && conf.page_table_address_space_bits <= 64);
     }
 
     ~Impl() = default;
 
     HaltReason Run() {
-        ASSERT(!is_executing);
+        assert(!is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
         is_executing = true;
         // TODO: Check code alignment
@@ -92,7 +92,7 @@ public:
     }
 
     HaltReason Step() {
-        ASSERT(!is_executing);
+        assert(!is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
         is_executing = true;
         const HaltReason hr = block_of_code.StepCode(&jit_state, GetCurrentSingleStep());
@@ -116,7 +116,7 @@ public:
     }
 
     void Reset() {
-        ASSERT(!is_executing);
+        assert(!is_executing);
         jit_state = {};
     }
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/a64_jitstate.h b/src/dynarmic/src/dynarmic/backend/x64/a64_jitstate.h
index 22fd94e5c9..85ee1aa4b9 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/a64_jitstate.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/a64_jitstate.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <array>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/backend/x64/nzcv_util.h"
 #include "dynarmic/frontend/A64/a64_location_descriptor.h"
diff --git a/src/dynarmic/src/dynarmic/backend/x64/abi.cpp b/src/dynarmic/src/dynarmic/backend/x64/abi.cpp
index 413af7b557..5d2ee735f3 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/abi.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/abi.cpp
@@ -10,7 +10,7 @@
 
 #include <algorithm>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include "dynarmic/backend/x64/xbyak.h"
 
 #include "dynarmic/backend/x64/block_of_code.h"
diff --git a/src/dynarmic/src/dynarmic/backend/x64/abi.h b/src/dynarmic/src/dynarmic/backend/x64/abi.h
index c37910ce22..f98fa302ca 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/abi.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/abi.h
@@ -10,7 +10,7 @@
 #include <array>
 #include <bitset>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include "dynarmic/backend/x64/hostloc.h"
 
 namespace Dynarmic::Backend::X64 {
diff --git a/src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp b/src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp
index 3a161fca6b..efaf463983 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp
@@ -24,7 +24,7 @@
 #include <array>
 #include <cstring>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
 #include "dynarmic/backend/x64/xbyak.h"
 
@@ -278,12 +278,12 @@ void BlockOfCode::DisableWriting() {
 }
 
 void BlockOfCode::ClearCache() {
-    ASSERT(prelude_complete);
+    assert(prelude_complete);
     SetCodePtr(code_begin);
 }
 
 size_t BlockOfCode::SpaceRemaining() const {
-    ASSERT(prelude_complete);
+    assert(prelude_complete);
     const u8* current_ptr = getCurr<const u8*>();
     if (current_ptr >= &top_[maxSize_])
         return 0;
@@ -515,7 +515,7 @@ void BlockOfCode::LoadRequiredFlagsForCondFromRax(IR::Cond cond) {
     case IR::Cond::NV:
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -553,7 +553,7 @@ void BlockOfCode::SetCodePtr(CodePtr code_ptr) {
 
 void BlockOfCode::EnsurePatchLocationSize(CodePtr begin, size_t size) {
     size_t current_size = getCurr<const u8*>() - reinterpret_cast<const u8*>(begin);
-    ASSERT(current_size <= size);
+    assert(current_size <= size);
     nop(size - current_size);
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/block_of_code.h b/src/dynarmic/src/dynarmic/backend/x64/block_of_code.h
index f6c12edaaa..ab05a0fa40 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/block_of_code.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/block_of_code.h
@@ -14,7 +14,7 @@
 #include <type_traits>
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include "dynarmic/backend/x64/xbyak.h"
 #include "dynarmic/backend/x64/abi.h"
 #include "dynarmic/backend/x64/callback.h"
@@ -120,7 +120,7 @@ public:
         case 64:
             return;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/callback.h b/src/dynarmic/src/dynarmic/backend/x64/callback.h
index 2bd917ad76..fb1a1a5855 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/callback.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/callback.h
@@ -11,7 +11,7 @@
 #include <functional>
 #include <vector>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include "dynarmic/backend/x64/xbyak.h"
 
 namespace Dynarmic::Backend::X64 {
diff --git a/src/dynarmic/src/dynarmic/backend/x64/constant_pool.cpp b/src/dynarmic/src/dynarmic/backend/x64/constant_pool.cpp
index 7dbd46bc2a..c20d61a2eb 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/constant_pool.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/constant_pool.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <cstring>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 #include "dynarmic/backend/x64/block_of_code.h"
 
@@ -29,7 +29,7 @@ Xbyak::Address ConstantPool::GetConstant(const Xbyak::AddressFrame& frame, u64 l
     const auto constant = ConstantT(lower, upper);
     auto iter = constant_info.find(constant);
     if (iter == constant_info.end()) {
-        ASSERT(insertion_point < pool.size());
+        assert(insertion_point < pool.size());
         ConstantT& target_constant = pool[insertion_point];
         target_constant = constant;
         iter = constant_info.insert({constant, &target_constant}).first;
diff --git a/src/dynarmic/src/dynarmic/backend/x64/constant_pool.h b/src/dynarmic/src/dynarmic/backend/x64/constant_pool.h
index efb19f48ed..79e57fc78c 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/constant_pool.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/constant_pool.h
@@ -13,7 +13,7 @@
 #include <span>
 #include <utility>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include <ankerl/unordered_dense.h>
 #include "dynarmic/backend/x64/xbyak.h"
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/constants.h b/src/dynarmic/src/dynarmic/backend/x64/constants.h
index a0ae9f3c1e..fb9789e053 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/constants.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/constants.h
@@ -11,7 +11,7 @@
 #include <optional>
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/fp/rounding_mode.h"
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/devirtualize.h b/src/dynarmic/src/dynarmic/backend/x64/devirtualize.h
index 422d21169f..e6efe010ff 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/devirtualize.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/devirtualize.h
@@ -12,7 +12,7 @@
 #include <utility>
 
 #include <bit>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include "dynarmic/mcl/function_info.hpp"
 
 #include "dynarmic/backend/x64/callback.h"
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp
index 4e515fef2f..b9fe0f27cc 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp
@@ -10,10 +10,10 @@
 
 #include <iterator>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include <boost/variant/detail/apply_visitor_binary.hpp>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include <ankerl/unordered_dense.h>
 
 #include "dynarmic/backend/x64/block_of_code.h"
@@ -53,7 +53,7 @@ std::optional<EmitX64::BlockDescriptor> EmitX64::GetBasicBlock(IR::LocationDescr
 }
 
 void EmitX64::EmitInvalid(EmitContext&, IR::Inst* inst) {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void EmitX64::EmitVoid(EmitContext&, IR::Inst*) {
@@ -103,7 +103,7 @@ void EmitX64::PushRSBHelper(Xbyak::Reg64 loc_desc_reg, Xbyak::Reg64 index_reg, I
     code.mov(qword[code.ABI_JIT_PTR + index_reg * 8 + code.GetJitStateInfo().offsetof_rsb_location_descriptors], loc_desc_reg);
     code.mov(qword[code.ABI_JIT_PTR + index_reg * 8 + code.GetJitStateInfo().offsetof_rsb_codeptrs], rcx);
     // Byte size hack
-    DEBUG_ASSERT(code.GetJitStateInfo().rsb_ptr_mask <= 0xFF);
+    assert(code.GetJitStateInfo().rsb_ptr_mask <= 0xFF);
     code.add(index_reg.cvt32(), 1); //flags trashed, 1 single byte, haswell doesn't care
     code.and_(index_reg.cvt32(), u32(code.GetJitStateInfo().rsb_ptr_mask)); //trashes flags
     // Results ready and sort by least needed: give OOO some break
@@ -144,7 +144,7 @@ void EmitX64::EmitVerboseDebuggingOutput(RegAlloc& reg_alloc) {
 
 void EmitX64::EmitPushRSB(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[0].IsImmediate());
+    assert(args[0].IsImmediate());
     const u64 unique_hash_of_target = args[0].GetImmediateU64();
 
     ctx.reg_alloc.ScratchGpr(code, HostLoc::RCX);
@@ -193,7 +193,7 @@ void EmitX64::EmitGetNZFromOp(EmitContext& ctx, IR::Inst* inst) {
         case IR::Type::U64:
             return 64;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }();
 
@@ -224,7 +224,7 @@ void EmitX64::EmitGetNZCVFromOp(EmitContext& ctx, IR::Inst* inst) {
         case IR::Type::U64:
             return 64;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }();
 
@@ -284,7 +284,7 @@ void EmitX64::EmitNZCVFromPackedFlags(EmitContext& ctx, IR::Inst* inst) {
 }
 
 void EmitX64::EmitAddCycles(size_t cycles) {
-    ASSERT(cycles < (std::numeric_limits<s32>::max)());
+    assert(cycles < (std::numeric_limits<s32>::max)());
     code.sub(qword[rsp + ABI_SHADOW_SPACE + offsetof(StackLayout, cycles_remaining)], static_cast<u32>(cycles));
 }
 
@@ -339,7 +339,7 @@ Xbyak::Label EmitX64::EmitCond(IR::Cond cond) {
         code.jle(pass);
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
     return pass;
 }
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_aes.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_aes.cpp
index 1ab5a12de1..ae05f9f590 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_aes.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_aes.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -6,7 +6,7 @@
  * SPDX-License-Identifier: 0BSD
  */
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/backend/x64/abi.h"
 #include "dynarmic/backend/x64/block_of_code.h"
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp
index f2af4e5b80..f0d2bef7af 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp
@@ -9,8 +9,8 @@
 #include <cstddef>
 #include <type_traits>
 
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 
 #include "dynarmic/backend/x64/block_of_code.h"
 #include "dynarmic/backend/x64/emit_x64.h"
@@ -129,7 +129,7 @@ void EmitX64::EmitIsZero64(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitTestBit(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const Xbyak::Reg64 result = ctx.reg_alloc.UseScratchGpr(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     // TODO: Flag optimization
     code.bt(result, args[1].GetImmediateU8());
     code.setc(result.cvt8());
@@ -194,7 +194,7 @@ static void EmitConditionalSelect(BlockOfCode& code, EmitContext& ctx, IR::Inst*
         code.mov(else_, then_);
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     ctx.reg_alloc.DefineValue(code, inst, else_);
@@ -663,7 +663,7 @@ void EmitX64::EmitArithmeticShiftRight64(EmitContext& ctx, IR::Inst* inst) {
     }
 }
 
-void EmitX64::EmitRotateRight32(EmitContext& ctx, IR::Inst* inst) {
+void EmitX64::EmitBitRotateRight32(EmitContext& ctx, IR::Inst* inst) {
     const auto carry_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetCarryFromOp);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@@ -736,7 +736,7 @@ void EmitX64::EmitRotateRight32(EmitContext& ctx, IR::Inst* inst) {
     }
 }
 
-void EmitX64::EmitRotateRight64(EmitContext& ctx, IR::Inst* inst) {
+void EmitX64::EmitBitRotateRight64(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto& operand_arg = args[0];
     auto& shift_arg = args[1];
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp
index d073991fbe..bac10be02e 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp
@@ -10,8 +10,8 @@
 #include <type_traits>
 #include <utility>
 
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 #include "dynarmic/mcl/integer_of_size.hpp"
 #include "dynarmic/backend/x64/xbyak.h"
 
@@ -659,7 +659,7 @@ static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, bo
                 FCODE(ucomis)(result, result);
                 code.jp(*fallback, code.T_NEAR);
             } else {
-                UNREACHABLE();
+                std::terminate(); //unreachable
             }
             if (ctx.FPCR().DN()) {
                 ForceToDefaultNaN<fsize>(code, result);
@@ -1079,7 +1079,7 @@ static void EmitFPRound(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, siz
         case 64: code.CallFunction(EmitFPRoundThunk<u64>); break;
         case 32: code.CallFunction(EmitFPRoundThunk<u32>); break;
         case 16: code.CallFunction(EmitFPRoundThunk<u16>); break;
-        default: UNREACHABLE();
+        default: std::terminate(); //unreachable
         }
     }
 }
@@ -1842,7 +1842,7 @@ void EmitX64::EmitFPFixedS32ToSingle(EmitContext& ctx, IR::Inst* inst) {
     if (rounding_mode == ctx.FPCR().RMode() || ctx.HasOptimization(OptimizationFlag::Unsafe_IgnoreStandardFPCRValue)) {
         code.cvtsi2ss(result, from);
     } else {
-        ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
+        assert(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
         code.EnterStandardASIMD();
         code.cvtsi2ss(result, from);
         code.LeaveStandardASIMD();
@@ -1878,7 +1878,7 @@ void EmitX64::EmitFPFixedU32ToSingle(EmitContext& ctx, IR::Inst* inst) {
     if (rounding_mode == ctx.FPCR().RMode() || ctx.HasOptimization(OptimizationFlag::Unsafe_IgnoreStandardFPCRValue)) {
         op();
     } else {
-        ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
+        assert(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
         code.EnterStandardASIMD();
         op();
         code.LeaveStandardASIMD();
@@ -1984,7 +1984,7 @@ void EmitX64::EmitFPFixedS64ToDouble(EmitContext& ctx, IR::Inst* inst) {
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     const size_t fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
-    ASSERT(rounding_mode == ctx.FPCR().RMode());
+    assert(rounding_mode == ctx.FPCR().RMode());
 
     code.cvtsi2sd(result, from);
 
@@ -2003,7 +2003,7 @@ void EmitX64::EmitFPFixedS64ToSingle(EmitContext& ctx, IR::Inst* inst) {
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     const size_t fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
-    ASSERT(rounding_mode == ctx.FPCR().RMode());
+    assert(rounding_mode == ctx.FPCR().RMode());
 
     code.cvtsi2ss(result, from);
 
@@ -2022,7 +2022,7 @@ void EmitX64::EmitFPFixedU64ToDouble(EmitContext& ctx, IR::Inst* inst) {
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     const size_t fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
-    ASSERT(rounding_mode == ctx.FPCR().RMode());
+    assert(rounding_mode == ctx.FPCR().RMode());
 
     if (code.HasHostFeature(HostFeature::AVX512F)) {
         code.vcvtusi2sd(result, result, from);
@@ -2053,7 +2053,7 @@ void EmitX64::EmitFPFixedU64ToSingle(EmitContext& ctx, IR::Inst* inst) {
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     const size_t fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
-    ASSERT(rounding_mode == ctx.FPCR().RMode());
+    assert(rounding_mode == ctx.FPCR().RMode());
 
     if (code.HasHostFeature(HostFeature::AVX512F)) {
         const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(code, args[0]);
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc
index 54fc595214..45d767f67f 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc
@@ -43,7 +43,7 @@ FakeCall AxxEmitX64::FastmemCallback(u64 rip_) {
     }
     fmt::print("dynarmic: Segfault happened within JITted code at rip = {:016x}\n"
         "Segfault wasn't at a fastmem patch location!\n", rip_);
-    UNREACHABLE(); //("iter != fastmem_patch_info.end()");
+    std::terminate(); //unreachable //("iter != fastmem_patch_info.end()");
 }
 
 template<std::size_t bitsize, auto callback>
@@ -113,7 +113,7 @@ void AxxEmitX64::EmitMemoryRead(AxxEmitContext& ctx, IR::Inst* inst) {
         });
     } else {
         // Use page table
-        ASSERT(conf.page_table);
+        assert(conf.page_table);
         const auto src_ptr = EmitVAddrLookup(code, ctx, bitsize, *abort, vaddr);
         EmitReadMemoryMov<bitsize>(code, value_idx, src_ptr, ordered);
 
@@ -200,7 +200,7 @@ void AxxEmitX64::EmitMemoryWrite(AxxEmitContext& ctx, IR::Inst* inst) {
         });
     } else {
         // Use page table
-        ASSERT(conf.page_table);
+        assert(conf.page_table);
         const auto dest_ptr = EmitVAddrLookup(code, ctx, bitsize, *abort, vaddr);
         EmitWriteMemoryMov<bitsize>(code, dest_ptr, value_idx, ordered);
 
@@ -216,7 +216,7 @@ void AxxEmitX64::EmitMemoryWrite(AxxEmitContext& ctx, IR::Inst* inst) {
 
 template<std::size_t bitsize, auto callback>
 void AxxEmitX64::EmitExclusiveReadMemory(AxxEmitContext& ctx, IR::Inst* inst) {
-    ASSERT(conf.global_monitor != nullptr);
+    assert(conf.global_monitor != nullptr);
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const bool ordered = IsOrdered(args[2].GetImmediateAccType());
 
@@ -267,7 +267,7 @@ void AxxEmitX64::EmitExclusiveReadMemory(AxxEmitContext& ctx, IR::Inst* inst) {
 
 template<std::size_t bitsize, auto callback>
 void AxxEmitX64::EmitExclusiveWriteMemory(AxxEmitContext& ctx, IR::Inst* inst) {
-    ASSERT(conf.global_monitor != nullptr);
+    assert(conf.global_monitor != nullptr);
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const bool ordered = IsOrdered(args[3].GetImmediateAccType());
 
@@ -320,7 +320,7 @@ void AxxEmitX64::EmitExclusiveWriteMemory(AxxEmitContext& ctx, IR::Inst* inst) {
 
 template<std::size_t bitsize, auto callback>
 void AxxEmitX64::EmitExclusiveReadMemoryInline(AxxEmitContext& ctx, IR::Inst* inst) {
-    ASSERT(conf.global_monitor && conf.fastmem_pointer);
+    assert(conf.global_monitor && conf.fastmem_pointer);
     if (!exception_handler.SupportsFastmem()) {
         EmitExclusiveReadMemory<bitsize, callback>(ctx, inst);
         return;
@@ -397,7 +397,7 @@ void AxxEmitX64::EmitExclusiveReadMemoryInline(AxxEmitContext& ctx, IR::Inst* in
 
 template<std::size_t bitsize, auto callback>
 void AxxEmitX64::EmitExclusiveWriteMemoryInline(AxxEmitContext& ctx, IR::Inst* inst) {
-    ASSERT(conf.global_monitor && conf.fastmem_pointer);
+    assert(conf.global_monitor && conf.fastmem_pointer);
     if (!exception_handler.SupportsFastmem()) {
         EmitExclusiveWriteMemory<bitsize, callback>(ctx, inst);
         return;
@@ -489,7 +489,7 @@ void AxxEmitX64::EmitExclusiveWriteMemoryInline(AxxEmitContext& ctx, IR::Inst* i
             code.cmpxchg16b(ptr[dest_ptr]);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
 
         code.setnz(status.cvt8());
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h
index 211f620ceb..83211c6c7c 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h
@@ -6,6 +6,8 @@
  * SPDX-License-Identifier: 0BSD
  */
 
+#pragma once
+
 #include <bit>
 #include "dynarmic/backend/x64/xbyak.h"
 
@@ -22,9 +24,9 @@ namespace {
 
 using namespace Xbyak::util;
 
-constexpr size_t page_bits = 12;
-constexpr size_t page_size = 1 << page_bits;
-constexpr size_t page_mask = (1 << page_bits) - 1;
+constexpr size_t page_table_const_bits = 12;
+constexpr size_t page_table_const_size = 1 << page_table_const_bits;
+constexpr size_t page_table_const_mask = (1 << page_table_const_bits) - 1;
 
 template<typename EmitContext>
 void EmitDetectMisalignedVAddr(BlockOfCode& code, EmitContext& ctx, size_t bitsize, Xbyak::Label& abort, Xbyak::Reg64 vaddr, Xbyak::Reg64 tmp) {
@@ -43,14 +45,14 @@ void EmitDetectMisalignedVAddr(BlockOfCode& code, EmitContext& ctx, size_t bitsi
         case 128:
             return 0b1111;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }();
 
     code.test(vaddr, align_mask);
 
     if (ctx.conf.only_detect_misalignment_via_page_table_on_page_boundary) {
-        const u32 page_align_mask = static_cast<u32>(page_size - 1) & ~align_mask;
+        const u32 page_align_mask = static_cast<u32>(page_table_const_size - 1) & ~align_mask;
 
         SharedLabel detect_boundary = GenSharedLabel(), resume = GenSharedLabel();
 
@@ -83,7 +85,7 @@ template<>
     // TODO: This code assumes vaddr has been zext from 32-bits to 64-bits.
 
     code.mov(tmp, vaddr.cvt32());
-    code.shr(tmp, int(page_bits));
+    code.shr(tmp, int(page_table_const_bits));
     code.shl(tmp, int(ctx.conf.page_table_log2_stride));
     code.mov(page, qword[r14 + tmp.cvt64()]);
     if (ctx.conf.page_table_pointer_mask_bits == 0) {
@@ -96,13 +98,13 @@ template<>
         return page + vaddr;
     }
     code.mov(tmp, vaddr.cvt32());
-    code.and_(tmp, static_cast<u32>(page_mask));
+    code.and_(tmp, static_cast<u32>(page_table_const_mask));
     return page + tmp.cvt64();
 }
 
 template<>
 [[maybe_unused]] Xbyak::RegExp EmitVAddrLookup<A64EmitContext>(BlockOfCode& code, A64EmitContext& ctx, size_t bitsize, Xbyak::Label& abort, Xbyak::Reg64 vaddr) {
-    const size_t valid_page_index_bits = ctx.conf.page_table_address_space_bits - page_bits;
+    const size_t valid_page_index_bits = ctx.conf.page_table_address_space_bits - page_table_const_bits;
     const size_t unused_top_bits = 64 - ctx.conf.page_table_address_space_bits;
 
     const Xbyak::Reg64 page = ctx.reg_alloc.ScratchGpr(code);
@@ -112,29 +114,29 @@ template<>
 
     if (unused_top_bits == 0) {
         code.mov(tmp, vaddr);
-        code.shr(tmp, int(page_bits));
+        code.shr(tmp, int(page_table_const_bits));
     } else if (ctx.conf.silently_mirror_page_table) {
         if (valid_page_index_bits >= 32) {
             if (code.HasHostFeature(HostFeature::BMI2)) {
                 const Xbyak::Reg64 bit_count = ctx.reg_alloc.ScratchGpr(code);
                 code.mov(bit_count, unused_top_bits);
                 code.bzhi(tmp, vaddr, bit_count);
-                code.shr(tmp, int(page_bits));
+                code.shr(tmp, int(page_table_const_bits));
                 ctx.reg_alloc.Release(bit_count);
             } else {
                 code.mov(tmp, vaddr);
                 code.shl(tmp, int(unused_top_bits));
-                code.shr(tmp, int(unused_top_bits + page_bits));
+                code.shr(tmp, int(unused_top_bits + page_table_const_bits));
             }
         } else {
             code.mov(tmp, vaddr);
-            code.shr(tmp, int(page_bits));
+            code.shr(tmp, int(page_table_const_bits));
             code.and_(tmp, u32((1 << valid_page_index_bits) - 1));
         }
     } else {
-        ASSERT(valid_page_index_bits < 32);
+        assert(valid_page_index_bits < 32);
         code.mov(tmp, vaddr);
-        code.shr(tmp, int(page_bits));
+        code.shr(tmp, int(page_table_const_bits));
         code.test(tmp, u32(-(1 << valid_page_index_bits)));
         code.jnz(abort, code.T_NEAR);
     }
@@ -151,7 +153,7 @@ template<>
         return page + vaddr;
     }
     code.mov(tmp, vaddr);
-    code.and_(tmp, static_cast<u32>(page_mask));
+    code.and_(tmp, static_cast<u32>(page_table_const_mask));
     return page + tmp;
 }
 
@@ -245,7 +247,7 @@ const void* EmitReadMemoryMov(BlockOfCode& code, int value_idx, const Xbyak::Reg
             }
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
         return fastmem_location;
     } else {
@@ -267,7 +269,7 @@ const void* EmitReadMemoryMov(BlockOfCode& code, int value_idx, const Xbyak::Reg
             code.movups(Xbyak::Xmm(value_idx), xword[addr]);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
         return fastmem_location;
     }
@@ -313,7 +315,7 @@ const void* EmitWriteMemoryMov(BlockOfCode& code, const Xbyak::RegExp& addr, int
             break;
         }
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
         return fastmem_location;
     } else {
@@ -335,7 +337,7 @@ const void* EmitWriteMemoryMov(BlockOfCode& code, const Xbyak::RegExp& addr, int
             code.movups(xword[addr], Xbyak::Xmm(value_idx));
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
         return fastmem_location;
     }
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_saturation.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_saturation.cpp
index 63827979df..48da79f6dd 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_saturation.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_saturation.cpp
@@ -8,9 +8,9 @@
 
 #include <limits>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include "dynarmic/mcl/integer_of_size.hpp"
 
 #include "dynarmic/backend/x64/block_of_code.h"
@@ -25,12 +25,12 @@ using namespace Xbyak::util;
 
 namespace {
 
-enum class Op {
+enum class SaturationOp {
     Add,
     Sub,
 };
 
-template<Op op, size_t size, bool has_overflow_inst = false>
+template<SaturationOp op, size_t size, bool has_overflow_inst = false>
 void EmitSignedSaturatedOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
 
@@ -51,7 +51,7 @@ void EmitSignedSaturatedOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst)
 
     // overflow now contains 0x7F... if a was positive, or 0x80... if a was negative
 
-    if constexpr (op == Op::Add) {
+    if constexpr (op == SaturationOp::Add) {
         code.add(result, addend);
     } else {
         code.sub(result, addend);
@@ -75,16 +75,16 @@ void EmitSignedSaturatedOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst)
     ctx.reg_alloc.DefineValue(code, inst, result);
 }
 
-template<Op op, size_t size>
+template<SaturationOp op, size_t size>
 void EmitUnsignedSaturatedOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
 
     Xbyak::Reg op_result = ctx.reg_alloc.UseScratchGpr(code, args[0]).changeBit(size);
     Xbyak::Reg addend = ctx.reg_alloc.UseScratchGpr(code, args[1]).changeBit(size);
 
-    constexpr u64 boundary = op == Op::Add ? (std::numeric_limits<mcl::unsigned_integer_of_size<size>>::max)() : 0;
+    constexpr u64 boundary = op == SaturationOp::Add ? (std::numeric_limits<mcl::unsigned_integer_of_size<size>>::max)() : 0;
 
-    if constexpr (op == Op::Add) {
+    if constexpr (op == SaturationOp::Add) {
         code.add(op_result, addend);
     } else {
         code.sub(op_result, addend);
@@ -106,11 +106,11 @@ void EmitUnsignedSaturatedOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst
 }  // anonymous namespace
 
 void EmitX64::EmitSignedSaturatedAddWithFlag32(EmitContext& ctx, IR::Inst* inst) {
-    EmitSignedSaturatedOp<Op::Add, 32, true>(code, ctx, inst);
+    EmitSignedSaturatedOp<SaturationOp::Add, 32, true>(code, ctx, inst);
 }
 
 void EmitX64::EmitSignedSaturatedSubWithFlag32(EmitContext& ctx, IR::Inst* inst) {
-    EmitSignedSaturatedOp<Op::Sub, 32, true>(code, ctx, inst);
+    EmitSignedSaturatedOp<SaturationOp::Sub, 32, true>(code, ctx, inst);
 }
 
 void EmitX64::EmitSignedSaturation(EmitContext& ctx, IR::Inst* inst) {
@@ -118,7 +118,7 @@ void EmitX64::EmitSignedSaturation(EmitContext& ctx, IR::Inst* inst) {
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const size_t N = args[1].GetImmediateU8();
-    ASSERT(N >= 1 && N <= 32);
+    assert(N >= 1 && N <= 32);
 
     if (N == 32) {
         if (overflow_inst) {
@@ -167,7 +167,7 @@ void EmitX64::EmitUnsignedSaturation(EmitContext& ctx, IR::Inst* inst) {
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const size_t N = args[1].GetImmediateU8();
-    ASSERT(N <= 31);
+    assert(N <= 31);
 
     const u32 saturated_value = (1u << N) - 1;
 
@@ -192,19 +192,19 @@ void EmitX64::EmitUnsignedSaturation(EmitContext& ctx, IR::Inst* inst) {
 }
 
 void EmitX64::EmitSignedSaturatedAdd8(EmitContext& ctx, IR::Inst* inst) {
-    EmitSignedSaturatedOp<Op::Add, 8>(code, ctx, inst);
+    EmitSignedSaturatedOp<SaturationOp::Add, 8>(code, ctx, inst);
 }
 
 void EmitX64::EmitSignedSaturatedAdd16(EmitContext& ctx, IR::Inst* inst) {
-    EmitSignedSaturatedOp<Op::Add, 16>(code, ctx, inst);
+    EmitSignedSaturatedOp<SaturationOp::Add, 16>(code, ctx, inst);
 }
 
 void EmitX64::EmitSignedSaturatedAdd32(EmitContext& ctx, IR::Inst* inst) {
-    EmitSignedSaturatedOp<Op::Add, 32>(code, ctx, inst);
+    EmitSignedSaturatedOp<SaturationOp::Add, 32>(code, ctx, inst);
 }
 
 void EmitX64::EmitSignedSaturatedAdd64(EmitContext& ctx, IR::Inst* inst) {
-    EmitSignedSaturatedOp<Op::Add, 64>(code, ctx, inst);
+    EmitSignedSaturatedOp<SaturationOp::Add, 64>(code, ctx, inst);
 }
 
 void EmitX64::EmitSignedSaturatedDoublingMultiplyReturnHigh16(EmitContext& ctx, IR::Inst* inst) {
@@ -256,51 +256,51 @@ void EmitX64::EmitSignedSaturatedDoublingMultiplyReturnHigh32(EmitContext& ctx,
 }
 
 void EmitX64::EmitSignedSaturatedSub8(EmitContext& ctx, IR::Inst* inst) {
-    EmitSignedSaturatedOp<Op::Sub, 8>(code, ctx, inst);
+    EmitSignedSaturatedOp<SaturationOp::Sub, 8>(code, ctx, inst);
 }
 
 void EmitX64::EmitSignedSaturatedSub16(EmitContext& ctx, IR::Inst* inst) {
-    EmitSignedSaturatedOp<Op::Sub, 16>(code, ctx, inst);
+    EmitSignedSaturatedOp<SaturationOp::Sub, 16>(code, ctx, inst);
 }
 
 void EmitX64::EmitSignedSaturatedSub32(EmitContext& ctx, IR::Inst* inst) {
-    EmitSignedSaturatedOp<Op::Sub, 32>(code, ctx, inst);
+    EmitSignedSaturatedOp<SaturationOp::Sub, 32>(code, ctx, inst);
 }
 
 void EmitX64::EmitSignedSaturatedSub64(EmitContext& ctx, IR::Inst* inst) {
-    EmitSignedSaturatedOp<Op::Sub, 64>(code, ctx, inst);
+    EmitSignedSaturatedOp<SaturationOp::Sub, 64>(code, ctx, inst);
 }
 
 void EmitX64::EmitUnsignedSaturatedAdd8(EmitContext& ctx, IR::Inst* inst) {
-    EmitUnsignedSaturatedOp<Op::Add, 8>(code, ctx, inst);
+    EmitUnsignedSaturatedOp<SaturationOp::Add, 8>(code, ctx, inst);
 }
 
 void EmitX64::EmitUnsignedSaturatedAdd16(EmitContext& ctx, IR::Inst* inst) {
-    EmitUnsignedSaturatedOp<Op::Add, 16>(code, ctx, inst);
+    EmitUnsignedSaturatedOp<SaturationOp::Add, 16>(code, ctx, inst);
 }
 
 void EmitX64::EmitUnsignedSaturatedAdd32(EmitContext& ctx, IR::Inst* inst) {
-    EmitUnsignedSaturatedOp<Op::Add, 32>(code, ctx, inst);
+    EmitUnsignedSaturatedOp<SaturationOp::Add, 32>(code, ctx, inst);
 }
 
 void EmitX64::EmitUnsignedSaturatedAdd64(EmitContext& ctx, IR::Inst* inst) {
-    EmitUnsignedSaturatedOp<Op::Add, 64>(code, ctx, inst);
+    EmitUnsignedSaturatedOp<SaturationOp::Add, 64>(code, ctx, inst);
 }
 
 void EmitX64::EmitUnsignedSaturatedSub8(EmitContext& ctx, IR::Inst* inst) {
-    EmitUnsignedSaturatedOp<Op::Sub, 8>(code, ctx, inst);
+    EmitUnsignedSaturatedOp<SaturationOp::Sub, 8>(code, ctx, inst);
 }
 
 void EmitX64::EmitUnsignedSaturatedSub16(EmitContext& ctx, IR::Inst* inst) {
-    EmitUnsignedSaturatedOp<Op::Sub, 16>(code, ctx, inst);
+    EmitUnsignedSaturatedOp<SaturationOp::Sub, 16>(code, ctx, inst);
 }
 
 void EmitX64::EmitUnsignedSaturatedSub32(EmitContext& ctx, IR::Inst* inst) {
-    EmitUnsignedSaturatedOp<Op::Sub, 32>(code, ctx, inst);
+    EmitUnsignedSaturatedOp<SaturationOp::Sub, 32>(code, ctx, inst);
 }
 
 void EmitX64::EmitUnsignedSaturatedSub64(EmitContext& ctx, IR::Inst* inst) {
-    EmitUnsignedSaturatedOp<Op::Sub, 64>(code, ctx, inst);
+    EmitUnsignedSaturatedOp<SaturationOp::Sub, 64>(code, ctx, inst);
 }
 
 }  // namespace Dynarmic::Backend::X64
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_sha.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_sha.cpp
index cd166f0cb8..8be898b84f 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_sha.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_sha.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -18,7 +18,7 @@ void EmitX64::EmitSHA256Hash(EmitContext& ctx, IR::Inst* inst) {
 
     const bool part1 = args[3].GetImmediateU1();
 
-    ASSERT(code.HasHostFeature(HostFeature::SHA));
+    assert(code.HasHostFeature(HostFeature::SHA));
 
     //      3   2   1   0
     // x =  d   c   b   a
@@ -54,7 +54,7 @@ void EmitX64::EmitSHA256Hash(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitSHA256MessageSchedule0(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
 
-    ASSERT(code.HasHostFeature(HostFeature::SHA));
+    assert(code.HasHostFeature(HostFeature::SHA));
 
     const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(code, args[0]);
     const Xbyak::Xmm y = ctx.reg_alloc.UseXmm(code, args[1]);
@@ -67,7 +67,7 @@ void EmitX64::EmitSHA256MessageSchedule0(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitSHA256MessageSchedule1(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
 
-    ASSERT(code.HasHostFeature(HostFeature::SHA));
+    assert(code.HasHostFeature(HostFeature::SHA));
 
     const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(code, args[0]);
     const Xbyak::Xmm y = ctx.reg_alloc.UseXmm(code, args[1]);
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp
index d94f0329f8..8a062fffde 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp
@@ -12,9 +12,9 @@
 #include <cstdlib>
 #include <type_traits>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include "dynarmic/mcl/function_info.hpp"
 #include "dynarmic/backend/x64/xbyak.h"
 
@@ -189,7 +189,7 @@ static void EmitTwoArgumentFallback(BlockOfCode& code, EmitContext& ctx, IR::Ins
 
 void EmitX64::EmitVectorGetElement8(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     // TODO: DefineValue directly on Argument for index == 0
@@ -213,7 +213,7 @@ void EmitX64::EmitVectorGetElement8(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorGetElement16(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     // TODO: DefineValue directly on Argument for index == 0
@@ -226,7 +226,7 @@ void EmitX64::EmitVectorGetElement16(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorGetElement32(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     // TODO: DefineValue directly on Argument for index == 0
@@ -247,7 +247,7 @@ void EmitX64::EmitVectorGetElement32(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorGetElement64(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     if (index == 0) {
@@ -275,7 +275,7 @@ void EmitX64::EmitVectorGetElement64(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorSetElement8(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
     const Xbyak::Xmm source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]);
 
@@ -307,7 +307,7 @@ void EmitX64::EmitVectorSetElement8(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorSetElement16(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     const Xbyak::Xmm source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]);
@@ -320,7 +320,7 @@ void EmitX64::EmitVectorSetElement16(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorSetElement32(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
     const Xbyak::Xmm source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]);
 
@@ -343,7 +343,7 @@ void EmitX64::EmitVectorSetElement32(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorSetElement64(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
     const Xbyak::Xmm source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]);
 
@@ -748,9 +748,9 @@ void EmitX64::EmitVectorBroadcast64(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitVectorBroadcastElementLower8(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 16);
+    assert(index < 16);
     if (index > 0) {
         code.psrldq(a, index);
     }
@@ -772,9 +772,9 @@ void EmitX64::EmitVectorBroadcastElementLower8(EmitContext& ctx, IR::Inst* inst)
 void EmitX64::EmitVectorBroadcastElementLower16(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 8);
+    assert(index < 8);
     if (index > 0) {
         code.psrldq(a, u8(index * 2));
     }
@@ -785,9 +785,9 @@ void EmitX64::EmitVectorBroadcastElementLower16(EmitContext& ctx, IR::Inst* inst
 void EmitX64::EmitVectorBroadcastElementLower32(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 4);
+    assert(index < 4);
 
     if (index > 0) {
         code.psrldq(a, u8(index * 4));
@@ -801,9 +801,9 @@ void EmitX64::EmitVectorBroadcastElementLower32(EmitContext& ctx, IR::Inst* inst
 void EmitX64::EmitVectorBroadcastElement8(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 16);
+    assert(index < 16);
     if (index > 0) {
         code.psrldq(a, index);
     }
@@ -825,9 +825,9 @@ void EmitX64::EmitVectorBroadcastElement8(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitVectorBroadcastElement16(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 8);
+    assert(index < 8);
     if (index == 0 && code.HasHostFeature(HostFeature::AVX2)) {
         code.vpbroadcastw(a, a);
     } else {
@@ -845,9 +845,9 @@ void EmitX64::EmitVectorBroadcastElement16(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitVectorBroadcastElement32(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 4);
+    assert(index < 4);
 
     code.pshufd(a, a, mcl::bit::replicate_element<2, u8>(index));
 
@@ -857,9 +857,9 @@ void EmitX64::EmitVectorBroadcastElement32(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitVectorBroadcastElement64(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    assert(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 2);
+    assert(index < 2);
 
     if (code.HasHostFeature(HostFeature::AVX)) {
         code.vpermilpd(a, a, mcl::bit::replicate_element<1, u8>(index));
@@ -1345,7 +1345,7 @@ void EmitX64::EmitVectorExtract(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
 
     const u8 position = args[2].GetImmediateU8();
-    ASSERT(position % 8 == 0);
+    assert(position % 8 == 0);
 
     if (position == 0) {
         ctx.reg_alloc.DefineValue(code, inst, args[0]);
@@ -1377,7 +1377,7 @@ void EmitX64::EmitVectorExtractLower(EmitContext& ctx, IR::Inst* inst) {
     const Xbyak::Xmm xmm_a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
 
     const u8 position = args[2].GetImmediateU8();
-    ASSERT(position % 8 == 0);
+    assert(position % 8 == 0);
 
     if (position != 0) {
         const Xbyak::Xmm xmm_b = ctx.reg_alloc.UseXmm(code, args[1]);
@@ -2280,27 +2280,27 @@ void EmitX64::EmitVectorMultiply64(EmitContext& ctx, IR::Inst* inst) {
 }
 
 void EmitX64::EmitVectorMultiplySignedWiden8(EmitContext&, IR::Inst*) {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void EmitX64::EmitVectorMultiplySignedWiden16(EmitContext&, IR::Inst*) {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void EmitX64::EmitVectorMultiplySignedWiden32(EmitContext&, IR::Inst*) {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void EmitX64::EmitVectorMultiplyUnsignedWiden8(EmitContext&, IR::Inst*) {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void EmitX64::EmitVectorMultiplyUnsignedWiden16(EmitContext&, IR::Inst*) {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void EmitX64::EmitVectorMultiplyUnsignedWiden32(EmitContext&, IR::Inst*) {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void EmitX64::EmitVectorNarrow16(EmitContext& ctx, IR::Inst* inst) {
@@ -3527,7 +3527,7 @@ void EmitX64::EmitVectorRotateWholeVectorRight(EmitContext& ctx, IR::Inst* inst)
     const Xbyak::Xmm operand = ctx.reg_alloc.UseXmm(code, args[0]);
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     const u8 shift_amount = args[1].GetImmediateU8();
-    ASSERT(shift_amount % 32 == 0);
+    assert(shift_amount % 32 == 0);
     const u8 shuffle_imm = std::rotr<u8>(0b11100100, shift_amount / 32 * 2);
 
     code.pshufd(result, operand, shuffle_imm);
@@ -3869,7 +3869,7 @@ static void EmitVectorSignedAbsoluteDifference(size_t esize, EmitContext& ctx, I
             code.psubd(x, tmp);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     } else {
         code.movdqa(tmp, y);
@@ -3888,7 +3888,7 @@ static void EmitVectorSignedAbsoluteDifference(size_t esize, EmitContext& ctx, I
             code.psubd(x, tmp);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -4092,7 +4092,7 @@ static void EmitVectorSignedSaturatedAbs(size_t esize, BlockOfCode& code, EmitCo
         break;
     }
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     code.or_(code.dword[code.ABI_JIT_PTR + code.GetJitStateInfo().offsetof_fpsr_qc], bit);
@@ -4542,7 +4542,7 @@ static void EmitVectorSignedSaturatedNarrowToSigned(size_t original_esize, Block
         code.punpcklwd(reconstructed, sign);
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     const Xbyak::Reg32 bit = ctx.reg_alloc.ScratchGpr(code).cvt32();
@@ -4591,13 +4591,13 @@ static void EmitVectorSignedSaturatedNarrowToUnsigned(size_t original_esize, Blo
         code.punpcklbw(reconstructed, xmm0);
         break;
     case 32:
-        ASSERT(code.HasHostFeature(HostFeature::SSE41));
+        assert(code.HasHostFeature(HostFeature::SSE41));
         code.packusdw(dest, xmm0);  // SSE4.1
         code.movdqa(reconstructed, dest);
         code.punpcklwd(reconstructed, xmm0);
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     const Xbyak::Reg32 bit = ctx.reg_alloc.ScratchGpr(code).cvt32();
@@ -4661,7 +4661,7 @@ static void EmitVectorSignedSaturatedNeg(size_t esize, BlockOfCode& code, EmitCo
         case 64:
             return code.Const(xword, 0x8000000000000000, 0x8000000000000000);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }();
 
@@ -4874,11 +4874,11 @@ void EmitX64::EmitVectorSub64(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorTable(EmitContext&, IR::Inst* inst) {
     // Do nothing. We *want* to hold on to the refcount for our arguments, so VectorTableLookup can use our arguments.
-    ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times");
+    assert(inst->UseCount() == 1 && "Table cannot be used multiple times");
 }
 
 void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) {
-    ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
+    assert(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst());
@@ -4957,7 +4957,7 @@ void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) {
             break;
         }
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
             break;
         }
         return;
@@ -5036,7 +5036,7 @@ void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) {
             code.pxor(xmm0, xmm0);
             code.punpcklqdq(xmm_table1, xmm0);
         } else {
-            ASSERT(table_size == 4);
+            assert(table_size == 4);
             const Xbyak::Xmm xmm_table1_upper = ctx.reg_alloc.UseXmm(code, table[3]);
             code.punpcklqdq(xmm_table1, xmm_table1_upper);
             ctx.reg_alloc.Release(xmm_table1_upper);
@@ -5133,7 +5133,7 @@ void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) {
 }
 
 void EmitX64::EmitVectorTableLookup128(EmitContext& ctx, IR::Inst* inst) {
-    ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
+    assert(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst());
@@ -5854,3 +5854,5 @@ void EmitX64::EmitZeroVector(EmitContext& ctx, IR::Inst* inst) {
 }
 
 }  // namespace Dynarmic::Backend::X64
+
+#undef ICODE
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp
index 70edfbd0bc..9c3d972fd7 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp
@@ -12,7 +12,7 @@
 #include <type_traits>
 #include <utility>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/function_info.hpp"
 #include "dynarmic/mcl/integer_of_size.hpp"
 #include "dynarmic/backend/x64/xbyak.h"
@@ -265,7 +265,7 @@ struct PairedIndexer {
         case 1:
             return std::make_tuple(b[2 * i], b[2 * i + 1]);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 };
 
@@ -288,7 +288,7 @@ struct PairedLowerIndexer {
             }
             return std::make_tuple(0, 0);
         } else {
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 };
@@ -681,7 +681,7 @@ void EmitX64::EmitFPVectorFromHalf32(EmitContext& ctx, IR::Inst* inst) {
             EmitTwoOpFallback<2>(code, ctx, inst, EmitFPVectorFromHalf32Thunk<FP::RoundingMode::ToNearest_TieAwayFromZero>);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 }
@@ -692,7 +692,7 @@ void EmitX64::EmitFPVectorFromSignedFixed32(EmitContext& ctx, IR::Inst* inst) {
     const int fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
     const bool fpcr_controlled = args[3].GetImmediateU1();
-    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    assert(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
         code.cvtdq2ps(xmm, xmm);
@@ -710,7 +710,7 @@ void EmitX64::EmitFPVectorFromSignedFixed64(EmitContext& ctx, IR::Inst* inst) {
     const int fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
     const bool fpcr_controlled = args[3].GetImmediateU1();
-    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    assert(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
         if (code.HasHostFeature(HostFeature::AVX512_OrthoFloat)) {
@@ -761,7 +761,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed32(EmitContext& ctx, IR::Inst* inst)
     const int fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
     const bool fpcr_controlled = args[3].GetImmediateU1();
-    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    assert(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
         if (code.HasHostFeature(HostFeature::AVX512_Ortho)) {
@@ -811,7 +811,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed64(EmitContext& ctx, IR::Inst* inst)
     const int fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
     const bool fpcr_controlled = args[3].GetImmediateU1();
-    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    assert(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
         if (code.HasHostFeature(HostFeature::AVX512_OrthoFloat)) {
@@ -1679,7 +1679,7 @@ void EmitFPVectorRoundInt(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
                 case FP::RoundingMode::TowardsPlusInfinity: return 0b10;
                 case FP::RoundingMode::TowardsMinusInfinity: return 0b01;
                 case FP::RoundingMode::TowardsZero: return 0b11;
-                default: UNREACHABLE();
+                default: std::terminate(); //unreachable
                 }
             }();
 
@@ -1720,7 +1720,7 @@ void EmitFPVectorRoundInt(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
             : EmitTwoOpFallback<3>(code, ctx, inst, EmitFPVectorRoundIntThunk<FPT, FP::RoundingMode::ToNearest_TieAwayFromZero, false>);
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -1988,7 +1988,7 @@ void EmitX64::EmitFPVectorToHalf32(EmitContext& ctx, IR::Inst* inst) {
             EmitTwoOpFallback<2>(code, ctx, inst, EmitFPVectorToHalf32Thunk<FP::RoundingMode::ToNearest_TieAwayFromZero>);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 }
diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp
index 03ded4066d..f9ad53c5a7 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -6,7 +6,7 @@
  * SPDX-License-Identifier: 0BSD
  */
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/backend/x64/block_of_code.h"
 #include "dynarmic/backend/x64/constants.h"
@@ -52,12 +52,12 @@ void EmitVectorSaturatedNative(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
     ctx.reg_alloc.DefineValue(code, inst, result);
 }
 
-enum class Op {
+enum class VectorSaturationOp {
     Add,
     Sub,
 };
 
-template<Op op, size_t esize>
+template<VectorSaturationOp op, size_t esize>
 void EmitVectorSignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
     static_assert(esize == 32 || esize == 64);
     constexpr u64 msb_mask = esize == 32 ? 0x8000000080000000 : 0x8000000000000000;
@@ -72,7 +72,7 @@ void EmitVectorSignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
 
         code.movaps(xmm0, operand1);
 
-        if constexpr (op == Op::Add) {
+        if constexpr (op == VectorSaturationOp::Add) {
             ICODE(vpadd)(result, operand1, operand2);
             code.vpternlogd(xmm0, result, operand2, 0b00100100);
         } else {
@@ -102,7 +102,7 @@ void EmitVectorSignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
     const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm(code);
 
     if (code.HasHostFeature(HostFeature::AVX)) {
-        if constexpr (op == Op::Add) {
+        if constexpr (op == VectorSaturationOp::Add) {
             ICODE(vpadd)(result, operand1, operand2);
         } else {
             ICODE(vpsub)(result, operand1, operand2);
@@ -112,7 +112,7 @@ void EmitVectorSignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
     } else {
         code.movaps(xmm0, operand1);
         code.movaps(tmp, operand1);
-        if constexpr (op == Op::Add) {
+        if constexpr (op == VectorSaturationOp::Add) {
             ICODE(padd)(result, operand2);
         } else {
             ICODE(psub)(result, operand2);
@@ -121,7 +121,7 @@ void EmitVectorSignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
         code.pxor(tmp, result);
     }
 
-    if constexpr (op == Op::Add) {
+    if constexpr (op == VectorSaturationOp::Add) {
         code.pandn(xmm0, tmp);
     } else {
         code.pand(xmm0, tmp);
@@ -165,7 +165,7 @@ void EmitVectorSignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
     }
 }
 
-template<Op op, size_t esize>
+template<VectorSaturationOp op, size_t esize>
 void EmitVectorUnsignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
     static_assert(esize == 32 || esize == 64);
 
@@ -177,7 +177,7 @@ void EmitVectorUnsignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst*
         const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
         const Xbyak::Reg8 overflow = ctx.reg_alloc.ScratchGpr(code).cvt8();
 
-        if constexpr (op == Op::Add) {
+        if constexpr (op == VectorSaturationOp::Add) {
             ICODE(vpadd)(result, operand1, operand2);
             ICODE(vpcmpu)(k1, result, operand1, CmpInt::LessThan);
             ICODE(vpternlog)(result | k1, result, result, u8(0xFF));
@@ -201,7 +201,7 @@ void EmitVectorUnsignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst*
     const Xbyak::Reg8 overflow = ctx.reg_alloc.ScratchGpr(code).cvt8();
     const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm(code);
 
-    if constexpr (op == Op::Add) {
+    if constexpr (op == VectorSaturationOp::Add) {
         if (code.HasHostFeature(HostFeature::AVX)) {
             code.vpxor(xmm0, operand1, operand2);
             code.vpand(tmp, operand1, operand2);
@@ -250,7 +250,7 @@ void EmitVectorUnsignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst*
     code.setnz(overflow);
     code.or_(code.byte[code.ABI_JIT_PTR + code.GetJitStateInfo().offsetof_fpsr_qc], overflow);
 
-    if constexpr (op == Op::Add) {
+    if constexpr (op == VectorSaturationOp::Add) {
         code.por(result, tmp);
         ctx.reg_alloc.DefineValue(code, inst, result);
     } else {
@@ -270,11 +270,11 @@ void EmitX64::EmitVectorSignedSaturatedAdd16(EmitContext& ctx, IR::Inst* inst) {
 }
 
 void EmitX64::EmitVectorSignedSaturatedAdd32(EmitContext& ctx, IR::Inst* inst) {
-    EmitVectorSignedSaturated<Op::Add, 32>(code, ctx, inst);
+    EmitVectorSignedSaturated<VectorSaturationOp::Add, 32>(code, ctx, inst);
 }
 
 void EmitX64::EmitVectorSignedSaturatedAdd64(EmitContext& ctx, IR::Inst* inst) {
-    EmitVectorSignedSaturated<Op::Add, 64>(code, ctx, inst);
+    EmitVectorSignedSaturated<VectorSaturationOp::Add, 64>(code, ctx, inst);
 }
 
 void EmitX64::EmitVectorSignedSaturatedSub8(EmitContext& ctx, IR::Inst* inst) {
@@ -286,11 +286,11 @@ void EmitX64::EmitVectorSignedSaturatedSub16(EmitContext& ctx, IR::Inst* inst) {
 }
 
 void EmitX64::EmitVectorSignedSaturatedSub32(EmitContext& ctx, IR::Inst* inst) {
-    EmitVectorSignedSaturated<Op::Sub, 32>(code, ctx, inst);
+    EmitVectorSignedSaturated<VectorSaturationOp::Sub, 32>(code, ctx, inst);
 }
 
 void EmitX64::EmitVectorSignedSaturatedSub64(EmitContext& ctx, IR::Inst* inst) {
-    EmitVectorSignedSaturated<Op::Sub, 64>(code, ctx, inst);
+    EmitVectorSignedSaturated<VectorSaturationOp::Sub, 64>(code, ctx, inst);
 }
 
 void EmitX64::EmitVectorUnsignedSaturatedAdd8(EmitContext& ctx, IR::Inst* inst) {
@@ -302,11 +302,11 @@ void EmitX64::EmitVectorUnsignedSaturatedAdd16(EmitContext& ctx, IR::Inst* inst)
 }
 
 void EmitX64::EmitVectorUnsignedSaturatedAdd32(EmitContext& ctx, IR::Inst* inst) {
-    EmitVectorUnsignedSaturated<Op::Add, 32>(code, ctx, inst);
+    EmitVectorUnsignedSaturated<VectorSaturationOp::Add, 32>(code, ctx, inst);
 }
 
 void EmitX64::EmitVectorUnsignedSaturatedAdd64(EmitContext& ctx, IR::Inst* inst) {
-    EmitVectorUnsignedSaturated<Op::Add, 64>(code, ctx, inst);
+    EmitVectorUnsignedSaturated<VectorSaturationOp::Add, 64>(code, ctx, inst);
 }
 
 void EmitX64::EmitVectorUnsignedSaturatedSub8(EmitContext& ctx, IR::Inst* inst) {
@@ -318,11 +318,11 @@ void EmitX64::EmitVectorUnsignedSaturatedSub16(EmitContext& ctx, IR::Inst* inst)
 }
 
 void EmitX64::EmitVectorUnsignedSaturatedSub32(EmitContext& ctx, IR::Inst* inst) {
-    EmitVectorUnsignedSaturated<Op::Sub, 32>(code, ctx, inst);
+    EmitVectorUnsignedSaturated<VectorSaturationOp::Sub, 32>(code, ctx, inst);
 }
 
 void EmitX64::EmitVectorUnsignedSaturatedSub64(EmitContext& ctx, IR::Inst* inst) {
-    EmitVectorUnsignedSaturated<Op::Sub, 64>(code, ctx, inst);
+    EmitVectorUnsignedSaturated<VectorSaturationOp::Sub, 64>(code, ctx, inst);
 }
 
 }  // namespace Dynarmic::Backend::X64
diff --git a/src/dynarmic/src/dynarmic/backend/x64/exception_handler_windows.cpp b/src/dynarmic/src/dynarmic/backend/x64/exception_handler_windows.cpp
index 3ae553bccd..9b091687dd 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/exception_handler_windows.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/exception_handler_windows.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -12,9 +12,9 @@
 #include <cstring>
 #include <vector>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include <bit>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/backend/exception_handler.h"
 #include "dynarmic/backend/x64/block_of_code.h"
@@ -104,7 +104,7 @@ static PrologueInformation GetPrologueInformation() {
         entry.code.OpInfo = reg;
     };
     const auto alloc_large = [&](u8 offset, size_t size) {
-        ASSERT(size % 8 == 0);
+        assert(size % 8 == 0);
         size /= 8;
 
         auto& entry = next_entry();
@@ -123,7 +123,7 @@ static PrologueInformation GetPrologueInformation() {
         }
     };
     const auto save_xmm128 = [&](u8 offset, u8 reg, size_t frame_offset) {
-        ASSERT(frame_offset % 16 == 0);
+        assert(frame_offset % 16 == 0);
 
         auto& entry = next_entry();
         entry.code.CodeOffset = offset;
@@ -165,7 +165,7 @@ static PrologueInformation GetPrologueInformation() {
         auto& last_entry = next_entry();
         last_entry.FrameOffset = 0;
     }
-    ASSERT(ret.unwind_code.size() % 2 == 0);
+    assert(ret.unwind_code.size() % 2 == 0);
 
     return ret;
 }
diff --git a/src/dynarmic/src/dynarmic/backend/x64/exclusive_monitor.cpp b/src/dynarmic/src/dynarmic/backend/x64/exclusive_monitor.cpp
index f8237c99e8..71054c31f3 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/exclusive_monitor.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/exclusive_monitor.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <algorithm>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 namespace Dynarmic {
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/host_feature.h b/src/dynarmic/src/dynarmic/backend/x64/host_feature.h
index 34dca971cb..019a36635b 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/host_feature.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/host_feature.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,7 +8,7 @@
 
 #pragma once
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Backend::X64 {
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/hostloc.h b/src/dynarmic/src/dynarmic/backend/x64/hostloc.h
index 2feecf5d5e..654ffa7510 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/hostloc.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/hostloc.h
@@ -10,8 +10,8 @@
 #include <bitset>
 #include <xbyak/xbyak.h>
 
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 #include "dynarmic/backend/x64/xbyak.h"
 
 namespace Dynarmic::Backend::X64 {
@@ -80,12 +80,12 @@ constexpr bool HostLocIsFlag(HostLoc reg) {
 }
 
 constexpr HostLoc HostLocRegIdx(int idx) {
-    ASSERT(idx >= 0 && idx <= 15);
+    assert(idx >= 0 && idx <= 15);
     return HostLoc(idx);
 }
 
 constexpr HostLoc HostLocXmmIdx(int idx) {
-    ASSERT(idx >= 0 && idx <= 15);
+    assert(idx >= 0 && idx <= 15);
     return HostLoc(size_t(HostLoc::XMM0) + idx);
 }
 
@@ -106,7 +106,7 @@ constexpr size_t HostLocBitWidth(HostLoc loc) {
         return 128;
     else if (HostLocIsFlag(loc))
         return 1;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 constexpr std::bitset<32> BuildRegSet(std::initializer_list<HostLoc> regs) {
@@ -161,12 +161,12 @@ const std::bitset<32> any_xmm = BuildRegSet({
 });
 
 inline Xbyak::Reg64 HostLocToReg64(HostLoc loc) noexcept {
-    ASSERT(HostLocIsGPR(loc));
+    assert(HostLocIsGPR(loc));
     return Xbyak::Reg64(int(loc));
 }
 
 inline Xbyak::Xmm HostLocToXmm(HostLoc loc) noexcept {
-    ASSERT(HostLocIsXMM(loc));
+    assert(HostLocIsXMM(loc));
     return Xbyak::Xmm(int(loc) - int(HostLoc::XMM0));
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/nzcv_util.h b/src/dynarmic/src/dynarmic/backend/x64/nzcv_util.h
index 1ee0ed4329..2abe06e035 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/nzcv_util.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/nzcv_util.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,17 +8,18 @@
 
 #pragma once
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
+#include <cstddef>
 
 namespace Dynarmic::Backend::X64::NZCV {
 
 constexpr u32 arm_mask = 0xF000'0000;
 constexpr u32 x64_mask = 0xC101;
 
-constexpr size_t x64_n_flag_bit = 15;
-constexpr size_t x64_z_flag_bit = 14;
-constexpr size_t x64_c_flag_bit = 8;
-constexpr size_t x64_v_flag_bit = 0;
+constexpr std::size_t x64_n_flag_bit = 15;
+constexpr std::size_t x64_z_flag_bit = 14;
+constexpr std::size_t x64_c_flag_bit = 8;
+constexpr std::size_t x64_v_flag_bit = 0;
 
 /// This is a constant used to create the x64 flags format from the ARM format.
 /// NZCV * multiplier: NZCV0NZCV000NZCV
@@ -46,7 +47,7 @@ inline u32 FromX64(u32 x64_flags) {
     nzcv |= mcl::bit::get_bit<15>(x64_flags) ? 1 << 31 : 0;
     nzcv |= mcl::bit::get_bit<14>(x64_flags) ? 1 << 30 : 0;
     nzcv |= mcl::bit::get_bit<8>(x64_flags) ? 1 << 29 : 0;
-    nzcv |= mcl::bit::get_bit<0>(x64_flags) ? 1 << 28 : 0;
+    nzcv |= mcl::bit::get_bit<0>(x64_flaags) ? 1 << 28 : 0;
     return nzcv;
     */
     return ((x64_flags & x64_mask) * from_x64_multiplier) & arm_mask;
diff --git a/src/dynarmic/src/dynarmic/backend/x64/oparg.h b/src/dynarmic/src/dynarmic/backend/x64/oparg.h
index d16728d19f..bd2e68b3dd 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/oparg.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/oparg.h
@@ -8,7 +8,7 @@
 
 #pragma once
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/backend/x64/xbyak.h"
 
 namespace Dynarmic::Backend::X64 {
@@ -30,7 +30,7 @@ struct OpArg {
         case Type::Reg:
             return inner_reg;
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     void setBit(int bits) {
@@ -57,7 +57,7 @@ struct OpArg {
                 return;
             }
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
 private:
diff --git a/src/dynarmic/src/dynarmic/backend/x64/perf_map.cpp b/src/dynarmic/src/dynarmic/backend/x64/perf_map.cpp
index 095d6194f6..eaa6c9e2b8 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/perf_map.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/perf_map.cpp
@@ -11,7 +11,7 @@
 #include <fmt/format.h>
 
 #include "dynarmic/backend/x64/perf_map.h"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #if defined(__linux__) && !defined(__ANDROID__)
 #    include <cstdio>
 #    include <cstdlib>
diff --git a/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp b/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp
index 5c5ed25131..a02657dd55 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp
+++ b/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp
@@ -13,7 +13,7 @@
 
 #include <fmt/ostream.h>
 #include "dynarmic/backend/x64/hostloc.h"
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include <bit>
 #include "dynarmic/backend/x64/xbyak.h"
 
@@ -47,7 +47,7 @@ static inline size_t GetBitWidth(const IR::Type type) noexcept {
         return 32;  // TODO: Update to 16 when flags optimization is done
     default:
         // A32REG A32EXTREG A64REG A64VEC COPROCINFO COND VOID TABLE ACCTYPE OPAQUE
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -56,11 +56,11 @@ static inline bool IsValuelessType(const IR::Type type) noexcept {
 }
 
 void HostLocInfo::ReleaseOne() noexcept {
-    ASSERT(is_being_used_count > 0);
+    assert(is_being_used_count > 0);
     --is_being_used_count;
     is_scratch = false;
     if (current_references > 0) {
-        ASSERT(size_t(accumulated_uses) + 1 < (std::numeric_limits<decltype(accumulated_uses)>::max)());
+        assert(size_t(accumulated_uses) + 1 < (std::numeric_limits<decltype(accumulated_uses)>::max)());
         ++accumulated_uses;
         --current_references;
         if (current_references == 0)
@@ -69,7 +69,7 @@ void HostLocInfo::ReleaseOne() noexcept {
 }
 
 void HostLocInfo::ReleaseAll() noexcept {
-    ASSERT(size_t(accumulated_uses) + current_references < (std::numeric_limits<decltype(accumulated_uses)>::max)());
+    assert(size_t(accumulated_uses) + current_references < (std::numeric_limits<decltype(accumulated_uses)>::max)());
     accumulated_uses += current_references;
     current_references = 0;
     is_set_last_use = false;
@@ -91,7 +91,7 @@ void HostLocInfo::AddValue(HostLoc loc, IR::Inst* inst) noexcept {
     }
     values.push_back(inst);
 
-    ASSERT(size_t(total_uses) + inst->UseCount() < (std::numeric_limits<decltype(total_uses)>::max)());
+    assert(size_t(total_uses) + inst->UseCount() < (std::numeric_limits<decltype(total_uses)>::max)());
     total_uses += inst->UseCount();
     max_bit_width = std::max<uint8_t>(max_bit_width, std::countr_zero(GetBitWidth(inst->GetType())));
 }
@@ -129,24 +129,24 @@ bool Argument::GetImmediateU1() const noexcept {
 
 u8 Argument::GetImmediateU8() const noexcept {
     const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm <= u64(std::numeric_limits<u8>::max()));
+    assert(imm <= u64(std::numeric_limits<u8>::max()));
     return u8(imm);
 }
 
 u16 Argument::GetImmediateU16() const noexcept {
     const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm <= u64(std::numeric_limits<u16>::max()));
+    assert(imm <= u64(std::numeric_limits<u16>::max()));
     return u16(imm);
 }
 
 u32 Argument::GetImmediateU32() const noexcept {
     const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm <= u64(std::numeric_limits<u32>::max()));
+    assert(imm <= u64(std::numeric_limits<u32>::max()));
     return u32(imm);
 }
 
 u64 Argument::GetImmediateS32() const noexcept {
-    ASSERT(FitsInImmediateS32());
+    assert(FitsInImmediateS32());
     return value.GetImmediateAsU64();
 }
 
@@ -155,12 +155,12 @@ u64 Argument::GetImmediateU64() const noexcept {
 }
 
 IR::Cond Argument::GetImmediateCond() const noexcept {
-    ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
+    assert(IsImmediate() && GetType() == IR::Type::Cond);
     return value.GetCond();
 }
 
 IR::AccType Argument::GetImmediateAccType() const noexcept {
-    ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
+    assert(IsImmediate() && GetType() == IR::Type::AccType);
     return value.GetAccType();
 }
 
@@ -201,7 +201,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(const IR::Inst* inst) noexcept
         ret[i].value = arg;
         if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
             auto const loc = ValueLocation(arg.GetInst());
-            ASSERT(loc && "argument must already been defined");
+            assert(loc && "argument must already been defined");
             LocInfo(*loc).AddArgReference();
         }
     }
@@ -209,7 +209,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(const IR::Inst* inst) noexcept
 }
 
 void RegAlloc::RegisterPseudoOperation(const IR::Inst* inst) noexcept {
-    ASSERT(IsValueLive(inst) || !inst->HasUses());
+    assert(IsValueLive(inst) || !inst->HasUses());
     for (size_t i = 0; i < inst->NumArgs(); i++) {
         auto const arg = inst->GetArg(i);
         if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
@@ -222,37 +222,37 @@ void RegAlloc::RegisterPseudoOperation(const IR::Inst* inst) noexcept {
 }
 
 Xbyak::Reg64 RegAlloc::UseScratchGpr(BlockOfCode& code, Argument& arg) noexcept {
-    ASSERT(!arg.allocated);
+    assert(!arg.allocated);
     arg.allocated = true;
     return HostLocToReg64(UseScratchImpl(code, arg.value, gpr_order));
 }
 
 Xbyak::Xmm RegAlloc::UseScratchXmm(BlockOfCode& code, Argument& arg) noexcept {
-    ASSERT(!arg.allocated);
+    assert(!arg.allocated);
     arg.allocated = true;
     return HostLocToXmm(UseScratchImpl(code, arg.value, xmm_order));
 }
 
 void RegAlloc::UseScratch(BlockOfCode& code, Argument& arg, HostLoc host_loc) noexcept {
-    ASSERT(!arg.allocated);
+    assert(!arg.allocated);
     arg.allocated = true;
     UseScratchImpl(code, arg.value, BuildRegSet({host_loc}));
 }
 
 void RegAlloc::DefineValue(BlockOfCode& code, IR::Inst* inst, const Xbyak::Reg& reg) noexcept {
-    ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
+    assert(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
     const auto hostloc = static_cast<HostLoc>(reg.getIdx() + static_cast<size_t>(reg.getKind() == Xbyak::Operand::XMM ? HostLoc::XMM0 : HostLoc::RAX));
     DefineValueImpl(code, inst, hostloc);
 }
 
 void RegAlloc::DefineValue(BlockOfCode& code, IR::Inst* inst, Argument& arg) noexcept {
-    ASSERT(!arg.allocated);
+    assert(!arg.allocated);
     arg.allocated = true;
     DefineValueImpl(code, inst, arg.value);
 }
 
 void RegAlloc::Release(const Xbyak::Reg& reg) noexcept {
-    ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
+    assert(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
     const auto hostloc = static_cast<HostLoc>(reg.getIdx() + static_cast<size_t>(reg.getKind() == Xbyak::Operand::XMM ? HostLoc::XMM0 : HostLoc::RAX));
     LocInfo(hostloc).ReleaseOne();
 }
@@ -375,22 +375,22 @@ void RegAlloc::HostCall(
             case IR::Type::U64:
                 break; //no op
             default:
-                UNREACHABLE();
+                std::terminate(); //unreachable
             }
         }
     }
 }
 
 void RegAlloc::AllocStackSpace(BlockOfCode& code, const size_t stack_space) noexcept {
-    ASSERT(stack_space < size_t((std::numeric_limits<s32>::max)()));
-    ASSERT(reserved_stack_space == 0);
+    assert(stack_space < size_t((std::numeric_limits<s32>::max)()));
+    assert(reserved_stack_space == 0);
     reserved_stack_space = stack_space;
     code.sub(code.rsp, u32(stack_space));
 }
 
 void RegAlloc::ReleaseStackSpace(BlockOfCode& code, const size_t stack_space) noexcept {
-    ASSERT(stack_space < size_t((std::numeric_limits<s32>::max)()));
-    ASSERT(reserved_stack_space == stack_space);
+    assert(stack_space < size_t((std::numeric_limits<s32>::max)()));
+    assert(reserved_stack_space == stack_space);
     reserved_stack_space = 0;
     code.add(code.rsp, u32(stack_space));
 }
@@ -410,7 +410,7 @@ HostLoc RegAlloc::SelectARegister(std::bitset<32> desired_locations) const noexc
     for (HostLoc i = HostLoc(0); i < HostLoc(desired_locations.size()); i = HostLoc(size_t(i) + 1)) {
         if (desired_locations.test(size_t(i))) {
             auto const& loc_info = LocInfo(i);
-            DEBUG_ASSERT(i != ABI_JIT_PTR);
+            assert(i != ABI_JIT_PTR);
             // Abstain from using upper registers unless absolutely nescesary
             if (loc_info.IsLocked()) {
                 // skip, not suitable for allocation
@@ -448,7 +448,7 @@ HostLoc RegAlloc::SelectARegister(std::bitset<32> desired_locations) const noexc
     auto const it_final = it_empty_candidate != HostLoc::FirstSpill
         ? it_empty_candidate : it_candidate != HostLoc::FirstSpill
         ? it_candidate : it_rex_candidate;
-    ASSERT(it_final != HostLoc::FirstSpill && "All candidate registers have already been allocated");
+    assert(it_final != HostLoc::FirstSpill && "All candidate registers have already been allocated");
     // Evil magic - increment LRU counter (will wrap at 256)
     const_cast<RegAlloc*>(this)->LocInfo(HostLoc(it_final)).lru_counter++;
     return HostLoc(it_final);
@@ -458,26 +458,26 @@ std::optional<HostLoc> RegAlloc::ValueLocation(const IR::Inst* value) const noex
     for (size_t i = 0; i < hostloc_info.size(); i++)
         if (hostloc_info[i].ContainsValue(value)) {
             //for (size_t j = 0; j < hostloc_info.size(); ++j)
-            //    ASSERT((i == j || !hostloc_info[j].ContainsValue(value)) && "duplicate defs");
+            //    assert((i == j || !hostloc_info[j].ContainsValue(value)) && "duplicate defs");
             return HostLoc(i);
         }
     return std::nullopt;
 }
 
 void RegAlloc::DefineValueImpl(BlockOfCode& code, IR::Inst* def_inst, HostLoc host_loc) noexcept {
-    ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined");
+    assert(!ValueLocation(def_inst) && "def_inst has already been defined");
     LocInfo(host_loc).AddValue(host_loc, def_inst);
-    ASSERT(*ValueLocation(def_inst) == host_loc);
+    assert(*ValueLocation(def_inst) == host_loc);
 }
 
 void RegAlloc::DefineValueImpl(BlockOfCode& code, IR::Inst* def_inst, const IR::Value& use_inst) noexcept {
-    ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined");
+    assert(!ValueLocation(def_inst) && "def_inst has already been defined");
     if (use_inst.IsImmediate()) {
         const HostLoc location = ScratchImpl(code, gpr_order);
         DefineValueImpl(code, def_inst, location);
         LoadImmediate(code, use_inst, location);
     } else {
-        ASSERT(ValueLocation(use_inst.GetInst()) && "use_inst must already be defined");
+        assert(ValueLocation(use_inst.GetInst()) && "use_inst must already be defined");
         const HostLoc location = *ValueLocation(use_inst.GetInst());
         DefineValueImpl(code, def_inst, location);
     }
@@ -485,22 +485,22 @@ void RegAlloc::DefineValueImpl(BlockOfCode& code, IR::Inst* def_inst, const IR::
 
 void RegAlloc::Move(BlockOfCode& code, HostLoc to, HostLoc from) noexcept {
     const size_t bit_width = LocInfo(from).GetMaxBitWidth();
-    ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsLocked());
-    ASSERT(bit_width <= HostLocBitWidth(to));
-    ASSERT(!LocInfo(from).IsEmpty() && "Mov eliminated");
+    assert(LocInfo(to).IsEmpty() && !LocInfo(from).IsLocked());
+    assert(bit_width <= HostLocBitWidth(to));
+    assert(!LocInfo(from).IsEmpty() && "Mov eliminated");
     EmitMove(code, bit_width, to, from);
     LocInfo(to) = std::exchange(LocInfo(from), {});
 }
 
 void RegAlloc::CopyToScratch(BlockOfCode& code, size_t bit_width, HostLoc to, HostLoc from) noexcept {
-    ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsEmpty());
+    assert(LocInfo(to).IsEmpty() && !LocInfo(from).IsEmpty());
     EmitMove(code, bit_width, to, from);
 }
 
 void RegAlloc::Exchange(BlockOfCode& code, HostLoc a, HostLoc b) noexcept {
-    ASSERT(!LocInfo(a).IsLocked() && !LocInfo(b).IsLocked());
-    ASSERT(LocInfo(a).GetMaxBitWidth() <= HostLocBitWidth(b));
-    ASSERT(LocInfo(b).GetMaxBitWidth() <= HostLocBitWidth(a));
+    assert(!LocInfo(a).IsLocked() && !LocInfo(b).IsLocked());
+    assert(LocInfo(a).GetMaxBitWidth() <= HostLocBitWidth(b));
+    assert(LocInfo(b).GetMaxBitWidth() <= HostLocBitWidth(a));
 
     if (LocInfo(a).IsEmpty()) {
         Move(code, a, b);
@@ -513,16 +513,16 @@ void RegAlloc::Exchange(BlockOfCode& code, HostLoc a, HostLoc b) noexcept {
 }
 
 void RegAlloc::MoveOutOfTheWay(BlockOfCode& code, HostLoc reg) noexcept {
-    ASSERT(!LocInfo(reg).IsLocked());
+    assert(!LocInfo(reg).IsLocked());
     if (!LocInfo(reg).IsEmpty()) {
         SpillRegister(code, reg);
     }
 }
 
 void RegAlloc::SpillRegister(BlockOfCode& code, HostLoc loc) noexcept {
-    ASSERT(HostLocIsRegister(loc) && "Only registers can be spilled");
-    ASSERT(!LocInfo(loc).IsEmpty() && "There is no need to spill unoccupied registers");
-    ASSERT(!LocInfo(loc).IsLocked() && "Registers that have been allocated must not be spilt");
+    assert(HostLocIsRegister(loc) && "Only registers can be spilled");
+    assert(!LocInfo(loc).IsEmpty() && "There is no need to spill unoccupied registers");
+    assert(!LocInfo(loc).IsLocked() && "Registers that have been allocated must not be spilt");
     auto const new_loc = FindFreeSpill(HostLocIsXMM(loc));
     Move(code, new_loc, loc);
 }
@@ -548,7 +548,7 @@ HostLoc RegAlloc::FindFreeSpill(bool is_xmm) const noexcept {
     for (size_t i = size_t(HostLoc::FirstSpill); i < hostloc_info.size(); ++i)
         if (const auto loc = HostLoc(i); LocInfo(loc).IsEmpty())
             return loc;
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 #define MAYBE_AVX(OPCODE, ...) \
@@ -558,7 +558,7 @@ HostLoc RegAlloc::FindFreeSpill(bool is_xmm) const noexcept {
     }()
 
 HostLoc RegAlloc::LoadImmediate(BlockOfCode& code, IR::Value imm, HostLoc host_loc) noexcept {
-    ASSERT(imm.IsImmediate() && "imm is not an immediate");
+    assert(imm.IsImmediate() && "imm is not an immediate");
     if (HostLocIsGPR(host_loc)) {
         const Xbyak::Reg64 reg = HostLocToReg64(host_loc);
         const u64 imm_value = imm.GetImmediateAsU64();
@@ -576,16 +576,16 @@ HostLoc RegAlloc::LoadImmediate(BlockOfCode& code, IR::Value imm, HostLoc host_l
             MAYBE_AVX(movaps, reg, code.Const(code.xword, imm_value));
         }
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
     return host_loc;
 }
 
 void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc to, const HostLoc from) noexcept {
     auto const spill_to_op_arg_helper = [&](HostLoc loc, size_t reserved_stack_space) {
-        ASSERT(HostLocIsSpill(loc));
+        assert(HostLocIsSpill(loc));
         size_t i = size_t(loc) - size_t(HostLoc::FirstSpill);
-        ASSERT(i < SpillCount && "Spill index greater than number of available spill locations");
+        assert(i < SpillCount && "Spill index greater than number of available spill locations");
         return Xbyak::util::rsp + reserved_stack_space + ABI_SHADOW_SPACE + offsetof(StackLayout, spill) + i * sizeof(StackLayout::spill[0]);
     };
     auto const spill_xmm_to_op = [&](const HostLoc loc) {
@@ -594,21 +594,21 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
     if (HostLocIsXMM(to) && HostLocIsXMM(from)) {
         MAYBE_AVX(movaps, HostLocToXmm(to), HostLocToXmm(from));
     } else if (HostLocIsGPR(to) && HostLocIsGPR(from)) {
-        ASSERT(bit_width != 128);
+        assert(bit_width != 128);
         if (bit_width == 64) {
             code.mov(HostLocToReg64(to), HostLocToReg64(from));
         } else {
             code.mov(HostLocToReg64(to).cvt32(), HostLocToReg64(from).cvt32());
         }
     } else if (HostLocIsXMM(to) && HostLocIsGPR(from)) {
-        ASSERT(bit_width != 128);
+        assert(bit_width != 128);
         if (bit_width == 64) {
             MAYBE_AVX(movq, HostLocToXmm(to), HostLocToReg64(from));
         } else {
             MAYBE_AVX(movd, HostLocToXmm(to), HostLocToReg64(from).cvt32());
         }
     } else if (HostLocIsGPR(to) && HostLocIsXMM(from)) {
-        ASSERT(bit_width != 128);
+        assert(bit_width != 128);
         if (bit_width == 64) {
             MAYBE_AVX(movq, HostLocToReg64(to), HostLocToXmm(from));
         } else {
@@ -616,7 +616,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
         }
     } else if (HostLocIsXMM(to) && HostLocIsSpill(from)) {
         const Xbyak::Address spill_addr = spill_xmm_to_op(from);
-        ASSERT(spill_addr.getBit() >= bit_width);
+        assert(spill_addr.getBit() >= bit_width);
         switch (bit_width) {
         case 128:
             MAYBE_AVX(movaps, HostLocToXmm(to), spill_addr);
@@ -630,11 +630,11 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
             MAYBE_AVX(movss, HostLocToXmm(to), spill_addr);
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     } else if (HostLocIsSpill(to) && HostLocIsXMM(from)) {
         const Xbyak::Address spill_addr = spill_xmm_to_op(to);
-        ASSERT(spill_addr.getBit() >= bit_width);
+        assert(spill_addr.getBit() >= bit_width);
         switch (bit_width) {
         case 128:
             MAYBE_AVX(movaps, spill_addr, HostLocToXmm(from));
@@ -648,30 +648,30 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
             MAYBE_AVX(movss, spill_addr, HostLocToXmm(from));
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     } else if (HostLocIsGPR(to) && HostLocIsSpill(from)) {
-        ASSERT(bit_width != 128);
+        assert(bit_width != 128);
         if (bit_width == 64) {
             code.mov(HostLocToReg64(to), Xbyak::util::qword[spill_to_op_arg_helper(from, reserved_stack_space)]);
         } else {
             code.mov(HostLocToReg64(to).cvt32(), Xbyak::util::dword[spill_to_op_arg_helper(from, reserved_stack_space)]);
         }
     } else if (HostLocIsSpill(to) && HostLocIsGPR(from)) {
-        ASSERT(bit_width != 128);
+        assert(bit_width != 128);
         if (bit_width == 64) {
             code.mov(Xbyak::util::qword[spill_to_op_arg_helper(to, reserved_stack_space)], HostLocToReg64(from));
         } else {
             code.mov(Xbyak::util::dword[spill_to_op_arg_helper(to, reserved_stack_space)], HostLocToReg64(from).cvt32());
         }
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 #undef MAYBE_AVX
 
 void RegAlloc::EmitExchange(BlockOfCode& code, const HostLoc a, const HostLoc b) noexcept {
-    ASSERT(HostLocIsGPR(a) && HostLocIsGPR(b) && "Exchanging XMM registers is uneeded OR invalid emit");
+    assert(HostLocIsGPR(a) && HostLocIsGPR(b) && "Exchanging XMM registers is uneeded OR invalid emit");
     code.xchg(HostLocToReg64(a), HostLocToReg64(b));
 }
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.h b/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.h
index 8b872a0e9c..3ca92216cd 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.h
@@ -13,7 +13,7 @@
 #include <optional>
 
 #include "boost/container/small_vector.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include "dynarmic/backend/x64/xbyak.h"
 #include <boost/container/static_vector.hpp>
 #include <boost/container/flat_set.hpp>
@@ -49,19 +49,19 @@ public:
         return is_being_used_count == 0 && current_references == 1 && size_t(accumulated_uses) + 1 == size_t(total_uses);
     }
     inline void ReadLock() noexcept {
-        ASSERT(size_t(is_being_used_count) + 1 < (std::numeric_limits<decltype(is_being_used_count)>::max)());
-        ASSERT(!is_scratch);
+        assert(size_t(is_being_used_count) + 1 < (std::numeric_limits<decltype(is_being_used_count)>::max)());
+        assert(!is_scratch);
         is_being_used_count++;
     }
     inline void WriteLock() noexcept {
-        ASSERT(is_being_used_count == 0);
+        assert(is_being_used_count == 0);
         is_being_used_count++;
         is_scratch = true;
     }
     inline void AddArgReference() noexcept {
-        ASSERT(size_t(current_references) + 1 < (std::numeric_limits<decltype(current_references)>::max)());
+        assert(size_t(current_references) + 1 < (std::numeric_limits<decltype(current_references)>::max)());
         ++current_references;
-        ASSERT(size_t(accumulated_uses) + current_references <= size_t(total_uses));
+        assert(size_t(accumulated_uses) + current_references <= size_t(total_uses));
     }
     void ReleaseOne() noexcept;
     void ReleaseAll() noexcept;
@@ -147,12 +147,12 @@ public:
         return !!ValueLocation(inst);
     }
     inline Xbyak::Reg64 UseGpr(BlockOfCode& code, Argument& arg) noexcept {
-        ASSERT(!arg.allocated);
+        assert(!arg.allocated);
         arg.allocated = true;
         return HostLocToReg64(UseImpl(code, arg.value, gpr_order));
     }
     inline Xbyak::Xmm UseXmm(BlockOfCode& code, Argument& arg) noexcept {
-        ASSERT(!arg.allocated);
+        assert(!arg.allocated);
         arg.allocated = true;
         return HostLocToXmm(UseImpl(code, arg.value, xmm_order));
     }
@@ -160,7 +160,7 @@ public:
         return UseGpr(code, arg);
     }
     inline void Use(BlockOfCode& code, Argument& arg, const HostLoc host_loc) noexcept {
-        ASSERT(!arg.allocated);
+        assert(!arg.allocated);
         arg.allocated = true;
         UseImpl(code, arg.value, BuildRegSet({host_loc}));
     }
@@ -205,7 +205,7 @@ public:
             iter.ReleaseAll();
     }
     inline void AssertNoMoreUses() noexcept {
-        ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), [](const auto& i) noexcept { return i.IsEmpty(); }));
+        assert(std::all_of(hostloc_info.begin(), hostloc_info.end(), [](const auto& i) noexcept { return i.IsEmpty(); }));
     }
 #ifndef NDEBUG
     inline void EmitVerboseDebuggingOutput(BlockOfCode& code) noexcept {
@@ -234,11 +234,11 @@ private:
     HostLoc FindFreeSpill(bool is_xmm) const noexcept;
 
     inline HostLocInfo& LocInfo(const HostLoc loc) noexcept {
-        DEBUG_ASSERT(loc != HostLoc::RSP && loc != ABI_JIT_PTR);
+        assert(loc != HostLoc::RSP && loc != ABI_JIT_PTR);
         return hostloc_info[size_t(loc)];
     }
     inline const HostLocInfo& LocInfo(const HostLoc loc) const noexcept {
-        DEBUG_ASSERT(loc != HostLoc::RSP && loc != ABI_JIT_PTR);
+        assert(loc != HostLoc::RSP && loc != ABI_JIT_PTR);
         return hostloc_info[size_t(loc)];
     }
 
diff --git a/src/dynarmic/src/dynarmic/backend/x64/stack_layout.h b/src/dynarmic/src/dynarmic/backend/x64/stack_layout.h
index 50737f12eb..3ec23ca2ce 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/stack_layout.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/stack_layout.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -9,12 +9,13 @@
 #pragma once
 
 #include <array>
+#include <cstddef>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Backend::X64 {
 
-constexpr size_t SpillCount = 64;
+constexpr std::size_t SpillCount = 64;
 
 #ifdef _MSC_VER
 #    pragma warning(push)
diff --git a/src/dynarmic/src/dynarmic/backend/x64/verbose_debugging_output.h b/src/dynarmic/src/dynarmic/backend/x64/verbose_debugging_output.h
index 3f4823010b..25c4ddc677 100644
--- a/src/dynarmic/src/dynarmic/backend/x64/verbose_debugging_output.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/verbose_debugging_output.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <array>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/backend/x64/stack_layout.h"
 
diff --git a/src/dynarmic/src/dynarmic/common/assert.cpp b/src/dynarmic/src/dynarmic/common/assert.cpp
deleted file mode 100644
index e3419514e8..0000000000
--- a/src/dynarmic/src/dynarmic/common/assert.cpp
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
-// SPDX-License-Identifier: GPL-3.0-or-later
-// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include <cstdio>
-#include <exception>
-
-[[noreturn]] void assert_terminate_impl(const char* s) {
-    std::puts(s);
-    std::fflush(stderr);
-    std::terminate();
-}
diff --git a/src/dynarmic/src/dynarmic/common/assert.h b/src/dynarmic/src/dynarmic/common/assert.h
deleted file mode 100644
index a79d865974..0000000000
--- a/src/dynarmic/src/dynarmic/common/assert.h
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
-// SPDX-License-Identifier: GPL-3.0-or-later
-// SPDX-FileCopyrightText: 2013 Dolphin Emulator Project
-// SPDX-FileCopyrightText: 2014 Citra Emulator Project
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#pragma once
-
-// TODO: Use source_info?
-[[noreturn]] void assert_terminate_impl(const char* s);
-#ifndef ASSERT
-#   define ASSERT(expr) do { auto&& condition = !(expr); if(condition) [[unlikely]] assert_terminate_impl(__FILE__ ": " #expr); } while(0)
-#endif
-#ifndef UNREACHABLE
-#   ifdef _MSC_VER
-#       define UNREACHABLE() ASSERT(false && __FILE__ ": unreachable")
-#   else
-#       define UNREACHABLE() __builtin_unreachable();
-#   endif
-#endif
-#ifndef DEBUG_ASSERT
-#   ifndef NDEBUG
-#       define DEBUG_ASSERT(_a_) ASSERT(_a_)
-#   else
-#       define DEBUG_ASSERT(_a_)
-#   endif
-#endif
diff --git a/src/dynarmic/src/dynarmic/common/atomic.h b/src/dynarmic/src/dynarmic/common/atomic.h
index 966921eb9a..5eb4288517 100644
--- a/src/dynarmic/src/dynarmic/common/atomic.h
+++ b/src/dynarmic/src/dynarmic/common/atomic.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,7 +8,7 @@
 
 #pragma once
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Atomic {
 
diff --git a/src/dynarmic/src/dynarmic/common/common_types.h b/src/dynarmic/src/dynarmic/common/common_types.h
deleted file mode 100644
index 711418d97f..0000000000
--- a/src/dynarmic/src/dynarmic/common/common_types.h
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
-// SPDX-License-Identifier: GPL-3.0-or-later
-
-// TODO(crueter): This is identical to root common_types.h
-
-#pragma once
-
-#include <cstdint>
-#include <cstdlib>
-#include <array>
-
-using u8 = std::uint8_t;   ///< 8-bit unsigned byte
-using u16 = std::uint16_t; ///< 16-bit unsigned short
-using u32 = std::uint32_t; ///< 32-bit unsigned word
-using u64 = std::uint64_t; ///< 64-bit unsigned int
-
-using s8 = std::int8_t;   ///< 8-bit signed byte
-using s16 = std::int16_t; ///< 16-bit signed short
-using s32 = std::int32_t; ///< 32-bit signed word
-using s64 = std::int64_t; ///< 64-bit signed int
-
-using f32 = float;  ///< 32-bit floating point
-using f64 = double; ///< 64-bit floating point
-
-using u128 = std::array<std::uint64_t, 2>;
-static_assert(sizeof(u128) == 16, "u128 must be 128 bits wide");
diff --git a/src/dynarmic/src/dynarmic/common/context.h b/src/dynarmic/src/dynarmic/common/context.h
index 941289cb94..e849c9861b 100644
--- a/src/dynarmic/src/dynarmic/common/context.h
+++ b/src/dynarmic/src/dynarmic/common/context.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 #pragma once
@@ -34,51 +34,24 @@
 #    endif
 #endif
 
-#ifdef ARCHITECTURE_x86_64
+#ifdef ARCHITECTURE_arm64
 #   ifdef __OpenBSD__
 #       define CTX_DECLARE(raw_context) ucontext_t* ucontext = reinterpret_cast<ucontext_t*>(raw_context);
 #   else
-#       define CTX_DECLARE(raw_context) \
-        ucontext_t* ucontext = reinterpret_cast<ucontext_t*>(raw_context);  \
-        [[maybe_unused]] auto& mctx = ucontext->uc_mcontext;
-#   endif
-#elif defined(ARCHITECTURE_arm64)
-#   ifdef __OpenBSD__
-#       define CTX_DECLARE(raw_context) ucontext_t* ucontext = reinterpret_cast<ucontext_t*>(raw_context);
-#   else
-#       define CTX_DECLARE(raw_context) \
-        ucontext_t* ucontext = reinterpret_cast<ucontext_t*>(raw_context);  \
+#       define CTX_DECLARE(raw_context) ucontext_t* ucontext = reinterpret_cast<ucontext_t*>(raw_context);  \
         [[maybe_unused]] auto& mctx = ucontext->uc_mcontext; \
         [[maybe_unused]] const auto fpctx = GetFloatingPointState(mctx);
 #   endif
+#else
+#   ifdef __OpenBSD__
+#       define CTX_DECLARE(raw_context) ucontext_t* ucontext = reinterpret_cast<ucontext_t*>(raw_context);
+#   else
+#       define CTX_DECLARE(raw_context) ucontext_t* ucontext = reinterpret_cast<ucontext_t*>(raw_context);  \
+        [[maybe_unused]] auto& mctx = ucontext->uc_mcontext;
+#   endif
 #endif
 
-#if defined(ARCHITECTURE_x86_64)
-#    if defined(__APPLE__)
-#        define CTX_RIP (mctx->__ss.__rip)
-#        define CTX_RSP (mctx->__ss.__rsp)
-#    elif defined(__linux__)
-#        define CTX_RIP (mctx.gregs[REG_RIP])
-#        define CTX_RSP (mctx.gregs[REG_RSP])
-#    elif defined(__FreeBSD__)
-#        define CTX_RIP (mctx.mc_rip)
-#        define CTX_RSP (mctx.mc_rsp)
-#    elif defined(__NetBSD__)
-#        define CTX_RIP (mctx.__gregs[_REG_RIP])
-#        define CTX_RSP (mctx.__gregs[_REG_RSP])
-#    elif defined(__OpenBSD__)
-#        define CTX_RIP (ucontext->sc_rip)
-#        define CTX_RSP (ucontext->sc_rsp)
-#    elif defined(__sun__)
-#        define CTX_RIP (mctx.gregs[REG_RIP])
-#        define CTX_RSP (mctx.gregs[REG_RSP])
-#    elif defined(__DragonFly__)
-#        define CTX_RIP (mctx.mc_rip)
-#        define CTX_RSP (mctx.mc_rsp)
-#    else
-#        error "Unknown platform"
-#    endif
-#elif defined(ARCHITECTURE_arm64)
+#ifdef ARCHITECTURE_arm64
 #    if defined(__APPLE__)
 #        define CTX_PC (mctx->__ss.__pc)
 #        define CTX_SP (mctx->__ss.__sp)
@@ -110,14 +83,113 @@
 #        define CTX_X(i) (mctx.mc_gpregs.gp_x[i])
 #        define CTX_Q(i) (mctx.mc_fpregs.fp_q[i])
 #    elif defined(__OpenBSD__)
+// https://github.com/openbsd/src/blob/master/sys/arch/arm64/include/signal.h
 #        define CTX_PC (ucontext->sc_elr)
 #        define CTX_SP (ucontext->sc_sp)
 #        define CTX_LR (ucontext->sc_lr)
 #        define CTX_X(i) (ucontext->sc_x[i])
 #        define CTX_Q(i) (ucontext->sc_q[i])
 #    else
-#        error "Unknown platform"
+#        error "unknown platform"
 #    endif
+#elif defined(__NetBSD__)
+// NetBSD always has useful macros for everything don't they?
+// Basically this special path means that for every arch that NetBSD supports
+// it atleast has the macro for _UC_MACHINE defined, thus it will be avoided on the
+// other macro branches!
+// https://github.com/NetBSD/src/blob/trunk/sys/arch/powerpc/include/mcontext.h
+// https://github.com/NetBSD/src/blob/trunk/sys/arch/mips/include/mcontext.h
+#   define CTX_PC (_UC_MACHINE_PC(ucontext))
+#   define CTX_SP (_UC_MACHINE_SP(ucontext))
+#elif defined(ARCHITECTURE_x86_64)
+#    if defined(__APPLE__)
+#        define CTX_RIP (mctx->__ss.__rip)
+#        define CTX_RSP (mctx->__ss.__rsp)
+#    elif defined(__linux__)
+#        define CTX_RIP (mctx.gregs[REG_RIP])
+#        define CTX_RSP (mctx.gregs[REG_RSP])
+#    elif defined(__FreeBSD__)
+#        define CTX_RIP (mctx.mc_rip)
+#        define CTX_RSP (mctx.mc_rsp)
+#    elif defined(__OpenBSD__)
+// https://github.com/openbsd/src/blob/master/sys/arch/x86_64/include/signal.h
+#        define CTX_RIP (ucontext->sc_rip)
+#        define CTX_RSP (ucontext->sc_rsp)
+#    elif defined(__sun__)
+#        define CTX_RIP (mctx.gregs[REG_RIP])
+#        define CTX_RSP (mctx.gregs[REG_RSP])
+#    elif defined(__DragonFly__)
+#        define CTX_RIP (mctx.mc_rip)
+#        define CTX_RSP (mctx.mc_rsp)
+#    else
+#        error "unknown platform"
+#    endif
+#elif defined(ARCHITECTURE_riscv64)
+#   if defined(__FreeBSD__)
+#       define CTX_SEPC (mctx.mc_gpregs.gp_sepc)
+#       define CTX_SP (mctx.mc_gpregs.gp_sp)
+#   elif defined(__linux__)
+#       define CTX_SEPC (mctx.__gregs[REG_PC])
+#       define CTX_SP (mctx.__gregs[REG_SP])
+#   elif defined(__OpenBSD__)
+// https://github.com/openbsd/src/blob/master/sys/arch/riscv64/include/signal.h
+#        define CTX_SEPC (ucontext->sc_sepc)
+#        define CTX_SP (ucontext->sc_sp)
+#    else
+#        error "unknown platform"
+#   endif
+#elif defined(ARCHITECTURE_powerpc64)
+#   if defined(__FreeBSD__)
+#       define CTX_PC (mctx.mc_srr0)
+#       define CTX_SP (mctx.mc_gpr[1])
+#   elif defined(__linux__)
+// https://github.com/lattera/glibc/blob/master/sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h
+#       define CTX_PC (mctx.__regs[REG_PC])
+#       define CTX_SP (mctx.__regs[REG_SP])
+#   elif defined(__OpenBSD__)
+// https://github.com/openbsd/src/blob/master/sys/arch/powerpc64/include/signal.h
+#        define CTX_PC (ucontext->sc_pc)
+#        define CTX_SP (ucontext->sc_reg[1])
+#    else
+#        error "unknown platform"
+#   endif
+#elif defined(ARCHITECTURE_mips64)
+#   if defined(__linux__)
+// https://github.com/lattera/glibc/blob/master/sysdeps/unix/sysv/linux/mips/sys/ucontext.h
+#       define CTX_PC (mctx.__pc)
+#       define CTX_SP (mctx.__gregs[29])
+#   elif defined(__OpenBSD__)
+// https://github.com/openbsd/src/blob/master/sys/arch/mips64/include/signal.h
+#        define CTX_PC (ucontext->sc_pc)
+#        define CTX_SP (ucontext->sc_regs[29])
+#    else
+#        error "unknown platform"
+#   endif
+#elif defined(ARCHITECTURE_loongarch64)
+#   if defined(__linux__)
+// https://github.com/bminor/glibc/blob/04e750e75b73957cf1c791535a3f4319534a52fc/sysdeps/unix/sysv/linux/loongarch/sys/ucontext.h
+#       define CTX_PC (mctx.__pc)
+#       define CTX_SP (mctx.__gregs[LARCH_REG_SP])
+#   elif defined(__OpenBSD__)
+// Literally MIPS64 copypaste?
+// https://github.com/openbsd/src/blob/master/sys/arch/loongson/include/signal.h
+#        define CTX_PC (ucontext->sc_pc)
+#        define CTX_SP (ucontext->sc_regs[29])
+#    else
+#        error "unknown platform"
+#   endif
+#elif defined(ARCHITECTURE_sparc64)
+#   if defined(__linux__)
+// https://github.com/lattera/glibc/blob/master/sysdeps/unix/sysv/linux/mips/sys/ucontext.h
+#       define CTX_PC (mctx.__gregs[1]) //%pc
+#       define CTX_SP (mctx.__gregs[17]) //%o6
+#   elif defined(__OpenBSD__)
+// https://github.com/openbsd/src/blob/master/sys/arch/sparc64/include/signal.h
+#        define CTX_PC (ucontext->sc_pc)
+#        define CTX_SP (ucontext->sc_sp)
+#    else
+#        error "unknown platform"
+#   endif
 #else
 #    error "unimplemented"
 #endif
diff --git a/src/dynarmic/src/dynarmic/common/crypto/aes.cpp b/src/dynarmic/src/dynarmic/common/crypto/aes.cpp
index c72481fbe3..12ebf1ed04 100644
--- a/src/dynarmic/src/dynarmic/common/crypto/aes.cpp
+++ b/src/dynarmic/src/dynarmic/common/crypto/aes.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <array>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Common::Crypto::AES {
 
@@ -133,8 +133,8 @@ static void InverseShiftRows(State& out_state, const State& state) {
 }
 
 static void SubBytes(State& state, const SubstitutionTable& table) {
-    for (size_t i = 0; i < 4; i++) {
-        for (size_t j = 0; j < 4; j++) {
+    for (std::size_t i = 0; i < 4; i++) {
+        for (std::size_t j = 0; j < 4; j++) {
             state[4 * i + j] = table[state[4 * i + j]];
         }
     }
@@ -151,7 +151,7 @@ void EncryptSingleRound(State& out_state, const State& state) {
 }
 
 void MixColumns(State& out_state, const State& state) {
-    for (size_t i = 0; i < out_state.size(); i += 4) {
+    for (std::size_t i = 0; i < out_state.size(); i += 4) {
         const u8 a = state[i];
         const u8 b = state[i + 1];
         const u8 c = state[i + 2];
@@ -167,7 +167,7 @@ void MixColumns(State& out_state, const State& state) {
 }
 
 void InverseMixColumns(State& out_state, const State& state) {
-    for (size_t i = 0; i < out_state.size(); i += 4) {
+    for (std::size_t i = 0; i < out_state.size(); i += 4) {
         const u8 a = state[i];
         const u8 b = state[i + 1];
         const u8 c = state[i + 2];
diff --git a/src/dynarmic/src/dynarmic/common/crypto/aes.h b/src/dynarmic/src/dynarmic/common/crypto/aes.h
index f5d68fe166..395baf674a 100644
--- a/src/dynarmic/src/dynarmic/common/crypto/aes.h
+++ b/src/dynarmic/src/dynarmic/common/crypto/aes.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <array>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Common::Crypto::AES {
 
diff --git a/src/dynarmic/src/dynarmic/common/crypto/crc32.cpp b/src/dynarmic/src/dynarmic/common/crypto/crc32.cpp
index 6b9c129a44..b476b8d8f8 100644
--- a/src/dynarmic/src/dynarmic/common/crypto/crc32.cpp
+++ b/src/dynarmic/src/dynarmic/common/crypto/crc32.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <array>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Common::Crypto::CRC32 {
 
diff --git a/src/dynarmic/src/dynarmic/common/crypto/crc32.h b/src/dynarmic/src/dynarmic/common/crypto/crc32.h
index 391bd8074b..f4057b9793 100644
--- a/src/dynarmic/src/dynarmic/common/crypto/crc32.h
+++ b/src/dynarmic/src/dynarmic/common/crypto/crc32.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,7 +8,7 @@
 
 #pragma once
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Common::Crypto::CRC32 {
 
diff --git a/src/dynarmic/src/dynarmic/common/fp/fpcr.h b/src/dynarmic/src/dynarmic/common/fp/fpcr.h
index 948917bc35..4af365e24c 100644
--- a/src/dynarmic/src/dynarmic/common/fp/fpcr.h
+++ b/src/dynarmic/src/dynarmic/common/fp/fpcr.h
@@ -10,9 +10,9 @@
 
 #include <optional>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/fp/rounding_mode.h"
 
@@ -73,7 +73,7 @@ public:
 
     /// Set rounding mode control field.
     void RMode(FP::RoundingMode rounding_mode) {
-        ASSERT(static_cast<u32>(rounding_mode) <= 0b11 && "FPCR: Invalid rounding mode");
+        assert(static_cast<u32>(rounding_mode) <= 0b11 && "FPCR: Invalid rounding mode");
         value = mcl::bit::set_bits<22, 23>(value, static_cast<u32>(rounding_mode));
     }
 
@@ -93,7 +93,7 @@ public:
     /// Set the stride of a vector when executing AArch32 VFP instructions.
     /// This field has no function in AArch64 state.
     void Stride(size_t stride) {
-        ASSERT(stride >= 1 && stride <= 2 && "FPCR: Invalid stride");
+        assert(stride >= 1 && stride <= 2 && "FPCR: Invalid stride");
         value = mcl::bit::set_bits<20, 21>(value, stride == 1 ? 0b00u : 0b11u);
     }
 
@@ -116,7 +116,7 @@ public:
     /// Sets the length of a vector when executing AArch32 VFP instructions.
     /// This field has no function in AArch64 state.
     void Len(size_t len) {
-        ASSERT(len >= 1 && len <= 8 && "FPCR: Invalid len");
+        assert(len >= 1 && len <= 8 && "FPCR: Invalid len");
         value = mcl::bit::set_bits<16, 18>(value, static_cast<u32>(len - 1));
     }
 
diff --git a/src/dynarmic/src/dynarmic/common/fp/fpsr.h b/src/dynarmic/src/dynarmic/common/fp/fpsr.h
index caa5cb92c7..18dd177111 100644
--- a/src/dynarmic/src/dynarmic/common/fp/fpsr.h
+++ b/src/dynarmic/src/dynarmic/common/fp/fpsr.h
@@ -9,7 +9,7 @@
 #pragma once
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::FP {
 
diff --git a/src/dynarmic/src/dynarmic/common/fp/fused.cpp b/src/dynarmic/src/dynarmic/common/fp/fused.cpp
index a965575a5a..d16eb44791 100644
--- a/src/dynarmic/src/dynarmic/common/fp/fused.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/fused.cpp
@@ -35,7 +35,7 @@ FPUnpacked FusedMulAdd(FPUnpacked addend, FPUnpacked op1, FPUnpacked op2) {
         return std::make_tuple(exponent, value);
     }();
 
-    if (product_value == 0) {
+    if (product_value == u128(0, 0)) {
         return addend;
     }
 
@@ -55,13 +55,13 @@ FPUnpacked FusedMulAdd(FPUnpacked addend, FPUnpacked op1, FPUnpacked op2) {
         }
 
         // addend < product
-        const u128 result = product_value + StickyLogicalShiftRight(addend.mantissa, exp_diff - normalized_point_position);
+        const u128 result = product_value + StickyLogicalShiftRight(u128(addend.mantissa, 0), exp_diff - normalized_point_position);
         return ReduceMantissa(product_sign, product_exponent, result);
     }
 
     // Subtraction
 
-    const u128 addend_long = u128(addend.mantissa) << normalized_point_position;
+    const u128 addend_long = u128(addend.mantissa, 0) << normalized_point_position;
 
     bool result_sign;
     u128 result;
diff --git a/src/dynarmic/src/dynarmic/common/fp/info.h b/src/dynarmic/src/dynarmic/common/fp/info.h
index eebca0fc0c..dae10729ee 100644
--- a/src/dynarmic/src/dynarmic/common/fp/info.h
+++ b/src/dynarmic/src/dynarmic/common/fp/info.h
@@ -9,7 +9,7 @@
 #pragma once
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::FP {
 
diff --git a/src/dynarmic/src/dynarmic/common/fp/mantissa_util.h b/src/dynarmic/src/dynarmic/common/fp/mantissa_util.h
index 43bb5fe604..766fb8f9a4 100644
--- a/src/dynarmic/src/dynarmic/common/fp/mantissa_util.h
+++ b/src/dynarmic/src/dynarmic/common/fp/mantissa_util.h
@@ -9,7 +9,7 @@
 #pragma once
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::FP {
 
diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPConvert.cpp b/src/dynarmic/src/dynarmic/common/fp/op/FPConvert.cpp
index 82803f715d..395ca5c926 100644
--- a/src/dynarmic/src/dynarmic/common/fp/op/FPConvert.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/op/FPConvert.cpp
@@ -9,7 +9,7 @@
 #include "dynarmic/common/fp/op/FPConvert.h"
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/fp/fpcr.h"
 #include "dynarmic/common/fp/fpsr.h"
diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPMulAdd.cpp b/src/dynarmic/src/dynarmic/common/fp/op/FPMulAdd.cpp
index 6990b135f6..1f0b6a8657 100644
--- a/src/dynarmic/src/dynarmic/common/fp/op/FPMulAdd.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/op/FPMulAdd.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,7 +8,7 @@
 
 #include "dynarmic/common/fp/op/FPMulAdd.h"
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/fp/fpcr.h"
 #include "dynarmic/common/fp/fpsr.h"
diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp b/src/dynarmic/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp
index 6b2d43e1ce..c4aa8bcb74 100644
--- a/src/dynarmic/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,7 +8,7 @@
 
 #include "dynarmic/common/fp/op/FPRSqrtEstimate.h"
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/fp/fpcr.h"
 #include "dynarmic/common/fp/fpsr.h"
diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp b/src/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp
index edab4bf147..83d67ebede 100644
--- a/src/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,8 +10,8 @@
 
 #include <tuple>
 
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 
 #include "dynarmic/common/fp/fpcr.h"
 #include "dynarmic/common/fp/fpsr.h"
@@ -55,7 +55,7 @@ FPT FPRecipEstimate(FPT op, FPCR fpcr, FPSR& fpsr) {
             case RoundingMode::TowardsZero:
                 return false;
             default:
-                UNREACHABLE();
+                std::terminate(); //unreachable
             }
         }();
 
@@ -86,7 +86,7 @@ FPT FPRecipEstimate(FPT op, FPCR fpcr, FPSR& fpsr) {
             result_exponent++;
             break;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPRecipExponent.cpp b/src/dynarmic/src/dynarmic/common/fp/op/FPRecipExponent.cpp
index 332870eb8a..b6fc63293f 100644
--- a/src/dynarmic/src/dynarmic/common/fp/op/FPRecipExponent.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/op/FPRecipExponent.cpp
@@ -9,7 +9,7 @@
 #include "dynarmic/common/fp/op/FPRecipExponent.h"
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/fp/fpcr.h"
 #include "dynarmic/common/fp/fpsr.h"
diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp b/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp
index 4bcfcd7c8a..6fea954bf8 100644
--- a/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp
@@ -8,9 +8,9 @@
 
 #include "dynarmic/common/fp/op/FPRoundInt.h"
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/fp/fpcr.h"
 #include "dynarmic/common/fp/fpsr.h"
@@ -26,7 +26,7 @@ namespace Dynarmic::FP {
 
 template<typename FPT>
 u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr) {
-    ASSERT(rounding != RoundingMode::ToOdd);
+    assert(rounding != RoundingMode::ToOdd);
 
     auto [type, sign, value] = FPUnpack<FPT>(op, fpcr, fpsr);
 
@@ -72,7 +72,7 @@ u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr)
         round_up = error > ResidualError::Half || (error == ResidualError::Half && !mcl::bit::most_significant_bit(int_result));
         break;
     case RoundingMode::ToOdd:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     if (round_up) {
diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.h b/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.h
index 1eb2bd8877..83dd9f9447 100644
--- a/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.h
+++ b/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,7 +8,7 @@
 
 #pragma once
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::FP {
 
diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp b/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp
index 2f37797b70..21ffa0139b 100644
--- a/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp
@@ -9,9 +9,9 @@
 #include "dynarmic/common/fp/op/FPToFixed.h"
 
 #include <fmt/format.h>
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/fp/fpcr.h"
 #include "dynarmic/common/fp/fpsr.h"
@@ -25,9 +25,9 @@ namespace Dynarmic::FP {
 
 template<typename FPT>
 u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, RoundingMode rounding, FPSR& fpsr) {
-    ASSERT(rounding != RoundingMode::ToOdd);
-    ASSERT(ibits <= 64);
-    ASSERT(fbits <= ibits);
+    assert(rounding != RoundingMode::ToOdd);
+    assert(ibits <= 64);
+    assert(fbits <= ibits);
 
     auto [type, sign, value] = FPUnpack<FPT>(op, fpcr, fpsr);
 
@@ -70,7 +70,7 @@ u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, Rou
         round_up = error > ResidualError::Half || (error == ResidualError::Half && !mcl::bit::most_significant_bit(int_result));
         break;
     case RoundingMode::ToOdd:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     if (round_up) {
diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.h b/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.h
index 6e19607d51..9d33fa53fb 100644
--- a/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.h
+++ b/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,7 +8,7 @@
 
 #pragma once
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::FP {
 
@@ -17,6 +17,6 @@ class FPSR;
 enum class RoundingMode;
 
 template<typename FPT>
-u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, RoundingMode rounding, FPSR& fpsr);
+u64 FPToFixed(std::size_t ibits, FPT op, std::size_t fbits, bool unsigned_, FPCR fpcr, RoundingMode rounding, FPSR& fpsr);
 
 }  // namespace Dynarmic::FP
diff --git a/src/dynarmic/src/dynarmic/common/fp/process_exception.cpp b/src/dynarmic/src/dynarmic/common/fp/process_exception.cpp
index 33e095de47..108e944f3d 100644
--- a/src/dynarmic/src/dynarmic/common/fp/process_exception.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/process_exception.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,7 +8,7 @@
 
 #include "dynarmic/common/fp/process_exception.h"
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 #include "dynarmic/common/fp/fpcr.h"
 #include "dynarmic/common/fp/fpsr.h"
@@ -18,31 +18,31 @@ namespace Dynarmic::FP {
 void FPProcessException(FPExc exception, FPCR fpcr, FPSR& fpsr) {
     switch (exception) {
     case FPExc::InvalidOp:
-        ASSERT(!fpcr.IOE() && "Raising floating point exceptions unimplemented");
+        assert(!fpcr.IOE() && "Raising floating point exceptions unimplemented");
         fpsr.IOC(true);
         break;
     case FPExc::DivideByZero:
-        ASSERT(!fpcr.DZE() && "Raising floating point exceptions unimplemented");
+        assert(!fpcr.DZE() && "Raising floating point exceptions unimplemented");
         fpsr.DZC(true);
         break;
     case FPExc::Overflow:
-        ASSERT(!fpcr.OFE() && "Raising floating point exceptions unimplemented");
+        assert(!fpcr.OFE() && "Raising floating point exceptions unimplemented");
         fpsr.OFC(true);
         break;
     case FPExc::Underflow:
-        ASSERT(!fpcr.UFE() && "Raising floating point exceptions unimplemented");
+        assert(!fpcr.UFE() && "Raising floating point exceptions unimplemented");
         fpsr.UFC(true);
         break;
     case FPExc::Inexact:
-        ASSERT(!fpcr.IXE() && "Raising floating point exceptions unimplemented");
+        assert(!fpcr.IXE() && "Raising floating point exceptions unimplemented");
         fpsr.IXC(true);
         break;
     case FPExc::InputDenorm:
-        ASSERT(!fpcr.IDE() && "Raising floating point exceptions unimplemented");
+        assert(!fpcr.IDE() && "Raising floating point exceptions unimplemented");
         fpsr.IDC(true);
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
diff --git a/src/dynarmic/src/dynarmic/common/fp/process_nan.cpp b/src/dynarmic/src/dynarmic/common/fp/process_nan.cpp
index 7f47852d98..6ac0de5fe7 100644
--- a/src/dynarmic/src/dynarmic/common/fp/process_nan.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/process_nan.cpp
@@ -10,7 +10,7 @@
 
 #include <optional>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
 
 #include "dynarmic/common/fp/fpcr.h"
@@ -23,7 +23,7 @@ namespace Dynarmic::FP {
 
 template<typename FPT>
 FPT FPProcessNaN(FPType type, FPT op, FPCR fpcr, FPSR& fpsr) {
-    ASSERT(type == FPType::QNaN || type == FPType::SNaN);
+    assert(type == FPType::QNaN || type == FPType::SNaN);
 
     constexpr size_t topfrac = FPInfo<FPT>::explicit_mantissa_width - 1;
 
diff --git a/src/dynarmic/src/dynarmic/common/fp/unpacked.cpp b/src/dynarmic/src/dynarmic/common/fp/unpacked.cpp
index d6bb615cb4..b27eb9b48b 100644
--- a/src/dynarmic/src/dynarmic/common/fp/unpacked.cpp
+++ b/src/dynarmic/src/dynarmic/common/fp/unpacked.cpp
@@ -85,8 +85,8 @@ std::tuple<bool, int, u64, ResidualError> Normalize(FPUnpacked op, int extra_rig
 
 template<typename FPT>
 FPT FPRoundBase(FPUnpacked op, FPCR fpcr, RoundingMode rounding, FPSR& fpsr) {
-    ASSERT(op.mantissa != 0);
-    ASSERT(rounding != RoundingMode::ToNearest_TieAwayFromZero);
+    assert(op.mantissa != 0);
+    assert(rounding != RoundingMode::ToNearest_TieAwayFromZero);
 
     constexpr int minimum_exp = FPInfo<FPT>::exponent_min;
     constexpr size_t E = FPInfo<FPT>::exponent_width;
diff --git a/src/dynarmic/src/dynarmic/common/fp/unpacked.h b/src/dynarmic/src/dynarmic/common/fp/unpacked.h
index effc604fb0..ca842c6e9e 100644
--- a/src/dynarmic/src/dynarmic/common/fp/unpacked.h
+++ b/src/dynarmic/src/dynarmic/common/fp/unpacked.h
@@ -11,7 +11,7 @@
 #include <tuple>
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/fp/fpcr.h"
 
diff --git a/src/dynarmic/src/dynarmic/common/llvm_disassemble.cpp b/src/dynarmic/src/dynarmic/common/llvm_disassemble.cpp
index 068c531f70..f22d460327 100644
--- a/src/dynarmic/src/dynarmic/common/llvm_disassemble.cpp
+++ b/src/dynarmic/src/dynarmic/common/llvm_disassemble.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -15,9 +15,9 @@
 #    include <llvm-c/Target.h>
 #endif
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include <bit>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/llvm_disassemble.h"
 
@@ -37,7 +37,7 @@ std::string DisassembleX64(const void* begin, const void* end) {
     while (pos < end) {
         char buffer[80];
         size_t inst_size = LLVMDisasmInstruction(llvm_ctx, const_cast<u8*>(pos), remaining, reinterpret_cast<u64>(pos), buffer, sizeof(buffer));
-        ASSERT(inst_size);
+        assert(inst_size);
         for (const u8* i = pos; i < pos + inst_size; i++)
             result += fmt::format("{:02x} ", *i);
         for (size_t i = inst_size; i < 10; i++)
diff --git a/src/dynarmic/src/dynarmic/common/llvm_disassemble.h b/src/dynarmic/src/dynarmic/common/llvm_disassemble.h
index 226b742ec5..7fbd9495d1 100644
--- a/src/dynarmic/src/dynarmic/common/llvm_disassemble.h
+++ b/src/dynarmic/src/dynarmic/common/llvm_disassemble.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <string>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Common {
 
diff --git a/src/dynarmic/src/dynarmic/common/math_util.h b/src/dynarmic/src/dynarmic/common/math_util.h
index 8915100ae4..edf2a8229f 100644
--- a/src/dynarmic/src/dynarmic/common/math_util.h
+++ b/src/dynarmic/src/dynarmic/common/math_util.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <utility>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::Common {
 
diff --git a/src/dynarmic/src/dynarmic/common/safe_ops.h b/src/dynarmic/src/dynarmic/common/safe_ops.h
index 5cc8cb5049..f5559336e0 100644
--- a/src/dynarmic/src/dynarmic/common/safe_ops.h
+++ b/src/dynarmic/src/dynarmic/common/safe_ops.h
@@ -11,7 +11,7 @@
 #include <type_traits>
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/u128.h"
 
diff --git a/src/dynarmic/src/dynarmic/common/spin_lock_riscv64.cpp b/src/dynarmic/src/dynarmic/common/spin_lock_riscv64.cpp
new file mode 100644
index 0000000000..bd07b8c915
--- /dev/null
+++ b/src/dynarmic/src/dynarmic/common/spin_lock_riscv64.cpp
@@ -0,0 +1,16 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+#include <mutex>
+
+#include "dynarmic/common/spin_lock.h"
+
+namespace Dynarmic {
+
+void SpinLock::Lock() noexcept {
+}
+
+void SpinLock::Unlock() noexcept {
+}
+
+}  // namespace Dynarmic
diff --git a/src/dynarmic/src/dynarmic/common/u128.cpp b/src/dynarmic/src/dynarmic/common/u128.cpp
index fb7de7a495..3ea6a758aa 100644
--- a/src/dynarmic/src/dynarmic/common/u128.cpp
+++ b/src/dynarmic/src/dynarmic/common/u128.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,7 +8,7 @@
 
 #include "dynarmic/common/u128.h"
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic {
 
@@ -137,7 +137,7 @@ u128 StickyLogicalShiftRight(u128 operand, int amount) {
     }
 
     if (operand.lower != 0 || operand.upper != 0) {
-        return u128(1);
+        return u128(1, 0);
     }
     return {};
 }
diff --git a/src/dynarmic/src/dynarmic/common/u128.h b/src/dynarmic/src/dynarmic/common/u128.h
index 363c8dfec4..1a5686828f 100644
--- a/src/dynarmic/src/dynarmic/common/u128.h
+++ b/src/dynarmic/src/dynarmic/common/u128.h
@@ -12,7 +12,7 @@
 #include <type_traits>
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic {
 
@@ -22,22 +22,13 @@ struct u128 {
     u128(u128&&) = default;
     u128& operator=(const u128&) = default;
     u128& operator=(u128&&) = default;
-
-    u128(u64 lower_, u64 upper_)
-            : lower(lower_), upper(upper_) {}
-
-    template<typename T>
-    /* implicit */ u128(T value)
-            : lower(value), upper(0) {
-        static_assert(std::is_integral_v<T>);
-        static_assert(mcl::bitsizeof<T> <= mcl::bitsizeof<u64>);
-    }
+    explicit u128(u64 lower_, u64 upper_) : lower(lower_), upper(upper_) {}
 
     u64 lower = 0;
     u64 upper = 0;
 
     template<size_t bit_position>
-    bool Bit() const {
+    [[nodiscard]] inline bool Bit() const {
         static_assert(bit_position < 128);
         if constexpr (bit_position < 64) {
             return mcl::bit::get_bit<bit_position>(lower);
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/FPSCR.h b/src/dynarmic/src/dynarmic/frontend/A32/FPSCR.h
index 7e0532ee93..c882add4d6 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/FPSCR.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/FPSCR.h
@@ -11,7 +11,7 @@
 #include <optional>
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/fp/rounding_mode.h"
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/ITState.h b/src/dynarmic/src/dynarmic/frontend/A32/ITState.h
index baabc1ca15..c8ea0f735b 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/ITState.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/ITState.h
@@ -9,7 +9,7 @@
 #pragma once
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/ir/cond.h"
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/PSR.h b/src/dynarmic/src/dynarmic/frontend/A32/PSR.h
index 16ca86aeac..8ea4a39d67 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/PSR.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/PSR.h
@@ -9,7 +9,7 @@
 #pragma once
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/frontend/A32/ITState.h"
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp b/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp
index d9495b881f..2ea9f82492 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,7 +8,7 @@
 
 #include "dynarmic/frontend/A32/a32_ir_emitter.h"
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 #include "dynarmic/frontend/A32/a32_types.h"
 #include "dynarmic/interface/A32/arch_version.h"
@@ -35,7 +35,7 @@ size_t IREmitter::ArchVersion() const {
     case ArchVersion::v8:
         return 8;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 u32 IREmitter::PC() const {
@@ -60,16 +60,16 @@ IR::U32U64 IREmitter::GetExtendedRegister(ExtReg reg) {
         return Inst<IR::U32U64>(Opcode::A32GetExtendedRegister32, IR::Value(reg));
     else if (A32::IsDoubleExtReg(reg))
         return Inst<IR::U32U64>(Opcode::A32GetExtendedRegister64, IR::Value(reg));
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 IR::U128 IREmitter::GetVector(ExtReg reg) {
-    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    assert(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
     return Inst<IR::U128>(Opcode::A32GetVector, IR::Value(reg));
 }
 
 void IREmitter::SetRegister(const Reg reg, const IR::U32& value) {
-    ASSERT(reg != A32::Reg::PC);
+    assert(reg != A32::Reg::PC);
     Inst(Opcode::A32SetRegister, IR::Value(reg), value);
 }
 
@@ -79,12 +79,12 @@ void IREmitter::SetExtendedRegister(const ExtReg reg, const IR::U32U64& value) {
     } else if (A32::IsDoubleExtReg(reg)) {
         Inst(Opcode::A32SetExtendedRegister64, IR::Value(reg), value);
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
 void IREmitter::SetVector(ExtReg reg, const IR::U128& value) {
-    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    assert(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
     Inst(Opcode::A32SetVector, IR::Value(reg), value);
 }
 
@@ -236,7 +236,7 @@ IR::UAny IREmitter::ReadMemory(size_t bitsize, const IR::U32& vaddr, IR::AccType
     case 64:
         return ReadMemory64(vaddr, acc_type);
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 IR::U8 IREmitter::ReadMemory8(const IR::U32& vaddr, IR::AccType acc_type) {
@@ -294,7 +294,7 @@ void IREmitter::WriteMemory(size_t bitsize, const IR::U32& vaddr, const IR::UAny
     case 64:
         return WriteMemory64(vaddr, value, acc_type);
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void IREmitter::WriteMemory8(const IR::U32& vaddr, const IR::U8& value, IR::AccType acc_type) {
@@ -361,7 +361,7 @@ IR::U32 IREmitter::ExclusiveWriteMemory64(const IR::U32& vaddr, const IR::U32& v
 }
 
 void IREmitter::CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1, CoprocReg CRd, CoprocReg CRn, CoprocReg CRm, size_t opc2) {
-    ASSERT(coproc_no <= 15);
+    assert(coproc_no <= 15);
     const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                  static_cast<u8>(two ? 1 : 0),
                                                  static_cast<u8>(opc1),
@@ -373,7 +373,7 @@ void IREmitter::CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1,
 }
 
 void IREmitter::CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, CoprocReg CRn, CoprocReg CRm, size_t opc2, const IR::U32& word) {
-    ASSERT(coproc_no <= 15);
+    assert(coproc_no <= 15);
     const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                  static_cast<u8>(two ? 1 : 0),
                                                  static_cast<u8>(opc1),
@@ -384,7 +384,7 @@ void IREmitter::CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, Copro
 }
 
 void IREmitter::CoprocSendTwoWords(size_t coproc_no, bool two, size_t opc, CoprocReg CRm, const IR::U32& word1, const IR::U32& word2) {
-    ASSERT(coproc_no <= 15);
+    assert(coproc_no <= 15);
     const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                  static_cast<u8>(two ? 1 : 0),
                                                  static_cast<u8>(opc),
@@ -393,7 +393,7 @@ void IREmitter::CoprocSendTwoWords(size_t coproc_no, bool two, size_t opc, Copro
 }
 
 IR::U32 IREmitter::CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, CoprocReg CRn, CoprocReg CRm, size_t opc2) {
-    ASSERT(coproc_no <= 15);
+    assert(coproc_no <= 15);
     const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                  static_cast<u8>(two ? 1 : 0),
                                                  static_cast<u8>(opc1),
@@ -404,7 +404,7 @@ IR::U32 IREmitter::CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, Cop
 }
 
 IR::U64 IREmitter::CoprocGetTwoWords(size_t coproc_no, bool two, size_t opc, CoprocReg CRm) {
-    ASSERT(coproc_no <= 15);
+    assert(coproc_no <= 15);
     const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                  static_cast<u8>(two ? 1 : 0),
                                                  static_cast<u8>(opc),
@@ -413,7 +413,7 @@ IR::U64 IREmitter::CoprocGetTwoWords(size_t coproc_no, bool two, size_t opc, Cop
 }
 
 void IREmitter::CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option) {
-    ASSERT(coproc_no <= 15);
+    assert(coproc_no <= 15);
     const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                  static_cast<u8>(two ? 1 : 0),
                                                  static_cast<u8>(long_transfer ? 1 : 0),
@@ -424,7 +424,7 @@ void IREmitter::CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer,
 }
 
 void IREmitter::CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option) {
-    ASSERT(coproc_no <= 15);
+    assert(coproc_no <= 15);
     const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                  static_cast<u8>(two ? 1 : 0),
                                                  static_cast<u8>(long_transfer ? 1 : 0),
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.h b/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.h
index 8f5e049416..5529c8b720 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <utility>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/frontend/A32/a32_location_descriptor.h"
 #include "dynarmic/ir/ir_emitter.h"
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/a32_location_descriptor.h b/src/dynarmic/src/dynarmic/frontend/A32/a32_location_descriptor.h
index cd850d0087..399a1681f3 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/a32_location_descriptor.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/a32_location_descriptor.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -13,7 +13,7 @@
 #include <tuple>
 
 #include <fmt/format.h>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/frontend/A32/FPSCR.h"
 #include "dynarmic/frontend/A32/ITState.h"
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/a32_types.h b/src/dynarmic/src/dynarmic/frontend/A32/a32_types.h
index 2a0cc25751..30c683eb7b 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/a32_types.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/a32_types.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,8 +10,8 @@
 
 #include <string>
 #include <fmt/format.h>
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 #include "dynarmic/interface/A32/coprocessor_util.h"
 #include "dynarmic/ir/cond.h"
 
@@ -85,7 +85,7 @@ constexpr bool IsQuadExtReg(ExtReg reg) {
 }
 
 inline size_t RegNumber(Reg reg) {
-    ASSERT(reg != Reg::INVALID_REG);
+    assert(reg != Reg::INVALID_REG);
     return size_t(reg);
 }
 
@@ -95,13 +95,13 @@ inline size_t RegNumber(ExtReg reg) {
     } else if (IsDoubleExtReg(reg)) {
         return size_t(reg) - size_t(ExtReg::D0);
     }
-    ASSERT(IsQuadExtReg(reg));
+    assert(IsQuadExtReg(reg));
     return size_t(reg) - size_t(ExtReg::Q0);
 }
 
 inline Reg operator+(Reg reg, size_t number) {
     const size_t new_reg = RegNumber(reg) + number;
-    ASSERT(new_reg <= 15);
+    assert(new_reg <= 15);
 
     return static_cast<Reg>(new_reg);
 }
@@ -109,7 +109,7 @@ inline Reg operator+(Reg reg, size_t number) {
 inline ExtReg operator+(ExtReg reg, size_t number) {
     const auto new_reg = static_cast<ExtReg>(static_cast<size_t>(reg) + number);
 
-    ASSERT((IsSingleExtReg(reg) && IsSingleExtReg(new_reg))
+    assert((IsSingleExtReg(reg) && IsSingleExtReg(new_reg))
            || (IsDoubleExtReg(reg) && IsDoubleExtReg(new_reg))
            || (IsQuadExtReg(reg) && IsQuadExtReg(new_reg)));
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/decoder/arm.h b/src/dynarmic/src/dynarmic/frontend/A32/decoder/arm.h
index bbf128d797..e16adaa7a4 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/decoder/arm.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/decoder/arm.h
@@ -16,7 +16,7 @@
 #include <vector>
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/frontend/decoder/decoder_detail.h"
 #include "dynarmic/frontend/decoder/matcher.h"
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/decoder/asimd.h b/src/dynarmic/src/dynarmic/frontend/A32/decoder/asimd.h
index a16caedd87..4f842a7125 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/decoder/asimd.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/decoder/asimd.h
@@ -16,7 +16,7 @@
 #include <iterator>
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/frontend/decoder/decoder_detail.h"
 #include "dynarmic/frontend/decoder/matcher.h"
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/decoder/thumb16.h b/src/dynarmic/src/dynarmic/frontend/A32/decoder/thumb16.h
index 16b99ba5aa..320c80b377 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/decoder/thumb16.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/decoder/thumb16.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -13,7 +13,7 @@
 #include <optional>
 #include <vector>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/frontend/decoder/decoder_detail.h"
 #include "dynarmic/frontend/decoder/matcher.h"
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/decoder/thumb32.h b/src/dynarmic/src/dynarmic/frontend/A32/decoder/thumb32.h
index 19418de67c..bedd8c3d6f 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/decoder/thumb32.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/decoder/thumb32.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -12,7 +12,7 @@
 #include <optional>
 #include <vector>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/frontend/decoder/decoder_detail.h"
 #include "dynarmic/frontend/decoder/matcher.h"
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/decoder/vfp.h b/src/dynarmic/src/dynarmic/frontend/A32/decoder/vfp.h
index a346304a9a..8dd1efd7d6 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/decoder/vfp.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/decoder/vfp.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -13,7 +13,7 @@
 #include <optional>
 #include <vector>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/frontend/decoder/decoder_detail.h"
 #include "dynarmic/frontend/decoder/matcher.h"
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/a32_translate.h b/src/dynarmic/src/dynarmic/frontend/A32/translate/a32_translate.h
index 33e641fcaf..d39e80a54f 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/a32_translate.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/a32_translate.h
@@ -7,7 +7,7 @@
  */
 #pragma once
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/interface/A32/arch_version.h"
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.cpp
index 82d25f1337..aa510a9be3 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.cpp
@@ -10,8 +10,8 @@
 
 #include <algorithm>
 
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 
 #include "dynarmic/frontend/A32/a32_ir_emitter.h"
 #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h"
@@ -21,7 +21,7 @@
 namespace Dynarmic::A32 {
 
 bool CondCanContinue(const ConditionalState cond_state, const A32::IREmitter& ir) {
-    ASSERT(cond_state != ConditionalState::Break && "Should never happen.");
+    assert(cond_state != ConditionalState::Break && "Should never happen.");
     if (cond_state == ConditionalState::None)
         return true;
 
@@ -32,7 +32,7 @@ bool CondCanContinue(const ConditionalState cond_state, const A32::IREmitter& ir
 }
 
 bool IsConditionPassed(TranslatorVisitor& v, IR::Cond cond) {
-    ASSERT(v.cond_state != ConditionalState::Break && "This should never happen. We requested a break but that wasn't honored.");
+    assert(v.cond_state != ConditionalState::Break && "This should never happen. We requested a break but that wasn't honored.");
 
     if (cond == IR::Cond::NV) {
         // NV conditional is obsolete
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.h b/src/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.h
index ab52dd7198..074e8da662 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -8,7 +8,7 @@
 
 #pragma once
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::IR {
 enum class Cond;
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_crc32.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_crc32.cpp
index 8ee5441013..4ae0a5e6b8 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_crc32.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_crc32.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2019 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -74,7 +77,7 @@ bool CRC32Variant(TranslatorVisitor& v, Cond cond, Imm<2> sz, Reg n, Reg d, Reg
             }
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
 
     v.ir.SetRegister(d, result);
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp
index 7b21e7cce1..b36d85a8d1 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp
@@ -8,7 +8,7 @@
 
 #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h"
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 #include "dynarmic/interface/A32/config.h"
 
@@ -29,7 +29,7 @@ bool TranslatorVisitor::ThumbConditionPassed() {
 
 bool TranslatorVisitor::VFPConditionPassed(Cond cond) {
     if (ir.current_location.TFlag()) {
-        ASSERT(cond == Cond::AL);
+        assert(cond == Cond::AL);
         return true;
     }
     return ArmConditionPassed(cond);
@@ -66,7 +66,7 @@ IR::UAny TranslatorVisitor::I(size_t bitsize, u64 value) {
     case 64:
         return ir.Imm64(value);
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -92,7 +92,7 @@ IR::ResultAndCarry<IR::U32> TranslatorVisitor::EmitImmShift(IR::U32 value, Shift
             return ir.RotateRightExtended(value, carry_in);
         }
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 IR::ResultAndCarry<IR::U32> TranslatorVisitor::EmitRegShift(IR::U32 value, ShiftType type, IR::U8 amount, IR::U1 carry_in) {
@@ -106,7 +106,7 @@ IR::ResultAndCarry<IR::U32> TranslatorVisitor::EmitRegShift(IR::U32 value, Shift
     case ShiftType::ROR:
         return ir.RotateRight(value, amount, carry_in);
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 }  // namespace Dynarmic::A32
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h
index a8888c355f..c7306f18ac 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h
@@ -8,7 +8,7 @@
 
 #pragma once
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
 
 #include "dynarmic/frontend/A32/a32_ir_emitter.h"
@@ -77,7 +77,7 @@ struct TranslatorVisitor final {
                 case 0b11:
                     return mcl::bit::replicate_element<u8, u32>(imm8);
                 }
-                UNREACHABLE();
+                std::terminate(); //unreachable
             }();
             return {imm32, carry_in};
         }
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp
index 8d0f78396a..c7beb96d56 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp
@@ -72,7 +72,7 @@ std::optional<std::tuple<size_t, size_t, size_t>> DecodeType(Imm<4> type, size_t
         }
         return std::tuple<size_t, size_t, size_t>{4, 1, 2};
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 }  // namespace
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp
index 9aa50c6b8c..e2eda87fd4 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp
@@ -8,7 +8,7 @@
 
 #include <vector>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
 
 #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h"
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp
index c5bdb1b551..e2cebd0346 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp
@@ -6,7 +6,7 @@
  * SPDX-License-Identifier: 0BSD
  */
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
 
 #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h"
@@ -110,7 +110,7 @@ bool TranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c, Imm
         return bic();
     }
 
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 }  // namespace Dynarmic::A32
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
index 45455aa444..2c2fec6940 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
@@ -172,7 +172,7 @@ bool TranslatorVisitor::asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool
             return ir.VectorReverseElementsInHalfGroups(esize, reg_m);
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
 
     ir.SetVector(d, result);
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp
index d9cc3b1e64..28d2ad804d 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp
@@ -8,7 +8,7 @@
 
 #include <utility>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
 
 #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h"
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
index e5a4eb537f..8cc977ea20 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
@@ -6,7 +6,7 @@
  * SPDX-License-Identifier: 0BSD
  */
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
 
 #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h"
@@ -130,10 +130,10 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, bool D, size_t imm6, size_t Vd, b
             }
             return v.ir.VectorUnsignedSaturatedNarrow(source_esize, wide_result);
         case Narrowing::SaturateToSigned:
-            ASSERT(signedness == Signedness::Signed);
+            assert(signedness == Signedness::Signed);
             return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
 
     v.ir.SetVector(d, result);
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp
index d7c667aecf..aef0c9d2e9 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp
@@ -95,7 +95,7 @@ bool TranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Re
         return UnpredictableInstruction();
     }
 
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    assert(!(!P && W) && "T form of instruction unimplemented");
     if ((!P || W) && n == t) {
         return UnpredictableInstruction();
     }
@@ -126,7 +126,7 @@ bool TranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Re
 // LDR <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDR <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<5> imm5, ShiftType shift, Reg m) {
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    assert(!(!P && W) && "T form of instruction unimplemented");
     if (m == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -184,7 +184,7 @@ bool TranslatorVisitor::arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, R
         return UnpredictableInstruction();
     }
 
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    assert(!(!P && W) && "T form of instruction unimplemented");
     if ((!P || W) && n == t) {
         return UnpredictableInstruction();
     }
@@ -209,7 +209,7 @@ bool TranslatorVisitor::arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, R
 // LDRB <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDRB <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<5> imm5, ShiftType shift, Reg m) {
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    assert(!(!P && W) && "T form of instruction unimplemented");
     if (t == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -352,7 +352,7 @@ bool TranslatorVisitor::arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n, R
 
 // LDRH <Rt>, [PC, #-/+<imm>]
 bool TranslatorVisitor::arm_LDRH_lit(Cond cond, bool P, bool U, bool W, Reg t, Imm<4> imm8a, Imm<4> imm8b) {
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    assert(!(!P && W) && "T form of instruction unimplemented");
     if (P == W) {
         return UnpredictableInstruction();
     }
@@ -382,7 +382,7 @@ bool TranslatorVisitor::arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, R
         return UnpredictableInstruction();
     }
 
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    assert(!(!P && W) && "T form of instruction unimplemented");
     if ((!P || W) && n == t) {
         return UnpredictableInstruction();
     }
@@ -407,7 +407,7 @@ bool TranslatorVisitor::arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, R
 // LDRH <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDRH <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    assert(!(!P && W) && "T form of instruction unimplemented");
     if (t == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -456,7 +456,7 @@ bool TranslatorVisitor::arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n,
         return UnpredictableInstruction();
     }
 
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    assert(!(!P && W) && "T form of instruction unimplemented");
     if ((!P || W) && n == t) {
         return UnpredictableInstruction();
     }
@@ -481,7 +481,7 @@ bool TranslatorVisitor::arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n,
 // LDRSB <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDRSB <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDRSB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    assert(!(!P && W) && "T form of instruction unimplemented");
     if (t == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -529,7 +529,7 @@ bool TranslatorVisitor::arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n,
         return UnpredictableInstruction();
     }
 
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    assert(!(!P && W) && "T form of instruction unimplemented");
     if ((!P || W) && n == t) {
         return UnpredictableInstruction();
     }
@@ -554,7 +554,7 @@ bool TranslatorVisitor::arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n,
 // LDRSH <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDRSH <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDRSH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    assert(!(!P && W) && "T form of instruction unimplemented");
     if (t == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -870,11 +870,11 @@ bool TranslatorVisitor::arm_LDMIB(Cond cond, bool W, Reg n, RegList list) {
 }
 
 bool TranslatorVisitor::arm_LDM_usr() {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 bool TranslatorVisitor::arm_LDM_eret() {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 static bool STMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::U32 start_address, IR::U32 writeback_address) {
@@ -955,7 +955,7 @@ bool TranslatorVisitor::arm_STMIB(Cond cond, bool W, Reg n, RegList list) {
 }
 
 bool TranslatorVisitor::arm_STM_usr() {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 }  // namespace Dynarmic::A32
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp
index 7a0640598c..2eb045237c 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp
@@ -15,7 +15,7 @@ namespace Dynarmic::A32 {
 // CPS<effect> <iflags>{, #<mode>}
 // CPS #<mode>
 bool TranslatorVisitor::arm_CPS() {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 // MRS<c> <Rd>, <spec_reg>
@@ -34,7 +34,7 @@ bool TranslatorVisitor::arm_MRS(Cond cond, Reg d) {
 
 // MSR<c> <spec_reg>, #<const>
 bool TranslatorVisitor::arm_MSR_imm(Cond cond, unsigned mask, int rotate, Imm<8> imm8) {
-    ASSERT(mask != 0 && "Decode error");
+    assert(mask != 0 && "Decode error");
 
     if (!ArmConditionPassed(cond)) {
         return true;
@@ -107,7 +107,7 @@ bool TranslatorVisitor::arm_MSR_reg(Cond cond, unsigned mask, Reg n) {
 
 // RFE{<amode>} <Rn>{!}
 bool TranslatorVisitor::arm_RFE() {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 // SETEND <endian_specifier>
@@ -118,7 +118,7 @@ bool TranslatorVisitor::arm_SETEND(bool E) {
 
 // SRS{<amode>} SP{!}, #<mode>
 bool TranslatorVisitor::arm_SRS() {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 }  // namespace Dynarmic::A32
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp
index a8c75e22b9..fb63f4590a 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp
@@ -687,7 +687,7 @@ bool TranslatorVisitor::thumb16_NOP() {
 
 // IT{<x>{<y>{<z>}}} <cond>
 bool TranslatorVisitor::thumb16_IT(Imm<8> imm8) {
-    ASSERT((imm8.Bits<0, 3>() != 0b0000) && "Decode Error");
+    assert((imm8.Bits<0, 3>() != 0b0000) && "Decode Error");
     if (imm8.Bits<4, 7>() == 0b1111 || (imm8.Bits<4, 7>() == 0b1110 && mcl::bit::count_ones(imm8.Bits<0, 3>()) != 1)) {
         return UnpredictableInstruction();
     }
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp
index 2f4f2f7298..7d8a4046e2 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -23,7 +23,7 @@ bool TranslatorVisitor::thumb32_TST_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm
 }
 
 bool TranslatorVisitor::thumb32_AND_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    assert(!(d == Reg::PC && S) && "Decode error");
     if ((d == Reg::PC && !S) || n == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -69,7 +69,7 @@ bool TranslatorVisitor::thumb32_MOV_imm(Imm<1> i, bool S, Imm<3> imm3, Reg d, Im
 }
 
 bool TranslatorVisitor::thumb32_ORR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT(n != Reg::PC && "Decode error");
+    assert(n != Reg::PC && "Decode error");
     if (d == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -100,7 +100,7 @@ bool TranslatorVisitor::thumb32_MVN_imm(Imm<1> i, bool S, Imm<3> imm3, Reg d, Im
 }
 
 bool TranslatorVisitor::thumb32_ORN_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT(n != Reg::PC && "Decode error");
+    assert(n != Reg::PC && "Decode error");
     if (d == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -128,7 +128,7 @@ bool TranslatorVisitor::thumb32_TEQ_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm
 }
 
 bool TranslatorVisitor::thumb32_EOR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    assert(!(d == Reg::PC && S) && "Decode error");
     if ((d == Reg::PC && !S) || n == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -156,7 +156,7 @@ bool TranslatorVisitor::thumb32_CMN_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm
 }
 
 bool TranslatorVisitor::thumb32_ADD_imm_1(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    assert(!(d == Reg::PC && S) && "Decode error");
     if ((d == Reg::PC && !S) || n == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -214,7 +214,7 @@ bool TranslatorVisitor::thumb32_CMP_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm
 }
 
 bool TranslatorVisitor::thumb32_SUB_imm_1(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    assert(!(d == Reg::PC && S) && "Decode error");
     if ((d == Reg::PC && !S) || n == Reg::PC) {
         return UnpredictableInstruction();
     }
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp
index 7ea31d40ee..661dafa830 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp
@@ -6,7 +6,7 @@
  * SPDX-License-Identifier: 0BSD
  */
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
 
 #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h"
@@ -17,7 +17,7 @@ namespace Dynarmic::A32 {
 using SaturationFunction = IR::ResultAndOverflow<IR::U32> (IREmitter::*)(const IR::U32&, size_t);
 
 static bool Saturation(TranslatorVisitor& v, bool sh, Reg n, Reg d, Imm<5> shift_amount, size_t saturate_to, SaturationFunction sat_fn) {
-    ASSERT(!(sh && shift_amount == 0) && "Invalid decode");
+    assert(!(sh && shift_amount == 0) && "Invalid decode");
 
     if (d == Reg::PC || n == Reg::PC) {
         return v.UnpredictableInstruction();
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp
index f6b7cb5c87..cf5c39a3d7 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -23,7 +23,7 @@ bool TranslatorVisitor::thumb32_TST_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy
 }
 
 bool TranslatorVisitor::thumb32_AND_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    assert(!(d == Reg::PC && S) && "Decode error");
 
     if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
@@ -67,7 +67,7 @@ bool TranslatorVisitor::thumb32_MOV_reg(bool S, Imm<3> imm3, Reg d, Imm<2> imm2,
 }
 
 bool TranslatorVisitor::thumb32_ORR_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT(n != Reg::PC && "Decode error");
+    assert(n != Reg::PC && "Decode error");
 
     if (d == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
@@ -97,7 +97,7 @@ bool TranslatorVisitor::thumb32_MVN_reg(bool S, Imm<3> imm3, Reg d, Imm<2> imm2,
 }
 
 bool TranslatorVisitor::thumb32_ORN_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT(n != Reg::PC && "Decode error");
+    assert(n != Reg::PC && "Decode error");
 
     if (d == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
@@ -125,7 +125,7 @@ bool TranslatorVisitor::thumb32_TEQ_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy
 }
 
 bool TranslatorVisitor::thumb32_EOR_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    assert(!(d == Reg::PC && S) && "Decode error");
 
     if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
@@ -168,7 +168,7 @@ bool TranslatorVisitor::thumb32_CMN_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy
 }
 
 bool TranslatorVisitor::thumb32_ADD_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    assert(!(d == Reg::PC && S) && "Decode error");
 
     if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
@@ -224,7 +224,7 @@ bool TranslatorVisitor::thumb32_CMP_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy
 }
 
 bool TranslatorVisitor::thumb32_SUB_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    assert(!(d == Reg::PC && S) && "Decode error");
 
     if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/vfp.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/vfp.cpp
index 794d247929..67e29c1237 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/vfp.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/vfp.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -1304,11 +1304,11 @@ bool TranslatorVisitor::vfp_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bo
 // VSTM{mode}<c> <Rn>{!}, <list of double registers>
 bool TranslatorVisitor::vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
     if (!p && !u && !w) {
-        ASSERT(false && "Decode error");
+        assert(false && "Decode error");
     }
 
     if (p && !w) {
-        ASSERT(false && "Decode error");
+        assert(false && "Decode error");
     }
 
     if (p == u && w) {
@@ -1356,11 +1356,11 @@ bool TranslatorVisitor::vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, R
 // VSTM{mode}<c> <Rn>{!}, <list of single registers>
 bool TranslatorVisitor::vfp_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
     if (!p && !u && !w) {
-        ASSERT(false && "Decode error");
+        assert(false && "Decode error");
     }
 
     if (p && !w) {
-        ASSERT(false && "Decode error");
+        assert(false && "Decode error");
     }
 
     if (p == u && w) {
@@ -1399,11 +1399,11 @@ bool TranslatorVisitor::vfp_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, R
 // VLDM{mode}<c> <Rn>{!}, <list of double registers>
 bool TranslatorVisitor::vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
     if (!p && !u && !w) {
-        ASSERT(false && "Decode error");
+        assert(false && "Decode error");
     }
 
     if (p && !w) {
-        ASSERT(false && "Decode error");
+        assert(false && "Decode error");
     }
 
     if (p == u && w) {
@@ -1449,11 +1449,11 @@ bool TranslatorVisitor::vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, R
 // VLDM{mode}<c> <Rn>{!}, <list of single registers>
 bool TranslatorVisitor::vfp_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
     if (!p && !u && !w) {
-        ASSERT(false && "Decode error");
+        assert(false && "Decode error");
     }
 
     if (p && !w) {
-        ASSERT(false && "Decode error");
+        assert(false && "Decode error");
     }
 
     if (p == u && w) {
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_arm.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_arm.cpp
index 5cc9ef3893..128a5d83bd 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_arm.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_arm.cpp
@@ -6,7 +6,7 @@
  * SPDX-License-Identifier: 0BSD
  */
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 #include "dynarmic/frontend/A32/a32_location_descriptor.h"
 #include "dynarmic/frontend/A32/a32_types.h"
@@ -73,7 +73,7 @@ void TranslateArm(IR::Block& block, LocationDescriptor descriptor, TranslateCall
             }
         }
     }
-    ASSERT(block.HasTerminal() && "Terminal has not been set");
+    assert(block.HasTerminal() && "Terminal has not been set");
     block.SetEndLocation(visitor.ir.current_location);
 }
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_thumb.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_thumb.cpp
index 309dd080f9..9477aa7db9 100644
--- a/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_thumb.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_thumb.cpp
@@ -8,7 +8,7 @@
 
 #include <tuple>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
 
 #include "dynarmic/frontend/A32/a32_ir_emitter.h"
@@ -172,7 +172,7 @@ void TranslateThumb(IR::Block& block, LocationDescriptor descriptor, TranslateCa
             }
         }
     }
-    ASSERT(block.HasTerminal() && "Terminal has not been set");
+    assert(block.HasTerminal() && "Terminal has not been set");
     block.SetEndLocation(visitor.ir.current_location);
 }
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.h b/src/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.h
index 18f32cdcc9..74b4babcb4 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.h
+++ b/src/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,8 +10,8 @@
 
 #include <optional>
 
-#include "dynarmic/common/common_types.h"
-#include "dynarmic/common/assert.h"
+#include "common/common_types.h"
+#include <cassert>
 
 #include "dynarmic/frontend/A64/a64_location_descriptor.h"
 #include "dynarmic/frontend/A64/a64_types.h"
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/a64_location_descriptor.h b/src/dynarmic/src/dynarmic/frontend/A64/a64_location_descriptor.h
index a8be0232ca..d0c6a9df3d 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/a64_location_descriptor.h
+++ b/src/dynarmic/src/dynarmic/frontend/A64/a64_location_descriptor.h
@@ -14,7 +14,7 @@
 
 #include <fmt/format.h>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/fp/fpcr.h"
 #include "dynarmic/ir/location_descriptor.h"
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/a64_types.h b/src/dynarmic/src/dynarmic/frontend/A64/a64_types.h
index 8d0f0abe80..8819fd44d6 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/a64_types.h
+++ b/src/dynarmic/src/dynarmic/frontend/A64/a64_types.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -11,8 +11,8 @@
 #include <string>
 
 #include <fmt/format.h>
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 
 #include "dynarmic/ir/cond.h"
 
@@ -114,14 +114,14 @@ constexpr size_t VecNumber(Vec vec) {
 
 inline Reg operator+(Reg reg, size_t number) {
     const size_t new_reg = RegNumber(reg) + number;
-    ASSERT(new_reg <= 31);
+    assert(new_reg <= 31);
 
     return static_cast<Reg>(new_reg);
 }
 
 inline Vec operator+(Vec vec, size_t number) {
     const size_t new_vec = VecNumber(vec) + number;
-    ASSERT(new_vec <= 31);
+    assert(new_vec <= 31);
 
     return static_cast<Vec>(new_vec);
 }
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/decoder/a64.h b/src/dynarmic/src/dynarmic/frontend/A64/decoder/a64.h
index 4ac04731ea..3ea6c70ade 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/decoder/a64.h
+++ b/src/dynarmic/src/dynarmic/frontend/A64/decoder/a64.h
@@ -16,7 +16,7 @@
 #include <vector>
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/frontend/decoder/decoder_detail.h"
 #include "dynarmic/frontend/decoder/matcher.h"
@@ -70,14 +70,15 @@ constexpr DecodeTable<V> GetDecodeTable() {
 
 /// In practice it must always suceed, otherwise something else unrelated would have gone awry
 template<typename V>
-std::reference_wrapper<const Matcher<V>> Decode(u32 instruction) {
+std::optional<std::reference_wrapper<const Matcher<V>>> Decode(u32 instruction) {
     alignas(64) static const auto table = GetDecodeTable<V>();
     const auto& subtable = table[detail::ToFastLookupIndex(instruction)];
     auto iter = std::find_if(subtable.begin(), subtable.end(), [instruction](const auto& matcher) {
         return matcher.Matches(instruction);
     });
-    DEBUG_ASSERT(iter != subtable.end());
-    return std::reference_wrapper<const Matcher<V>>(*iter);
+    return iter != subtable.end()
+        ? std::optional{ std::reference_wrapper<const Matcher<V>>(*iter) }
+        : std::nullopt;
 }
 
 template<typename V>
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.cpp
index 6778d13890..fe1ee90b88 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.cpp
@@ -25,7 +25,11 @@ void Translate(IR::Block& block, LocationDescriptor descriptor, MemoryReadCodeFu
         const u64 pc = visitor.ir.current_location->PC();
         if (const auto instruction = memory_read_code(pc)) {
             auto decoder = Decode<TranslatorVisitor>(*instruction);
-            should_continue = decoder.get().call(visitor, *instruction);
+            if (decoder) {
+                should_continue = decoder->get().call(visitor, *instruction);
+            } else {
+                should_continue = visitor.RaiseException(Exception::UnallocatedEncoding);
+            }
         } else {
             should_continue = visitor.RaiseException(Exception::NoExecuteFault);
         }
@@ -36,7 +40,7 @@ void Translate(IR::Block& block, LocationDescriptor descriptor, MemoryReadCodeFu
     if (single_step && should_continue) {
         visitor.ir.SetTerm(IR::Term::LinkBlock{*visitor.ir.current_location});
     }
-    ASSERT(block.HasTerminal() && "Terminal has not been set");
+    assert(block.HasTerminal() && "Terminal has not been set");
     block.SetEndLocation(*visitor.ir.current_location);
 }
 
@@ -45,13 +49,15 @@ bool TranslateSingleInstruction(IR::Block& block, LocationDescriptor descriptor,
 
     bool should_continue = true;
     auto const decoder = Decode<TranslatorVisitor>(instruction);
-    should_continue = decoder.get().call(visitor, instruction);
+    if (decoder) {
+        should_continue = decoder->get().call(visitor, instruction);
+    } else {
+        should_continue = false;
+    }
 
     visitor.ir.current_location = visitor.ir.current_location->AdvancePC(4);
     block.CycleCount()++;
-
     block.SetEndLocation(*visitor.ir.current_location);
-
     return should_continue;
 }
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.h b/src/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.h
index 125979f8b7..61033eb530 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.h
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.h
@@ -10,7 +10,7 @@
 #include <functional>
 #include <optional>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic {
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp
index 5fa7ac1f98..c89bf108f0 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2018 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -27,7 +30,7 @@ bool TranslatorVisitor::SCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg
         case 64:
             return ir.FPSignedFixedToDouble(intval, fracbits, rounding_mode);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
 
     V_scalar(*fltsize, Vd, fltval);
@@ -54,7 +57,7 @@ bool TranslatorVisitor::UCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg
         case 64:
             return ir.FPUnsignedFixedToDouble(intval, fracbits, rounding_mode);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
 
     V_scalar(*fltsize, Vd, fltval);
@@ -79,7 +82,7 @@ bool TranslatorVisitor::FCVTZS_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec
     } else if (intsize == 64) {
         intval = ir.FPToFixedS64(fltval, fracbits, FP::RoundingMode::TowardsZero);
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     X(intsize, Rd, intval);
@@ -104,7 +107,7 @@ bool TranslatorVisitor::FCVTZU_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec
     } else if (intsize == 64) {
         intval = ir.FPToFixedU64(fltval, fracbits, FP::RoundingMode::TowardsZero);
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     X(intsize, Rd, intval);
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp
index 2f98ebfb13..417ba04e46 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2018 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -23,7 +26,7 @@ bool TranslatorVisitor::SCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
     } else if (*fltsize == 64) {
         fltval = ir.FPSignedFixedToDouble(intval, 0, ir.current_location->FPCR().RMode());
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     V_scalar(*fltsize, Vd, fltval);
@@ -46,7 +49,7 @@ bool TranslatorVisitor::UCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
     } else if (*fltsize == 64) {
         fltval = ir.FPUnsignedFixedToDouble(intval, 0, ir.current_location->FPCR().RMode());
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     V_scalar(*fltsize, Vd, fltval);
@@ -75,7 +78,7 @@ bool TranslatorVisitor::FMOV_float_gen(bool sf, Imm<2> type, Imm<1> rmode_0, Imm
         case 0b11:
             return 16;
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }();
 
@@ -127,7 +130,7 @@ static bool FloaingPointConvertSignedInteger(TranslatorVisitor& v, bool sf, Imm<
     } else if (intsize == 64) {
         intval = v.ir.FPToFixedS64(fltval, 0, rounding_mode);
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     v.X(intsize, Rd, intval);
@@ -149,7 +152,7 @@ static bool FloaingPointConvertUnsignedInteger(TranslatorVisitor& v, bool sf, Im
     } else if (intsize == 64) {
         intval = v.ir.FPToFixedU64(fltval, 0, rounding_mode);
     } else {
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     v.X(intsize, Rd, intval);
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp
index f3ecd7c604..8c48000e92 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp
@@ -19,7 +19,7 @@ bool TranslatorVisitor::UnpredictableInstruction() {
 }
 
 bool TranslatorVisitor::DecodeError() {
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 bool TranslatorVisitor::ReservedValue() {
@@ -72,7 +72,7 @@ IR::UAny TranslatorVisitor::I(size_t bitsize, u64 value) {
     case 64:
         return ir.Imm64(value);
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 IR::UAny TranslatorVisitor::X(size_t bitsize, Reg reg) {
@@ -86,7 +86,7 @@ IR::UAny TranslatorVisitor::X(size_t bitsize, Reg reg) {
     case 64:
         return ir.GetX(reg);
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void TranslatorVisitor::X(size_t bitsize, Reg reg, IR::U32U64 value) {
@@ -98,7 +98,7 @@ void TranslatorVisitor::X(size_t bitsize, Reg reg, IR::U32U64 value) {
         ir.SetX(reg, value);
         return;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 IR::U32U64 TranslatorVisitor::SP(size_t bitsize) {
@@ -108,7 +108,7 @@ IR::U32U64 TranslatorVisitor::SP(size_t bitsize) {
     case 64:
         return ir.GetSP();
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void TranslatorVisitor::SP(size_t bitsize, IR::U32U64 value) {
@@ -120,7 +120,7 @@ void TranslatorVisitor::SP(size_t bitsize, IR::U32U64 value) {
         ir.SetSP(value);
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
@@ -133,7 +133,7 @@ IR::U128 TranslatorVisitor::V(size_t bitsize, Vec vec) {
     case 128:
         return ir.GetQ(vec);
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void TranslatorVisitor::V(size_t bitsize, Vec vec, IR::U128 value) {
@@ -149,7 +149,7 @@ void TranslatorVisitor::V(size_t bitsize, Vec vec, IR::U128 value) {
         ir.SetQ(vec, value);
         return;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 IR::UAnyU128 TranslatorVisitor::V_scalar(size_t bitsize, Vec vec) {
@@ -170,8 +170,8 @@ void TranslatorVisitor::V_scalar(size_t bitsize, Vec vec, IR::UAnyU128 value) {
 }
 
 IR::U128 TranslatorVisitor::Vpart(size_t bitsize, Vec vec, size_t part) {
-    ASSERT(part == 0 || part == 1);
-    ASSERT(bitsize == 64);
+    assert(part == 0 || part == 1);
+    assert(bitsize == 64);
     if (part == 0) {
         return V(64, vec);
     }
@@ -179,33 +179,33 @@ IR::U128 TranslatorVisitor::Vpart(size_t bitsize, Vec vec, size_t part) {
 }
 
 void TranslatorVisitor::Vpart(size_t bitsize, Vec vec, size_t part, IR::U128 value) {
-    ASSERT(part == 0 || part == 1);
+    assert(part == 0 || part == 1);
     if (part == 0) {
-        ASSERT(bitsize == 64);
+        assert(bitsize == 64);
         V(128, vec, ir.VectorZeroExtend(bitsize, value));
     } else {
-        ASSERT(bitsize == 64);
+        assert(bitsize == 64);
         V(128, vec, ir.VectorInterleaveLower(64, V(128, vec), value));
     }
 }
 
 IR::UAny TranslatorVisitor::Vpart_scalar(size_t bitsize, Vec vec, size_t part) {
-    ASSERT(part == 0 || part == 1);
+    assert(part == 0 || part == 1);
     if (part == 0) {
-        ASSERT(bitsize == 8 || bitsize == 16 || bitsize == 32 || bitsize == 64);
+        assert(bitsize == 8 || bitsize == 16 || bitsize == 32 || bitsize == 64);
     } else {
-        ASSERT(bitsize == 64);
+        assert(bitsize == 64);
     }
     return ir.VectorGetElement(bitsize, V(128, vec), part);
 }
 
 void TranslatorVisitor::Vpart_scalar(size_t bitsize, Vec vec, size_t part, IR::UAny value) {
-    ASSERT(part == 0 || part == 1);
+    assert(part == 0 || part == 1);
     if (part == 0) {
-        ASSERT(bitsize == 8 || bitsize == 16 || bitsize == 32 || bitsize == 64);
+        assert(bitsize == 8 || bitsize == 16 || bitsize == 32 || bitsize == 64);
         V(128, vec, ir.ZeroExtendToQuad(value));
     } else {
-        ASSERT(bitsize == 64);
+        assert(bitsize == 64);
         V(128, vec, ir.VectorSetElement(64, V(128, vec), 1, value));
     }
 }
@@ -223,7 +223,7 @@ IR::UAnyU128 TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccTyp
     case 16:
         return ir.ReadMemory128(address, acc_type);
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccType acc_type, IR::UAnyU128 value) {
@@ -244,7 +244,7 @@ void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccType acc_ty
         ir.WriteMemory128(address, value, acc_type);
         return;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 IR::UAnyU128 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::AccType acc_type) {
@@ -260,7 +260,7 @@ IR::UAnyU128 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, I
     case 16:
         return ir.ExclusiveReadMemory128(address, acc_type);
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 IR::U32 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::AccType acc_type, IR::UAnyU128 value) {
@@ -276,7 +276,7 @@ IR::U32 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::Ac
     case 16:
         return ir.ExclusiveWriteMemory128(address, value, acc_type);
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 IR::U32U64 TranslatorVisitor::SignExtend(IR::UAny value, size_t to_size) {
@@ -286,7 +286,7 @@ IR::U32U64 TranslatorVisitor::SignExtend(IR::UAny value, size_t to_size) {
     case 64:
         return ir.SignExtendToLong(value);
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 IR::U32U64 TranslatorVisitor::ZeroExtend(IR::UAny value, size_t to_size) {
@@ -296,7 +296,7 @@ IR::U32U64 TranslatorVisitor::ZeroExtend(IR::UAny value, size_t to_size) {
     case 64:
         return ir.ZeroExtendToLong(value);
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 IR::U32U64 TranslatorVisitor::ShiftReg(size_t bitsize, Reg reg, Imm<2> shift, IR::U8 amount) {
@@ -311,12 +311,12 @@ IR::U32U64 TranslatorVisitor::ShiftReg(size_t bitsize, Reg reg, Imm<2> shift, IR
     case 0b11:
         return ir.RotateRight(result, amount);
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, u8 shift) {
-    ASSERT(shift <= 4);
-    ASSERT(bitsize == 32 || bitsize == 64);
+    assert(shift <= 4);
+    assert(bitsize == 32 || bitsize == 64);
     IR::UAny val = X(bitsize, reg);
     size_t len;
     IR::U32U64 extended;
@@ -374,7 +374,7 @@ IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option,
         break;
     }
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     if (len < bitsize) {
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp
index 0e67e11b4b..a5c24f5176 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2018 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -69,7 +72,7 @@ static bool ExclusiveSharedDecodeAndOperation(TranslatorVisitor& v, bool pair, s
         break;
     }
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     return true;
@@ -172,7 +175,7 @@ static bool OrderedSharedDecodeAndOperation(TranslatorVisitor& v, size_t size, b
         break;
     }
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     return true;
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_multiple_structures.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_multiple_structures.cpp
index 77c57a9659..61ad6422e6 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_multiple_structures.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_multiple_structures.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2018 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -48,7 +51,7 @@ static bool SharedDecodeAndOperation(TranslatorVisitor& v, bool wback, IR::MemOp
     default:
         return v.UnallocatedEncoding();
     }
-    ASSERT(rpt == 1 || selem == 1);
+    assert(rpt == 1 || selem == 1);
 
     if ((size == 0b11 && !Q) && selem != 1) {
         return v.ReservedValue();
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp
index d939c45f2c..befc119567 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2018 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -18,10 +21,10 @@ static bool LoadStoreRegisterImmediate(TranslatorVisitor& v, bool wback, bool po
         signed_ = false;
     } else if (size == 0b11) {
         memop = IR::MemOp::PREFETCH;
-        ASSERT(!opc.Bit<0>());
+        assert(!opc.Bit<0>());
     } else {
         memop = IR::MemOp::LOAD;
-        ASSERT(!(size == 0b10 && opc.Bit<0>() == 1));
+        assert(!(size == 0b10 && opc.Bit<0>() == 1));
         regsize = opc.Bit<0>() ? 32 : 64;
         signed_ = true;
     }
@@ -150,7 +153,7 @@ static bool LoadStoreSIMD(TranslatorVisitor& v, bool wback, bool postindex, size
         }
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     if (wback) {
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp
index 4c81564f7c..20407b1190 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2018 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -63,7 +66,7 @@ bool TranslatorVisitor::STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback,
         break;
     }
     case IR::MemOp::PREFETCH:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     if (wback) {
@@ -133,7 +136,7 @@ bool TranslatorVisitor::STP_LDP_fpsimd(Imm<2> opc, bool not_postindex, bool wbac
         break;
     }
     case IR::MemOp::PREFETCH:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     if (wback) {
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp
index 9791095868..4bf8095e3f 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2018 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -67,7 +70,7 @@ static bool RegSharedDecodeAndOperation(TranslatorVisitor& v, size_t scale, u8 s
         // TODO: Prefetch
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     return true;
@@ -125,7 +128,7 @@ static bool VecSharedDecodeAndOperation(TranslatorVisitor& v, size_t scale, u8 s
         break;
     }
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     return true;
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp
index 6147a54a02..907d1794be 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2018 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -78,7 +81,7 @@ bool FPMinMax(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, MinMaxOpera
         case MinMaxOperation::MinNumeric:
             return v.ir.FPMinNumeric(lhs, rhs);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     };
 
@@ -141,7 +144,7 @@ bool ScalarMinMax(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, Sca
             return v.ir.MinUnsigned(a, b);
 
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     };
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp
index 2afece1c46..166a4a5c2e 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp
@@ -95,7 +95,7 @@ bool TranslatorVisitor::MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<
         return bic();
     }
 
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 bool TranslatorVisitor::FMOV_2(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd) {
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp
index e3b8d7502c..4a00e4f84b 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2018 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -31,7 +34,7 @@ bool FPPairwiseMinMax(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, MinMaxOpera
         case MinMaxOperationSSPW::MinNumeric:
             return v.ir.FPMinNumeric(element1, element2);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }();
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
index 332eb35ebe..02b95b44ea 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
@@ -198,10 +198,10 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn,
             }
             return v.ir.VectorUnsignedSaturatedNarrow(source_esize, wide_result);
         case Narrowing::SaturateToSigned:
-            ASSERT(SignednessSSSBI == SignednessSSSBI::Signed);
+            assert(SignednessSSSBI == SignednessSSSBI::Signed);
             return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
 
     const IR::UAny segment = v.ir.VectorGetElement(esize, result, 0);
@@ -251,7 +251,7 @@ bool ScalarFPConvertWithRound(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Ve
                      : v.ir.FPUnsignedFixedToSingle(operand, fbits, rounding_mode);
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
 
     v.V_scalar(esize, Vd, result);
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp
index ad5b89df3a..e9a1271008 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp
@@ -120,7 +120,7 @@ bool ScalarFPCompareRegister(TranslatorVisitor& v, bool sz, Vec Vm, Vec Vn, Vec
                                         v.ir.FPVectorAbs(esize, operand2));
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
 
     v.V_scalar(datasize, Vd, v.ir.VectorGetElement(esize, result, 0));
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
index 0fc37f538f..31517e7eb5 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2018 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -40,7 +43,7 @@ bool ScalarFPCompareAgainstZero(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, C
             return v.ir.FPVectorGreater(esize, zero, operand);
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
 
     v.V_scalar(datasize, Vd, v.ir.VectorGetElement(esize, result, 0));
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp
index bb0c6fc175..89bf3fdba2 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -73,7 +73,7 @@ bool MultiplyByElementHalfPrecision(TranslatorVisitor& v, Imm<1> L, Imm<1> M, Im
 
         // TODO: Currently we don't implement half-precision paths
         //       for regular multiplication and extended multiplication.
-        ASSERT(extra_behavior != ExtraBehavior::None
+        assert(extra_behavior != ExtraBehavior::None
             && extra_behavior != ExtraBehavior::MultiplyExtended);
         if (extra_behavior == ExtraBehavior::Subtract) {
             operand1 = v.ir.FPNeg(operand1);
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
index 33debd1062..49227afa2a 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
@@ -127,10 +127,10 @@ bool ShiftRightNarrowingSSBI(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> i
             }
             return v.ir.VectorUnsignedSaturatedNarrow(source_esize, wide_result);
         case NarrowingSSBI::SaturateToSigned:
-            ASSERT(SignednessSSBI == SignednessSSBI::Signed);
+            assert(SignednessSSBI == SignednessSSBI::Signed);
             return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
 
     v.Vpart(64, Vd, part, result);
@@ -222,7 +222,7 @@ bool ConvertFloat(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn
                      ? v.ir.FPVectorToSignedFixed(esize, operand, fbits, rounding_mode)
                      : v.ir.FPVectorToUnsignedFixed(esize, operand, fbits, rounding_mode);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
 
     v.V(datasize, Vd, result);
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp
index 1cfc2ced78..c2118c9588 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2018 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -158,7 +161,7 @@ bool FPCompareRegister(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Ve
                                         v.ir.FPVectorAbs(esize, operand2));
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
 
     v.V(datasize, Vd, result);
@@ -195,7 +198,7 @@ bool VectorMinMaxOperationSTS(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm,
             return v.ir.VectorMinUnsigned(esize, operand1, operand2);
 
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }();
 
@@ -272,7 +275,7 @@ bool PairedMinMaxOperationSTS(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm,
             return Q ? v.ir.VectorPairedMinUnsigned(esize, operand1, operand2) : v.ir.VectorPairedMinUnsignedLower(esize, operand1, operand2);
 
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }();
 
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same_extra.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same_extra.cpp
index 91ade93f4b..4a3353125f 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same_extra.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same_extra.cpp
@@ -66,7 +66,7 @@ bool TranslatorVisitor::FCMLA_vec(bool Q, Imm<2> size, Vec Vm, Imm<2> rot, Vec V
     const size_t esize = 8U << size.ZeroExtend();
 
     // TODO: Currently we don't support half-precision floating point
-    ASSERT(esize != 16);
+    assert(esize != 16);
 
     const size_t datasize = Q ? 128 : 64;
     const size_t num_elements = datasize / esize;
@@ -135,7 +135,7 @@ bool TranslatorVisitor::FCADD_vec(bool Q, Imm<2> size, Vec Vm, Imm<1> rot, Vec V
     const size_t esize = 8U << size.ZeroExtend();
 
     // TODO: Currently we don't support half-precision floating point
-    ASSERT(esize != 16);
+    assert(esize != 16);
 
     const size_t datasize = Q ? 128 : 64;
     const size_t num_elements = datasize / esize;
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp
index 80a8e531a7..365713e2b3 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
  * Copyright (c) 2018 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -74,7 +77,7 @@ bool FPCompareAgainstZero(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd,
             return v.ir.FPVectorGreater(esize, zero, operand);
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
 
     v.V(datasize, Vd, result);
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp
index 12ff153dd8..5244c6fbc4 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp
@@ -8,7 +8,7 @@
 
 #include <utility>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 #include "dynarmic/frontend/A64/translate/impl/impl.h"
 
@@ -83,7 +83,7 @@ bool FPMultiplyByElement(TranslatorVisitor& v, bool Q, bool sz, Imm<1> L, Imm<1>
         case ExtraBehaviorSVXIE::Subtract:
             return v.ir.FPVectorMulAdd(esize, operand3, v.ir.FPVectorNeg(esize, operand1), operand2);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
     v.V(datasize, Vd, result);
     return true;
@@ -113,7 +113,7 @@ bool FPMultiplyByElementHalfPrecision(TranslatorVisitor& v, bool Q, Imm<1> L, Im
         case ExtraBehaviorSVXIE::Subtract:
             return v.ir.FPVectorMulAdd(esize, operand3, v.ir.FPVectorNeg(esize, operand1), operand2);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }();
     v.V(datasize, Vd, result);
     return true;
@@ -223,7 +223,7 @@ bool TranslatorVisitor::FCMLA_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4
     const size_t esize = 8U << size.ZeroExtend();
 
     // TODO: We don't support the half-precision floating point variant yet.
-    ASSERT(esize != 16);
+    assert(esize != 16);
 
     const size_t index = [=] {
         if (size == 0b01) {
diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/system.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/system.cpp
index c60fdc3ae0..40ad6e32df 100644
--- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/system.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/system.cpp
@@ -118,7 +118,7 @@ bool TranslatorVisitor::MSR_reg(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, I
     default:
         break;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 bool TranslatorVisitor::MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
@@ -158,7 +158,7 @@ bool TranslatorVisitor::MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3
         X(64, Rt, ir.GetTPIDRRO());
         return true;
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 }  // namespace Dynarmic::A64
diff --git a/src/dynarmic/src/dynarmic/frontend/decoder/decoder_detail.h b/src/dynarmic/src/dynarmic/frontend/decoder/decoder_detail.h
index 3ab360c287..6e9aa27e9b 100644
--- a/src/dynarmic/src/dynarmic/frontend/decoder/decoder_detail.h
+++ b/src/dynarmic/src/dynarmic/frontend/decoder/decoder_detail.h
@@ -12,7 +12,7 @@
 #include <array>
 #include <tuple>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
 #include "dynarmic/mcl/function_info.hpp"
 
@@ -99,9 +99,9 @@ struct detail {
                 shifts[arg_index] = bit_position;
             }
         }
-#if !defined(DYNARMIC_IGNORE_ASSERTS) && !defined(__ANDROID__)
+#if !defined(DYNARMIC_IGNORE_assertS) && !defined(__ANDROID__)
         // Avoids a MSVC ICE, and avoids Android NDK issue.
-        ASSERT(std::all_of(masks.begin(), masks.end(), [](auto m) { return m != 0; }));
+        assert(std::all_of(masks.begin(), masks.end(), [](auto m) { return m != 0; }));
 #endif
         return std::make_tuple(masks, shifts);
     }
diff --git a/src/dynarmic/src/dynarmic/frontend/decoder/matcher.h b/src/dynarmic/src/dynarmic/frontend/decoder/matcher.h
index f7e2884e0c..2eb7dae759 100644
--- a/src/dynarmic/src/dynarmic/frontend/decoder/matcher.h
+++ b/src/dynarmic/src/dynarmic/frontend/decoder/matcher.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <functional>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 namespace Dynarmic::Decoder {
 
@@ -51,7 +51,7 @@ public:
     /// @param v The visitor to use
     /// @param instruction The instruction to decode.
     inline handler_return_type call(Visitor& v, opcode_type instruction) const noexcept {
-        ASSERT(Matches(instruction));
+        assert(Matches(instruction));
         return fn(v, instruction);
     }
 
diff --git a/src/dynarmic/src/dynarmic/frontend/imm.cpp b/src/dynarmic/src/dynarmic/frontend/imm.cpp
index aeb7b5d3f6..51a5d92ebd 100644
--- a/src/dynarmic/src/dynarmic/frontend/imm.cpp
+++ b/src/dynarmic/src/dynarmic/frontend/imm.cpp
@@ -8,9 +8,9 @@
 
 #include "dynarmic/frontend/imm.h"
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic {
 
@@ -64,7 +64,7 @@ u64 AdvSIMDExpandImm(bool op, Imm<4> cmode, Imm<8> imm8) {
             return result;
         }
     }
-    UNREACHABLE();
+    std::terminate(); //unreachable
 }
 
 }  // namespace Dynarmic
diff --git a/src/dynarmic/src/dynarmic/frontend/imm.h b/src/dynarmic/src/dynarmic/frontend/imm.h
index 3a6c10316a..5eb4ca6922 100644
--- a/src/dynarmic/src/dynarmic/frontend/imm.h
+++ b/src/dynarmic/src/dynarmic/frontend/imm.h
@@ -10,9 +10,9 @@
 
 #include <type_traits>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/math_util.h"
 
@@ -29,7 +29,7 @@ public:
 
     explicit Imm(u32 value)
             : value(value) {
-        ASSERT((mcl::bit::get_bits<0, bit_size - 1>(value) == value) && "More bits in value than expected");
+        assert((mcl::bit::get_bits<0, bit_size - 1>(value) == value) && "More bits in value than expected");
     }
 
     template<typename T = u32>
diff --git a/src/dynarmic/src/dynarmic/ir/basic_block.cpp b/src/dynarmic/src/dynarmic/ir/basic_block.cpp
index ac0f03d76a..70f3cfeb4f 100644
--- a/src/dynarmic/src/dynarmic/ir/basic_block.cpp
+++ b/src/dynarmic/src/dynarmic/ir/basic_block.cpp
@@ -14,7 +14,7 @@
 #include <string>
 
 #include <fmt/format.h>
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/frontend/A32/a32_types.h"
 #include "dynarmic/frontend/A64/a64_types.h"
 #include "dynarmic/ir/cond.h"
@@ -49,7 +49,7 @@ Block::iterator Block::PrependNewInst(iterator insertion_point, Opcode opcode, s
         pooled_inst.back().emplace_back(opcode);
         inst = &pooled_inst.back()[pooled_inst.back().size() - 1];
     }
-    DEBUG_ASSERT(args.size() == inst->NumArgs());
+    assert(args.size() == inst->NumArgs());
     std::for_each(args.begin(), args.end(), [&inst, index = size_t(0)](const auto& arg) mutable {
         inst->SetArg(index, arg);
         index++;
@@ -69,7 +69,7 @@ void Block::Reset(LocationDescriptor location_) noexcept {
     terminal = Term::Invalid{};
     cond_failed_cycle_count = 0;
     cycle_count = 0;
-    ASSERT(instructions.size() == 0);
+    assert(instructions.size() == 0);
 }
 
 static std::string TerminalToString(const Terminal& terminal_variant) noexcept {
diff --git a/src/dynarmic/src/dynarmic/ir/basic_block.h b/src/dynarmic/src/dynarmic/ir/basic_block.h
index bbf1319957..90599ef8a3 100644
--- a/src/dynarmic/src/dynarmic/ir/basic_block.h
+++ b/src/dynarmic/src/dynarmic/ir/basic_block.h
@@ -17,7 +17,7 @@
 #include <boost/container/static_vector.hpp>
 #include <boost/container/stable_vector.hpp>
 #include "dynarmic/mcl/intrusive_list.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/ir/location_descriptor.h"
 #include "dynarmic/ir/microinstruction.h"
@@ -119,12 +119,12 @@ public:
     }
     /// Sets the terminal instruction for this basic block.
     inline void SetTerminal(Terminal term) noexcept {
-        ASSERT(!HasTerminal() && "Terminal has already been set.");
+        assert(!HasTerminal() && "Terminal has already been set.");
         terminal = std::move(term);
     }
     /// Replaces the terminal instruction for this basic block.
     inline void ReplaceTerminal(Terminal term) noexcept {
-        ASSERT(HasTerminal() && "Terminal has not been set.");
+        assert(HasTerminal() && "Terminal has not been set.");
         terminal = std::move(term);
     }
     /// Determines whether or not this basic block has a terminal instruction.
diff --git a/src/dynarmic/src/dynarmic/ir/ir_emitter.h b/src/dynarmic/src/dynarmic/ir/ir_emitter.h
index 37f7c18065..25f64e7be7 100644
--- a/src/dynarmic/src/dynarmic/ir/ir_emitter.h
+++ b/src/dynarmic/src/dynarmic/ir/ir_emitter.h
@@ -10,8 +10,8 @@
 
 #include <vector>
 
-#include "dynarmic/common/common_types.h"
-#include "dynarmic/common/assert.h"
+#include "common/common_types.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
 
 #include "dynarmic/ir/opcodes.h"
@@ -118,10 +118,10 @@ public:
             }
             return LeastSignificantWord(value);
         case 64:
-            ASSERT(value.GetType() == Type::U64);
+            assert(value.GetType() == Type::U64);
             return value;
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U32 LeastSignificantWord(const U64& value) {
@@ -189,7 +189,7 @@ public:
     }
 
     U32U64 ConditionalSelect(Cond cond, const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         if (a.GetType() == Type::U32) {
             return Inst<U32>(Opcode::ConditionalSelect32, Value{cond}, a, b);
         } else {
@@ -228,7 +228,7 @@ public:
     }
 
     ResultAndCarry<U32> RotateRight(const U32& value_in, const U8& shift_amount, const U1& carry_in) {
-        const auto result = Inst<U32>(Opcode::RotateRight32, value_in, shift_amount, carry_in);
+        const auto result = Inst<U32>(Opcode::BitRotateRight32, value_in, shift_amount, carry_in);
         const auto carry_out = Inst<U1>(Opcode::GetCarryFromOp, result);
         return {result, carry_out};
     }
@@ -265,14 +265,14 @@ public:
 
     U32U64 RotateRight(const U32U64& value_in, const U8& shift_amount) {
         if (value_in.GetType() == Type::U32) {
-            return Inst<U32>(Opcode::RotateRight32, value_in, shift_amount, Imm1(0));
+            return Inst<U32>(Opcode::BitRotateRight32, value_in, shift_amount, Imm1(0));
         } else {
-            return Inst<U64>(Opcode::RotateRight64, value_in, shift_amount);
+            return Inst<U64>(Opcode::BitRotateRight64, value_in, shift_amount);
         }
     }
 
     U32U64 LogicalShiftLeftMasked(const U32U64& value_in, const U32U64& shift_amount) {
-        ASSERT(value_in.GetType() == shift_amount.GetType());
+        assert(value_in.GetType() == shift_amount.GetType());
         if (value_in.GetType() == Type::U32) {
             return Inst<U32>(Opcode::LogicalShiftLeftMasked32, value_in, shift_amount);
         } else {
@@ -281,7 +281,7 @@ public:
     }
 
     U32U64 LogicalShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount) {
-        ASSERT(value_in.GetType() == shift_amount.GetType());
+        assert(value_in.GetType() == shift_amount.GetType());
         if (value_in.GetType() == Type::U32) {
             return Inst<U32>(Opcode::LogicalShiftRightMasked32, value_in, shift_amount);
         } else {
@@ -290,7 +290,7 @@ public:
     }
 
     U32U64 ArithmeticShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount) {
-        ASSERT(value_in.GetType() == shift_amount.GetType());
+        assert(value_in.GetType() == shift_amount.GetType());
         if (value_in.GetType() == Type::U32) {
             return Inst<U32>(Opcode::ArithmeticShiftRightMasked32, value_in, shift_amount);
         } else {
@@ -299,7 +299,7 @@ public:
     }
 
     U32U64 RotateRightMasked(const U32U64& value_in, const U32U64& shift_amount) {
-        ASSERT(value_in.GetType() == shift_amount.GetType());
+        assert(value_in.GetType() == shift_amount.GetType());
         if (value_in.GetType() == Type::U32) {
             return Inst<U32>(Opcode::RotateRightMasked32, value_in, shift_amount);
         } else {
@@ -308,7 +308,7 @@ public:
     }
 
     U32U64 AddWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         if (a.GetType() == Type::U32) {
             return Inst<U32>(Opcode::Add32, a, b, carry_in);
         } else {
@@ -317,7 +317,7 @@ public:
     }
 
     U32U64 Add(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         if (a.GetType() == Type::U32) {
             return Inst<U32>(Opcode::Add32, a, b, Imm1(0));
         } else {
@@ -326,7 +326,7 @@ public:
     }
 
     U32U64 SubWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         if (a.GetType() == Type::U32) {
             return Inst<U32>(Opcode::Sub32, a, b, carry_in);
         } else {
@@ -335,7 +335,7 @@ public:
     }
 
     U32U64 Sub(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         if (a.GetType() == Type::U32) {
             return Inst<U32>(Opcode::Sub32, a, b, Imm1(1));
         } else {
@@ -376,7 +376,7 @@ public:
     }
 
     U32U64 And(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         if (a.GetType() == Type::U32) {
             return Inst<U32>(Opcode::And32, a, b);
         } else {
@@ -385,7 +385,7 @@ public:
     }
 
     U32U64 AndNot(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         if (a.GetType() == Type::U32) {
             return Inst<U32>(Opcode::AndNot32, a, b);
         } else {
@@ -394,7 +394,7 @@ public:
     }
 
     U32U64 Eor(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         if (a.GetType() == Type::U32) {
             return Inst<U32>(Opcode::Eor32, a, b);
         } else {
@@ -403,7 +403,7 @@ public:
     }
 
     U32U64 Or(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         if (a.GetType() == Type::U32) {
             return Inst<U32>(Opcode::Or32, a, b);
         } else {
@@ -430,7 +430,7 @@ public:
         case Type::U64:
             return U64(a);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -445,7 +445,7 @@ public:
         case Type::U64:
             return Inst<U32>(Opcode::LeastSignificantWord, a);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -472,7 +472,7 @@ public:
         case Type::U64:
             return U64(a);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -487,7 +487,7 @@ public:
         case Type::U64:
             return Inst<U32>(Opcode::LeastSignificantWord, a);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -547,11 +547,11 @@ public:
 
     U32U64 ReplicateBit(const U32U64& a, u8 bit) {
         if (a.GetType() == IR::Type::U32) {
-            ASSERT(bit < 32);
+            assert(bit < 32);
             return Inst<U32>(Opcode::ReplicateBit32, a, Imm8(bit));
         }
 
-        ASSERT(bit < 64);
+        assert(bit < 64);
         return Inst<U64>(Opcode::ReplicateBit64, a, Imm8(bit));
     }
 
@@ -600,21 +600,21 @@ public:
     }
 
     ResultAndOverflow<U32> SignedSaturation(const U32& a, size_t bit_size_to_saturate_to) {
-        ASSERT(bit_size_to_saturate_to >= 1 && bit_size_to_saturate_to <= 32);
+        assert(bit_size_to_saturate_to >= 1 && bit_size_to_saturate_to <= 32);
         const auto result = Inst<U32>(Opcode::SignedSaturation, a, Imm8(static_cast<u8>(bit_size_to_saturate_to)));
         const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
         return {result, overflow};
     }
 
     ResultAndOverflow<U32> UnsignedSaturation(const U32& a, size_t bit_size_to_saturate_to) {
-        ASSERT(bit_size_to_saturate_to <= 31);
+        assert(bit_size_to_saturate_to <= 31);
         const auto result = Inst<U32>(Opcode::UnsignedSaturation, a, Imm8(static_cast<u8>(bit_size_to_saturate_to)));
         const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
         return {result, overflow};
     }
 
     UAny SignedSaturatedAdd(const UAny& a, const UAny& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         const auto result = [&]() -> IR::UAny {
             switch (a.GetType()) {
             case IR::Type::U8:
@@ -633,7 +633,7 @@ public:
     }
 
     UAny SignedSaturatedDoublingMultiplyReturnHigh(const UAny& a, const UAny& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         const auto result = [&]() -> IR::UAny {
             switch (a.GetType()) {
             case IR::Type::U16:
@@ -641,14 +641,14 @@ public:
             case IR::Type::U32:
                 return Inst<U32>(Opcode::SignedSaturatedDoublingMultiplyReturnHigh32, a, b);
             default:
-                UNREACHABLE();
+                std::terminate(); //unreachable
             }
         }();
         return result;
     }
 
     UAny SignedSaturatedSub(const UAny& a, const UAny& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         const auto result = [&]() -> IR::UAny {
             switch (a.GetType()) {
             case IR::Type::U8:
@@ -667,7 +667,7 @@ public:
     }
 
     UAny UnsignedSaturatedAdd(const UAny& a, const UAny& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         const auto result = [&]() -> IR::UAny {
             switch (a.GetType()) {
             case IR::Type::U8:
@@ -686,7 +686,7 @@ public:
     }
 
     UAny UnsignedSaturatedSub(const UAny& a, const UAny& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
         const auto result = [&]() -> IR::UAny {
             switch (a.GetType()) {
             case IR::Type::U8:
@@ -715,7 +715,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedAdd64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -730,7 +730,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedSub64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -745,7 +745,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -760,7 +760,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorUnsignedSaturatedSub64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -989,7 +989,7 @@ public:
     }
 
     UAny VectorGetElement(size_t esize, const U128& a, size_t index) {
-        ASSERT(esize * index < 128 && "Invalid index");
+        assert(esize * index < 128 && "Invalid index");
         switch (esize) {
         case 8:
             return Inst<U8>(Opcode::VectorGetElement8, a, Imm8(static_cast<u8>(index)));
@@ -1000,12 +1000,12 @@ public:
         case 64:
             return Inst<U64>(Opcode::VectorGetElement64, a, Imm8(static_cast<u8>(index)));
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U128 VectorSetElement(size_t esize, const U128& a, size_t index, const IR::UAny& elem) {
-        ASSERT(esize * index < 128 && "Invalid index");
+        assert(esize * index < 128 && "Invalid index");
         switch (esize) {
         case 8:
             return Inst<U128>(Opcode::VectorSetElement8, a, Imm8(static_cast<u8>(index)), elem);
@@ -1016,7 +1016,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSetElement64, a, Imm8(static_cast<u8>(index)), elem);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1031,7 +1031,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorAbs64, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorAdd(size_t esize, const U128& a, const U128& b) {
@@ -1045,7 +1045,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorAdd64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorAnd(const U128& a, const U128& b) {
@@ -1067,7 +1067,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorArithmeticShiftRight64, a, Imm8(shift_amount));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorArithmeticVShift(size_t esize, const U128& a, const U128& b) {
@@ -1081,7 +1081,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorArithmeticVShift64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorBroadcastLower(size_t esize, const UAny& a) {
@@ -1093,7 +1093,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorBroadcastLower32, U32(a));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorBroadcast(size_t esize, const UAny& a) {
@@ -1107,11 +1107,11 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorBroadcast64, U64(a));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorBroadcastElementLower(size_t esize, const U128& a, size_t index) {
-        ASSERT(esize * index < 128 && "Invalid index");
+        assert(esize * index < 128 && "Invalid index");
         switch (esize) {
         case 8:
             return Inst<U128>(Opcode::VectorBroadcastElementLower8, a, u8(index));
@@ -1120,11 +1120,11 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorBroadcastElementLower32, a, u8(index));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorBroadcastElement(size_t esize, const U128& a, size_t index) {
-        ASSERT(esize * index < 128 && "Invalid index");
+        assert(esize * index < 128 && "Invalid index");
         switch (esize) {
         case 8:
             return Inst<U128>(Opcode::VectorBroadcastElement8, a, u8(index));
@@ -1135,7 +1135,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorBroadcastElement64, a, u8(index));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorCountLeadingZeros(size_t esize, const U128& a) {
@@ -1147,7 +1147,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorCountLeadingZeros32, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorDeinterleaveEven(size_t esize, const U128& a, const U128& b) {
@@ -1161,7 +1161,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorDeinterleaveEven64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorDeinterleaveOdd(size_t esize, const U128& a, const U128& b) {
@@ -1175,7 +1175,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorDeinterleaveOdd64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorDeinterleaveEvenLower(size_t esize, const U128& a, const U128& b) {
@@ -1187,7 +1187,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorDeinterleaveEvenLower32, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorDeinterleaveOddLower(size_t esize, const U128& a, const U128& b) {
@@ -1199,7 +1199,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorDeinterleaveOddLower32, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorEor(const U128& a, const U128& b) {
@@ -1219,16 +1219,16 @@ public:
         case 128:
             return Inst<U128>(Opcode::VectorEqual128, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorExtract(const U128& a, const U128& b, size_t position) {
-        ASSERT(position <= 128);
+        assert(position <= 128);
         return Inst<U128>(Opcode::VectorExtract, a, b, Imm8(static_cast<u8>(position)));
     }
 
     U128 VectorExtractLower(const U128& a, const U128& b, size_t position) {
-        ASSERT(position <= 64);
+        assert(position <= 64);
         return Inst<U128>(Opcode::VectorExtractLower, a, b, Imm8(static_cast<u8>(position)));
     }
 
@@ -1243,7 +1243,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorGreaterS64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorGreaterEqualSigned(size_t esize, const U128& a, const U128& b) {
@@ -1267,7 +1267,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorHalvingAddS32, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorHalvingAddUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1279,7 +1279,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorHalvingAddU32, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorHalvingSubSigned(size_t esize, const U128& a, const U128& b) {
@@ -1291,7 +1291,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorHalvingSubS32, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorHalvingSubUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1303,7 +1303,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorHalvingSubU32, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorInterleaveLower(size_t esize, const U128& a, const U128& b) {
@@ -1317,7 +1317,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorInterleaveLower64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorInterleaveUpper(size_t esize, const U128& a, const U128& b) {
@@ -1331,7 +1331,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorInterleaveUpper64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorLessEqualSigned(size_t esize, const U128& a, const U128& b) {
@@ -1361,7 +1361,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorLogicalShiftLeft64, a, Imm8(shift_amount));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount) {
@@ -1375,7 +1375,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorLogicalShiftRight64, a, Imm8(shift_amount));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorLogicalVShift(size_t esize, const U128& a, const U128& b) {
@@ -1389,7 +1389,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorLogicalVShift64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorMaxSigned(size_t esize, const U128& a, const U128& b) {
@@ -1403,7 +1403,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorMaxS64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorMaxUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1417,7 +1417,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorMaxU64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorMinSigned(size_t esize, const U128& a, const U128& b) {
@@ -1431,7 +1431,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorMinS64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorMinUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1445,7 +1445,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorMinU64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorMultiply(size_t esize, const U128& a, const U128& b) {
@@ -1459,7 +1459,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorMultiply64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorMultiplySignedWiden(size_t esize, const U128& a, const U128& b) {
@@ -1471,7 +1471,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorMultiplySignedWiden32, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorMultiplyUnsignedWiden(size_t esize, const U128& a, const U128& b) {
@@ -1483,7 +1483,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorMultiplyUnsignedWiden32, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorNarrow(size_t original_esize, const U128& a) {
@@ -1495,7 +1495,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorNarrow64, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorNot(const U128& a) {
@@ -1517,7 +1517,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorPairedAdd64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorPairedAddLower(size_t esize, const U128& a, const U128& b) {
@@ -1529,7 +1529,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedAddLower32, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorPairedAddSignedWiden(size_t original_esize, const U128& a) {
@@ -1541,7 +1541,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedAddSignedWiden32, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorPairedAddUnsignedWiden(size_t original_esize, const U128& a) {
@@ -1553,7 +1553,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedAddUnsignedWiden32, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorPairedMaxSigned(size_t esize, const U128& a, const U128& b) {
@@ -1565,7 +1565,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMaxS32, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1578,7 +1578,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMaxU32, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1591,7 +1591,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMinS32, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1604,7 +1604,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMinU32, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1617,7 +1617,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMaxLowerS32, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1630,7 +1630,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMaxLowerU32, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1643,7 +1643,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMinLowerS32, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1656,7 +1656,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorPairedMinLowerU32, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1671,7 +1671,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorPolynomialMultiplyLong64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1688,7 +1688,7 @@ public:
         case 8:
             return Inst<U128>(Opcode::VectorReverseElementsInHalfGroups8, a);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1699,7 +1699,7 @@ public:
         case 16:
             return Inst<U128>(Opcode::VectorReverseElementsInWordGroups16, a);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1712,7 +1712,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorReverseElementsInLongGroups32, a);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1728,11 +1728,11 @@ public:
             return Inst<U128>(Opcode::VectorReduceAdd64, a);
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorRotateLeft(size_t esize, const U128& a, u8 amount) {
-        ASSERT(amount < esize);
+        assert(amount < esize);
 
         if (amount == 0) {
             return a;
@@ -1743,7 +1743,7 @@ public:
     }
 
     U128 VectorRotateRight(size_t esize, const U128& a, u8 amount) {
-        ASSERT(amount < esize);
+        assert(amount < esize);
 
         if (amount == 0) {
             return a;
@@ -1754,7 +1754,7 @@ public:
     }
 
     U128 VectorRotateWholeVectorRight(const U128& a, u8 amount) {
-        ASSERT(amount % 32 == 0);
+        assert(amount % 32 == 0);
         return Inst<U128>(Opcode::VectorRotateWholeVectorRight, a, Imm8(amount));
     }
 
@@ -1768,7 +1768,7 @@ public:
             return Inst<U128>(Opcode::VectorRoundingHalvingAddS32, a, b);
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorRoundingHalvingAddUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1781,7 +1781,7 @@ public:
             return Inst<U128>(Opcode::VectorRoundingHalvingAddU32, a, b);
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorRoundingShiftLeftSigned(size_t esize, const U128& a, const U128& b) {
@@ -1796,7 +1796,7 @@ public:
             return Inst<U128>(Opcode::VectorRoundingShiftLeftS64, a, b);
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorRoundingShiftLeftUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1811,7 +1811,7 @@ public:
             return Inst<U128>(Opcode::VectorRoundingShiftLeftU64, a, b);
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorSignExtend(size_t original_esize, const U128& a) {
@@ -1825,7 +1825,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignExtend64, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorSignedAbsoluteDifference(size_t esize, const U128& a, const U128& b) {
@@ -1837,7 +1837,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorSignedAbsoluteDifference32, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     UpperAndLower VectorSignedMultiply(size_t esize, const U128& a, const U128& b) {
@@ -1848,7 +1848,7 @@ public:
             case 32:
                 return Inst(Opcode::VectorSignedMultiply32, a, b);
             }
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }();
 
         return {
@@ -1868,7 +1868,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedAbs64, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorSignedSaturatedAccumulateUnsigned(size_t esize, const U128& a, const U128& b) {
@@ -1882,7 +1882,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedAccumulateUnsigned64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorSignedSaturatedDoublingMultiplyHigh(size_t esize, const U128& a, const U128& b) {
@@ -1892,7 +1892,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorSignedSaturatedDoublingMultiplyHigh32, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1903,7 +1903,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorSignedSaturatedDoublingMultiplyHighRounding32, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -1914,7 +1914,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorSignedSaturatedDoublingMultiplyLong32, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorSignedSaturatedNarrowToSigned(size_t original_esize, const U128& a) {
@@ -1926,7 +1926,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedNarrowToSigned64, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorSignedSaturatedNarrowToUnsigned(size_t original_esize, const U128& a) {
@@ -1938,7 +1938,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedNarrowToUnsigned64, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorSignedSaturatedNeg(size_t esize, const U128& a) {
@@ -1952,7 +1952,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedNeg64, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorSignedSaturatedShiftLeft(size_t esize, const U128& a, const U128& b) {
@@ -1966,11 +1966,11 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedShiftLeft64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorSignedSaturatedShiftLeftUnsigned(size_t esize, const U128& a, u8 shift_amount) {
-        ASSERT(shift_amount < esize);
+        assert(shift_amount < esize);
         switch (esize) {
         case 8:
             return Inst<U128>(Opcode::VectorSignedSaturatedShiftLeftUnsigned8, a, Imm8(shift_amount));
@@ -1981,7 +1981,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSignedSaturatedShiftLeftUnsigned64, a, Imm8(shift_amount));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorSub(size_t esize, const U128& a, const U128& b) {
@@ -1995,28 +1995,28 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorSub64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     Table VectorTable(std::vector<U64> values) {
-        ASSERT(values.size() >= 1 && values.size() <= 4);
+        assert(values.size() >= 1 && values.size() <= 4);
         values.resize(4);
         return Inst<Table>(Opcode::VectorTable, values[0], values[1], values[2], values[3]);
     }
 
     Table VectorTable(std::vector<U128> values) {
-        ASSERT(values.size() >= 1 && values.size() <= 4);
+        assert(values.size() >= 1 && values.size() <= 4);
         values.resize(4);
         return Inst<Table>(Opcode::VectorTable, values[0], values[1], values[2], values[3]);
     }
 
     U64 VectorTableLookup(const U64& defaults, const Table& table, const U64& indices) {
-        ASSERT(table.GetInst()->GetArg(0).GetType() == Type::U64);
+        assert(table.GetInst()->GetArg(0).GetType() == Type::U64);
         return Inst<U64>(Opcode::VectorTableLookup64, defaults, table, indices);
     }
 
     U128 VectorTableLookup(const U128& defaults, const Table& table, const U128& indices) {
-        ASSERT(table.GetInst()->GetArg(0).GetType() == Type::U128);
+        assert(table.GetInst()->GetArg(0).GetType() == Type::U128);
         return Inst<U128>(Opcode::VectorTableLookup128, defaults, table, indices);
     }
 
@@ -2031,7 +2031,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorTranspose64, a, b, Imm1(part));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorUnsignedAbsoluteDifference(size_t esize, const U128& a, const U128& b) {
@@ -2043,7 +2043,7 @@ public:
         case 32:
             return Inst<U128>(Opcode::VectorUnsignedAbsoluteDifference32, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorUnsignedRecipEstimate(const U128& a) {
@@ -2065,7 +2065,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorUnsignedSaturatedAccumulateSigned64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorUnsignedSaturatedNarrow(size_t esize, const U128& a) {
@@ -2077,7 +2077,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorUnsignedSaturatedNarrow64, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorUnsignedSaturatedShiftLeft(size_t esize, const U128& a, const U128& b) {
@@ -2091,7 +2091,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorUnsignedSaturatedShiftLeft64, a, b);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorZeroExtend(size_t original_esize, const U128& a) {
@@ -2105,7 +2105,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::VectorZeroExtend64, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 VectorZeroUpper(const U128& a) {
@@ -2125,12 +2125,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPAbs64, a);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U32U64 FPAdd(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         switch (a.GetType()) {
         case Type::U32:
@@ -2138,12 +2138,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPAdd64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     NZCV FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         const IR::U1 exc_on_qnan_imm = Imm1(exc_on_qnan);
 
@@ -2153,12 +2153,12 @@ public:
         case Type::U64:
             return Inst<NZCV>(Opcode::FPCompare64, a, b, exc_on_qnan_imm);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U32U64 FPDiv(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         switch (a.GetType()) {
         case Type::U32:
@@ -2166,12 +2166,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPDiv64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U32U64 FPMax(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         switch (a.GetType()) {
         case Type::U32:
@@ -2179,12 +2179,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMax64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U32U64 FPMaxNumeric(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         switch (a.GetType()) {
         case Type::U32:
@@ -2192,12 +2192,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMaxNumeric64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U32U64 FPMin(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         switch (a.GetType()) {
         case Type::U32:
@@ -2205,12 +2205,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMin64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U32U64 FPMinNumeric(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         switch (a.GetType()) {
         case Type::U32:
@@ -2218,12 +2218,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMinNumeric64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U32U64 FPMul(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         switch (a.GetType()) {
         case Type::U32:
@@ -2231,12 +2231,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMul64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U16U32U64 FPMulAdd(const U16U32U64& a, const U16U32U64& b, const U16U32U64& c) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         switch (a.GetType()) {
         case Type::U16:
@@ -2246,12 +2246,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMulAdd64, a, b, c);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U16U32U64 FPMulSub(const U16U32U64& a, const U16U32U64& b, const U16U32U64& c) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         switch (a.GetType()) {
         case Type::U16:
@@ -2261,12 +2261,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMulSub64, a, b, c);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U32U64 FPMulX(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         switch (a.GetType()) {
         case Type::U32:
@@ -2274,7 +2274,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPMulX64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -2287,7 +2287,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPNeg64, a);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -2300,7 +2300,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPRecipEstimate64, a);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -2313,12 +2313,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPRecipExponent64, a);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U16U32U64 FPRecipStepFused(const U16U32U64& a, const U16U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         switch (a.GetType()) {
         case Type::U16:
@@ -2328,7 +2328,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPRecipStepFused64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -2344,7 +2344,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPRoundInt64, a, rounding_value, exact_imm);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -2357,12 +2357,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPRSqrtEstimate64, a);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U16U32U64 FPRSqrtStepFused(const U16U32U64& a, const U16U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         switch (a.GetType()) {
         case Type::U16:
@@ -2372,7 +2372,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPRSqrtStepFused64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -2383,12 +2383,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPSqrt64, a);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U32U64 FPSub(const U32U64& a, const U32U64& b) {
-        ASSERT(a.GetType() == b.GetType());
+        assert(a.GetType() == b.GetType());
 
         switch (a.GetType()) {
         case Type::U32:
@@ -2396,7 +2396,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPSub64, a, b);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -2425,7 +2425,7 @@ public:
     }
 
     U16 FPToFixedS16(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) {
-        ASSERT(fbits <= 16);
+        assert(fbits <= 16);
 
         const U8 fbits_imm = Imm8(static_cast<u8>(fbits));
         const U8 rounding_imm = Imm8(static_cast<u8>(rounding));
@@ -2438,12 +2438,12 @@ public:
         case Type::U64:
             return Inst<U16>(Opcode::FPDoubleToFixedS16, a, fbits_imm, rounding_imm);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U32 FPToFixedS32(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) {
-        ASSERT(fbits <= 32);
+        assert(fbits <= 32);
 
         const U8 fbits_imm = Imm8(static_cast<u8>(fbits));
         const U8 rounding_imm = Imm8(static_cast<u8>(rounding));
@@ -2456,12 +2456,12 @@ public:
         case Type::U64:
             return Inst<U32>(Opcode::FPDoubleToFixedS32, a, fbits_imm, rounding_imm);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U64 FPToFixedS64(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) {
-        ASSERT(fbits <= 64);
+        assert(fbits <= 64);
 
         const U8 fbits_imm = Imm8(static_cast<u8>(fbits));
         const U8 rounding_imm = Imm8(static_cast<u8>(rounding));
@@ -2474,12 +2474,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPDoubleToFixedS64, a, fbits_imm, rounding_imm);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U16 FPToFixedU16(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) {
-        ASSERT(fbits <= 16);
+        assert(fbits <= 16);
 
         const U8 fbits_imm = Imm8(static_cast<u8>(fbits));
         const U8 rounding_imm = Imm8(static_cast<u8>(rounding));
@@ -2492,12 +2492,12 @@ public:
         case Type::U64:
             return Inst<U16>(Opcode::FPDoubleToFixedU16, a, fbits_imm, rounding_imm);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U32 FPToFixedU32(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) {
-        ASSERT(fbits <= 32);
+        assert(fbits <= 32);
 
         const U8 fbits_imm = Imm8(static_cast<u8>(fbits));
         const U8 rounding_imm = Imm8(static_cast<u8>(rounding));
@@ -2510,12 +2510,12 @@ public:
         case Type::U64:
             return Inst<U32>(Opcode::FPDoubleToFixedU32, a, fbits_imm, rounding_imm);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U64 FPToFixedU64(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) {
-        ASSERT(fbits <= 64);
+        assert(fbits <= 64);
 
         const U8 fbits_imm = Imm8(static_cast<u8>(fbits));
         const U8 rounding_imm = Imm8(static_cast<u8>(rounding));
@@ -2528,12 +2528,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPDoubleToFixedU64, a, fbits_imm, rounding_imm);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U32 FPSignedFixedToSingle(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) {
-        ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64)));
+        assert(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64)));
 
         const IR::U8 fbits_imm = Imm8(static_cast<u8>(fbits));
         const IR::U8 rounding_imm = Imm8(static_cast<u8>(rounding));
@@ -2546,12 +2546,12 @@ public:
         case Type::U64:
             return Inst<U32>(Opcode::FPFixedS64ToSingle, a, fbits_imm, rounding_imm);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U32 FPUnsignedFixedToSingle(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) {
-        ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64)));
+        assert(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64)));
 
         const IR::U8 fbits_imm = Imm8(static_cast<u8>(fbits));
         const IR::U8 rounding_imm = Imm8(static_cast<u8>(rounding));
@@ -2564,12 +2564,12 @@ public:
         case Type::U64:
             return Inst<U32>(Opcode::FPFixedU64ToSingle, a, fbits_imm, rounding_imm);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U64 FPSignedFixedToDouble(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) {
-        ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64)));
+        assert(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64)));
 
         const IR::U8 fbits_imm = Imm8(static_cast<u8>(fbits));
         const IR::U8 rounding_imm = Imm8(static_cast<u8>(rounding));
@@ -2582,12 +2582,12 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPFixedS64ToDouble, a, fbits_imm, rounding_imm);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
     U64 FPUnsignedFixedToDouble(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) {
-        ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64)));
+        assert(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64)));
 
         const IR::U8 fbits_imm = Imm8(static_cast<u8>(fbits));
         const IR::U8 rounding_imm = Imm8(static_cast<u8>(rounding));
@@ -2600,7 +2600,7 @@ public:
         case Type::U64:
             return Inst<U64>(Opcode::FPFixedU64ToDouble, a, fbits_imm, rounding_imm);
         default:
-            UNREACHABLE();
+            std::terminate(); //unreachable
         }
     }
 
@@ -2613,7 +2613,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorAbs64, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2623,7 +2623,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorAdd64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorDiv(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2633,7 +2633,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorDiv64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorEqual(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2645,34 +2645,34 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorEqual64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorFromHalf(size_t esize, const U128& a, FP::RoundingMode rounding, bool fpcr_controlled = true) {
-        ASSERT(esize == 32);
+        assert(esize == 32);
         return Inst<U128>(Opcode::FPVectorFromHalf32, a, Imm8(static_cast<u8>(rounding)), Imm1(fpcr_controlled));
     }
 
     U128 FPVectorFromSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) {
-        ASSERT(fbits <= esize);
+        assert(fbits <= esize);
         switch (esize) {
         case 32:
             return Inst<U128>(Opcode::FPVectorFromSignedFixed32, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)), Imm1(fpcr_controlled));
         case 64:
             return Inst<U128>(Opcode::FPVectorFromSignedFixed64, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)), Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorFromUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) {
-        ASSERT(fbits <= esize);
+        assert(fbits <= esize);
         switch (esize) {
         case 32:
             return Inst<U128>(Opcode::FPVectorFromUnsignedFixed32, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)), Imm1(fpcr_controlled));
         case 64:
             return Inst<U128>(Opcode::FPVectorFromUnsignedFixed64, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)), Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorGreater(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2682,7 +2682,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorGreater64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorGreaterEqual(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2692,7 +2692,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorGreaterEqual64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorMax(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2702,7 +2702,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMax64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorMaxNumeric(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2712,7 +2712,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMaxNumeric64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorMin(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2722,7 +2722,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMin64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorMinNumeric(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2732,7 +2732,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMinNumeric64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorMul(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2742,7 +2742,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMul64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorMulAdd(size_t esize, const U128& a, const U128& b, const U128& c, bool fpcr_controlled = true) {
@@ -2754,7 +2754,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMulAdd64, a, b, c, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorMulX(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2764,7 +2764,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorMulX64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorNeg(size_t esize, const U128& a) {
@@ -2776,7 +2776,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorNeg64, a);
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2786,7 +2786,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorPairedAdd64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2796,7 +2796,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorPairedAddLower64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled = true) {
@@ -2808,7 +2808,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorRecipEstimate64, a, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2820,7 +2820,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorRecipStepFused64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact, bool fpcr_controlled = true) {
@@ -2835,7 +2835,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorRoundInt64, operand, rounding_imm, exact_imm, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorRSqrtEstimate(size_t esize, const U128& a, bool fpcr_controlled = true) {
@@ -2847,7 +2847,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorRSqrtEstimate64, a, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2859,7 +2859,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorRSqrtStepFused64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorSqrt(size_t esize, const U128& a, bool fpcr_controlled = true) {
@@ -2869,7 +2869,7 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorSqrt64, a, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorSub(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) {
@@ -2879,16 +2879,16 @@ public:
         case 64:
             return Inst<U128>(Opcode::FPVectorSub64, a, b, Imm1(fpcr_controlled));
         }
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorToHalf(size_t esize, const U128& a, FP::RoundingMode rounding, bool fpcr_controlled = true) {
-        ASSERT(esize == 32);
+        assert(esize == 32);
         return Inst<U128>(Opcode::FPVectorToHalf32, a, Imm8(static_cast<u8>(rounding)), Imm1(fpcr_controlled));
     }
 
     U128 FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) {
-        ASSERT(fbits <= esize);
+        assert(fbits <= esize);
 
         const U8 fbits_imm = Imm8(static_cast<u8>(fbits));
         const U8 rounding_imm = Imm8(static_cast<u8>(rounding));
@@ -2902,11 +2902,11 @@ public:
             return Inst<U128>(Opcode::FPVectorToSignedFixed64, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled));
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     U128 FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) {
-        ASSERT(fbits <= esize);
+        assert(fbits <= esize);
 
         const U8 fbits_imm = Imm8(static_cast<u8>(fbits));
         const U8 rounding_imm = Imm8(static_cast<u8>(rounding));
@@ -2920,7 +2920,7 @@ public:
             return Inst<U128>(Opcode::FPVectorToUnsignedFixed64, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled));
         }
 
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     void Breakpoint() {
diff --git a/src/dynarmic/src/dynarmic/ir/location_descriptor.h b/src/dynarmic/src/dynarmic/ir/location_descriptor.h
index 5c7c954d38..ca44c03306 100644
--- a/src/dynarmic/src/dynarmic/ir/location_descriptor.h
+++ b/src/dynarmic/src/dynarmic/ir/location_descriptor.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -12,7 +12,7 @@
 #include <string>
 
 #include <fmt/format.h>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::IR {
 
diff --git a/src/dynarmic/src/dynarmic/ir/microinstruction.cpp b/src/dynarmic/src/dynarmic/ir/microinstruction.cpp
index cc555474ef..890fe3cffa 100644
--- a/src/dynarmic/src/dynarmic/ir/microinstruction.cpp
+++ b/src/dynarmic/src/dynarmic/ir/microinstruction.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -10,7 +10,7 @@
 
 #include <algorithm>
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 #include "dynarmic/ir/opcodes.h"
 #include "dynarmic/ir/type.h"
@@ -27,7 +27,7 @@ Inst* Inst::GetAssociatedPseudoOperation(Opcode opcode) {
     Inst* pseudoop = next_pseudoop;
     while (pseudoop) {
         if (pseudoop->GetOpcode() == opcode) {
-            ASSERT(pseudoop->GetArg(0).GetInst() == this);
+            assert(pseudoop->GetArg(0).GetInst() == this);
             return pseudoop;
         }
         pseudoop = pseudoop->next_pseudoop;
@@ -42,10 +42,10 @@ Type Inst::GetType() const {
 }
 
 void Inst::SetArg(size_t index, Value value) noexcept {
-    DEBUG_ASSERT(index < GetNumArgsOf(op));
-    DEBUG_ASSERT(AreTypesCompatible(value.GetType(), GetArgTypeOf(op, index)));
-    //DEBUG_ASSERT(index < GetNumArgsOf(op) && "Inst::SetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op));
-    //DEBUG_ASSERT(AreTypesCompatible(value.GetType(), GetArgTypeOf(op, index)) && "Inst::SetArg: type {} of argument {} not compatible with operation {} ({})", value.GetType(), index, op, GetArgTypeOf(op, index));
+    assert(index < GetNumArgsOf(op));
+    assert(AreTypesCompatible(value.GetType(), GetArgTypeOf(op, index)));
+    //assert(index < GetNumArgsOf(op) && "Inst::SetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op));
+    //assert(AreTypesCompatible(value.GetType(), GetArgTypeOf(op, index)) && "Inst::SetArg: type {} of argument {} not compatible with operation {} ({})", value.GetType(), index, op, GetArgTypeOf(op, index));
     if (!args[index].IsImmediate()) {
         UndoUse(args[index]);
     }
@@ -81,13 +81,13 @@ void Inst::Use(const Value& value) {
 
     if (IsAPseudoOperation(op)) {
         if (op == Opcode::GetNZCVFromOp) {
-            ASSERT(MayGetNZCVFromOp(value.GetInst()->GetOpcode()) && "This value doesn't support the GetNZCVFromOp pseduo-op");
+            assert(MayGetNZCVFromOp(value.GetInst()->GetOpcode()) && "This value doesn't support the GetNZCVFromOp pseduo-op");
         }
 
         Inst* insert_point = value.GetInst();
         while (insert_point->next_pseudoop) {
             insert_point = insert_point->next_pseudoop;
-            DEBUG_ASSERT(insert_point->GetArg(0).GetInst() == value.GetInst());
+            assert(insert_point->GetArg(0).GetInst() == value.GetInst());
         }
         insert_point->next_pseudoop = this;
     }
@@ -100,7 +100,7 @@ void Inst::UndoUse(const Value& value) {
         Inst* insert_point = value.GetInst();
         while (insert_point->next_pseudoop != this) {
             insert_point = insert_point->next_pseudoop;
-            DEBUG_ASSERT(insert_point->GetArg(0).GetInst() == value.GetInst());
+            assert(insert_point->GetArg(0).GetInst() == value.GetInst());
         }
         insert_point->next_pseudoop = next_pseudoop;
         next_pseudoop = nullptr;
diff --git a/src/dynarmic/src/dynarmic/ir/microinstruction.h b/src/dynarmic/src/dynarmic/ir/microinstruction.h
index fb3ac1f49a..b85e58b4e3 100644
--- a/src/dynarmic/src/dynarmic/ir/microinstruction.h
+++ b/src/dynarmic/src/dynarmic/ir/microinstruction.h
@@ -11,7 +11,7 @@
 #include <array>
 
 #include "dynarmic/mcl/intrusive_list.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/ir/value.h"
 #include "dynarmic/ir/opcodes.h"
@@ -53,10 +53,10 @@ public:
     }
 
     inline Value GetArg(size_t index) const noexcept {
-        DEBUG_ASSERT(index < GetNumArgsOf(op));
-        DEBUG_ASSERT(!args[index].IsEmpty() || GetArgTypeOf(op, index) == IR::Type::Opaque);
-        //DEBUG_ASSERT(index < GetNumArgsOf(op) && "Inst::GetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op));
-        //DEBUG_ASSERT(!args[index].IsEmpty() || GetArgTypeOf(op, index) == IR::Type::Opaque && "Inst::GetArg: index {} is empty", index, args[index].GetType());
+        assert(index < GetNumArgsOf(op));
+        assert(!args[index].IsEmpty() || GetArgTypeOf(op, index) == IR::Type::Opaque);
+        //assert(index < GetNumArgsOf(op) && "Inst::GetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op));
+        //assert(!args[index].IsEmpty() || GetArgTypeOf(op, index) == IR::Type::Opaque && "Inst::GetArg: index {} is empty", index, args[index].GetType());
         return args[index];
     }
     void SetArg(size_t index, Value value) noexcept;
diff --git a/src/dynarmic/src/dynarmic/ir/opcodes.h b/src/dynarmic/src/dynarmic/ir/opcodes.h
index 5886eb6a20..f975896a6b 100644
--- a/src/dynarmic/src/dynarmic/ir/opcodes.h
+++ b/src/dynarmic/src/dynarmic/ir/opcodes.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -11,7 +11,7 @@
 #include <string>
 
 #include <fmt/format.h>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::IR {
 
@@ -45,8 +45,8 @@ constexpr bool IsArithmeticShift(const Opcode op) noexcept {
 
 /// @brief Determines whether or not this instruction performs a logical shift.
 constexpr bool IsCircularShift(const Opcode op) noexcept {
-    return op == Opcode::RotateRight32
-        || op == Opcode::RotateRight64
+    return op == Opcode::BitRotateRight32
+        || op == Opcode::BitRotateRight64
         || op == Opcode::RotateRightExtended;
 }
 
diff --git a/src/dynarmic/src/dynarmic/ir/opcodes.inc b/src/dynarmic/src/dynarmic/ir/opcodes.inc
index b05220834d..6f57f278a3 100644
--- a/src/dynarmic/src/dynarmic/ir/opcodes.inc
+++ b/src/dynarmic/src/dynarmic/ir/opcodes.inc
@@ -46,8 +46,9 @@ OPCODE(LogicalShiftRight32,                                 U32,            U32,
 OPCODE(LogicalShiftRight64,                                 U64,            U64,            U8                                              )
 OPCODE(ArithmeticShiftRight32,                              U32,            U32,            U8,             U1                              )
 OPCODE(ArithmeticShiftRight64,                              U64,            U64,            U8                                              )
-OPCODE(RotateRight32,                                       U32,            U32,            U8,             U1                              )
-OPCODE(RotateRight64,                                       U64,            U64,            U8                                              )
+// windows.h defines RotateRight64 and RotateRight32
+OPCODE(BitRotateRight32,                                       U32,            U32,            U8,             U1                              )
+OPCODE(BitRotateRight64,                                       U64,            U64,            U8                                              )
 OPCODE(RotateRightExtended,                                 U32,            U32,            U1                                              )
 OPCODE(LogicalShiftLeftMasked32,                            U32,            U32,            U32                                             )
 OPCODE(LogicalShiftLeftMasked64,                            U64,            U64,            U64                                             )
diff --git a/src/dynarmic/src/dynarmic/ir/opt_passes.cpp b/src/dynarmic/src/dynarmic/ir/opt_passes.cpp
index ee29081d4d..ff7bd71c95 100644
--- a/src/dynarmic/src/dynarmic/ir/opt_passes.cpp
+++ b/src/dynarmic/src/dynarmic/ir/opt_passes.cpp
@@ -323,7 +323,7 @@ static void RegisterPass(IR::Block& block) {
         switch (opcode) {
         case IR::Opcode::A32GetRegister: {
             const A32::Reg reg = inst->GetArg(0).GetA32RegRef();
-            ASSERT(reg != A32::Reg::PC);
+            assert(reg != A32::Reg::PC);
             const size_t reg_index = size_t(reg);
             do_get(reg_info[reg_index], inst);
             break;
@@ -383,7 +383,7 @@ static void RegisterPass(IR::Block& block) {
                            },
                            inst);
             } else {
-                DEBUG_ASSERT(A32::IsQuadExtReg(reg));
+                assert(A32::IsQuadExtReg(reg));
                 do_ext_get(ExtValueType::VectorQuad,
                            {
                                ext_reg_info[reg_index * 4 + 0],
@@ -409,7 +409,7 @@ static void RegisterPass(IR::Block& block) {
                            stored_value,
                            inst);
             } else {
-                DEBUG_ASSERT(A32::IsQuadExtReg(reg));
+                assert(A32::IsQuadExtReg(reg));
                 do_ext_set(ExtValueType::VectorQuad,
                            {
                                ext_reg_info[reg_index * 4 + 0],
@@ -1072,12 +1072,12 @@ static void ConstantPropagation(IR::Block& block) {
                 ReplaceUsesWith(inst, false, Safe::ArithmeticShiftRight<u64>(inst.GetArg(0).GetU64(), inst.GetArg(1).GetU8()));
             }
             break;
-        case Op::RotateRight32:
+        case Op::BitRotateRight32:
             if (FoldShifts(inst)) {
                 ReplaceUsesWith(inst, true, mcl::bit::rotate_right<u32>(inst.GetArg(0).GetU32(), inst.GetArg(1).GetU8()));
             }
             break;
-        case Op::RotateRight64:
+        case Op::BitRotateRight64:
             if (FoldShifts(inst)) {
                 ReplaceUsesWith(inst, false, mcl::bit::rotate_right<u64>(inst.GetArg(0).GetU64(), inst.GetArg(1).GetU8()));
             }
@@ -1430,7 +1430,7 @@ static void VerificationPass(const IR::Block& block) {
         for (size_t i = 0; i < inst.NumArgs(); i++) {
             const IR::Type t1 = inst.GetArg(i).GetType();
             const IR::Type t2 = IR::GetArgTypeOf(inst.GetOpcode(), i);
-            ASSERT(IR::AreTypesCompatible(t1, t2));
+            assert(IR::AreTypesCompatible(t1, t2));
         }
     }
     ankerl::unordered_dense::map<IR::Inst*, size_t> actual_uses;
@@ -1440,7 +1440,7 @@ static void VerificationPass(const IR::Block& block) {
                 actual_uses[arg.GetInst()]++;
     }
     for (auto const& pair : actual_uses)
-        ASSERT(pair.first->UseCount() == pair.second);
+        assert(pair.first->UseCount() == pair.second);
 }
 
 void Optimize(IR::Block& block, const A32::UserConfig& conf, const Optimization::PolyfillOptions& polyfill_options) {
diff --git a/src/dynarmic/src/dynarmic/ir/terminal.h b/src/dynarmic/src/dynarmic/ir/terminal.h
index 187648b45c..9b91b27382 100644
--- a/src/dynarmic/src/dynarmic/ir/terminal.h
+++ b/src/dynarmic/src/dynarmic/ir/terminal.h
@@ -9,7 +9,7 @@
 #pragma once
 
 #include <boost/variant.hpp>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/ir/cond.h"
 #include "dynarmic/ir/location_descriptor.h"
diff --git a/src/dynarmic/src/dynarmic/ir/type.h b/src/dynarmic/src/dynarmic/ir/type.h
index e223513367..3344e26db1 100644
--- a/src/dynarmic/src/dynarmic/ir/type.h
+++ b/src/dynarmic/src/dynarmic/ir/type.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -11,7 +11,7 @@
 #include <string>
 
 #include <fmt/format.h>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace Dynarmic::IR {
 
diff --git a/src/dynarmic/src/dynarmic/ir/value.cpp b/src/dynarmic/src/dynarmic/ir/value.cpp
index 451036b1fd..faf1c445fe 100644
--- a/src/dynarmic/src/dynarmic/ir/value.cpp
+++ b/src/dynarmic/src/dynarmic/ir/value.cpp
@@ -8,7 +8,7 @@
 
 #include "dynarmic/ir/value.h"
 
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/mcl/bit.hpp"
 
 #include "dynarmic/ir/microinstruction.h"
@@ -119,32 +119,32 @@ Type Value::GetType() const noexcept {
 }
 
 A32::Reg Value::GetA32RegRef() const {
-    ASSERT(type == Type::A32Reg);
+    assert(type == Type::A32Reg);
     return inner.imm_a32regref;
 }
 
 A32::ExtReg Value::GetA32ExtRegRef() const {
-    ASSERT(type == Type::A32ExtReg);
+    assert(type == Type::A32ExtReg);
     return inner.imm_a32extregref;
 }
 
 A64::Reg Value::GetA64RegRef() const {
-    ASSERT(type == Type::A64Reg);
+    assert(type == Type::A64Reg);
     return inner.imm_a64regref;
 }
 
 A64::Vec Value::GetA64VecRef() const {
-    ASSERT(type == Type::A64Vec);
+    assert(type == Type::A64Vec);
     return inner.imm_a64vecref;
 }
 
 Inst* Value::GetInst() const {
-    ASSERT(type == Type::Opaque);
+    assert(type == Type::Opaque);
     return inner.inst;
 }
 
 Inst* Value::GetInstRecursive() const {
-    ASSERT(type == Type::Opaque);
+    assert(type == Type::Opaque);
     if (IsIdentity())
         return inner.inst->GetArg(0).GetInstRecursive();
     return inner.inst;
@@ -153,61 +153,61 @@ Inst* Value::GetInstRecursive() const {
 bool Value::GetU1() const {
     if (IsIdentity())
         return inner.inst->GetArg(0).GetU1();
-    ASSERT(type == Type::U1);
+    assert(type == Type::U1);
     return inner.imm_u1;
 }
 
 u8 Value::GetU8() const {
     if (IsIdentity())
         return inner.inst->GetArg(0).GetU8();
-    ASSERT(type == Type::U8);
+    assert(type == Type::U8);
     return inner.imm_u8;
 }
 
 u16 Value::GetU16() const {
     if (IsIdentity())
         return inner.inst->GetArg(0).GetU16();
-    ASSERT(type == Type::U16);
+    assert(type == Type::U16);
     return inner.imm_u16;
 }
 
 u32 Value::GetU32() const {
     if (IsIdentity())
         return inner.inst->GetArg(0).GetU32();
-    ASSERT(type == Type::U32);
+    assert(type == Type::U32);
     return inner.imm_u32;
 }
 
 u64 Value::GetU64() const {
     if (IsIdentity())
         return inner.inst->GetArg(0).GetU64();
-    ASSERT(type == Type::U64);
+    assert(type == Type::U64);
     return inner.imm_u64;
 }
 
 Value::CoprocessorInfo Value::GetCoprocInfo() const {
     if (IsIdentity())
         return inner.inst->GetArg(0).GetCoprocInfo();
-    ASSERT(type == Type::CoprocInfo);
+    assert(type == Type::CoprocInfo);
     return inner.imm_coproc;
 }
 
 Cond Value::GetCond() const {
     if (IsIdentity())
         return inner.inst->GetArg(0).GetCond();
-    ASSERT(type == Type::Cond);
+    assert(type == Type::Cond);
     return inner.imm_cond;
 }
 
 AccType Value::GetAccType() const {
     if (IsIdentity())
         return inner.inst->GetArg(0).GetAccType();
-    ASSERT(type == Type::AccType);
+    assert(type == Type::AccType);
     return inner.imm_acctype;
 }
 
 s64 Value::GetImmediateAsS64() const {
-    ASSERT(IsImmediate());
+    assert(IsImmediate());
     switch (GetType()) {
     case IR::Type::U1:
         return s64(GetU1());
@@ -220,12 +220,12 @@ s64 Value::GetImmediateAsS64() const {
     case IR::Type::U64:
         return s64(GetU64());
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
 u64 Value::GetImmediateAsU64() const {
-    ASSERT(IsImmediate());
+    assert(IsImmediate());
     switch (GetType()) {
     case IR::Type::U1:
         return u64(GetU1());
@@ -238,7 +238,7 @@ u64 Value::GetImmediateAsU64() const {
     case IR::Type::U64:
         return u64(GetU64());
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 }
 
diff --git a/src/dynarmic/src/dynarmic/ir/value.h b/src/dynarmic/src/dynarmic/ir/value.h
index ce439f77d1..5f8d2e76ca 100644
--- a/src/dynarmic/src/dynarmic/ir/value.h
+++ b/src/dynarmic/src/dynarmic/ir/value.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -11,8 +11,8 @@
 #include <array>
 #include <type_traits>
 
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 
 #include "dynarmic/ir/type.h"
 
@@ -147,12 +147,12 @@ public:
     template<Type other_type, typename = std::enable_if_t<(other_type & type_) != Type::Void>>
     /* implicit */ TypedValue(const TypedValue<other_type>& value)
             : Value(value) {
-        ASSERT((value.GetType() & type_) != Type::Void);
+        assert((value.GetType() & type_) != Type::Void);
     }
 
     explicit TypedValue(const Value& value)
             : Value(value) {
-        ASSERT((value.GetType() & type_) != Type::Void);
+        assert((value.GetType() & type_) != Type::Void);
     }
 
     explicit TypedValue(Inst* inst)
diff --git a/src/dynarmic/src/dynarmic/mcl/bit.hpp b/src/dynarmic/src/dynarmic/mcl/bit.hpp
index 1ef9880a5f..c4ec4259b5 100644
--- a/src/dynarmic/src/dynarmic/mcl/bit.hpp
+++ b/src/dynarmic/src/dynarmic/mcl/bit.hpp
@@ -9,8 +9,8 @@
 #include <climits>
 #include <cstddef>
 
-#include "dynarmic/common/common_types.h"
-#include "dynarmic/common/assert.h"
+#include "common/common_types.h"
+#include <cassert>
 
 namespace mcl {
 namespace detail {
@@ -104,7 +104,7 @@ constexpr T ones() {
 /// Create a mask with `count` number of one bits.
 template<BitIntegral T>
 constexpr T ones(size_t count) {
-    ASSERT(count <= bitsizeof<T> && "count larger than bitsize of T");
+    assert(count <= bitsizeof<T> && "count larger than bitsize of T");
     if (count == 0) {
         return 0;
     }
@@ -124,9 +124,9 @@ constexpr T mask() {
 /// Create a mask of type T for bits [begin_bit, end_bit] inclusive.
 template<BitIntegral T>
 constexpr T mask(size_t begin_bit, size_t end_bit) {
-    ASSERT(begin_bit <= end_bit && "invalid bit range (position of beginning bit cannot be greater than that of end bit)");
-    ASSERT(begin_bit < bitsizeof<T> && "begin_bit must be smaller than size of T");
-    ASSERT(end_bit < bitsizeof<T> && "end_bit must be smaller than size of T");
+    assert(begin_bit <= end_bit && "invalid bit range (position of beginning bit cannot be greater than that of end bit)");
+    assert(begin_bit < bitsizeof<T> && "begin_bit must be smaller than size of T");
+    assert(end_bit < bitsizeof<T> && "end_bit must be smaller than size of T");
     return ones<T>(end_bit - begin_bit + 1) << begin_bit;
 }
 
@@ -227,7 +227,7 @@ constexpr T sign_extend(T value) {
 /// Sign-extends a value that has bit_count bits to the full bitwidth of type T.
 template<BitIntegral T>
 constexpr T sign_extend(size_t bit_count, T value) {
-    ASSERT(bit_count != 0 && "cannot sign-extend zero-sized value");
+    assert(bit_count != 0 && "cannot sign-extend zero-sized value");
     using S = std::make_signed_t<T>;
     const size_t shift_amount = bitsizeof<T> - bit_count;
     return T(S(value << shift_amount) >> shift_amount);
@@ -257,8 +257,8 @@ constexpr T replicate_element(T value) {
 /// Replicate an element across a value of type T.
 template<BitIntegral T>
 constexpr T replicate_element(size_t element_size, T value) {
-    ASSERT(element_size <= bitsizeof<T> && "element_size is too large");
-    ASSERT(bitsizeof<T> % element_size == 0 && "bitsize of T not divisible by element_size");
+    assert(element_size <= bitsizeof<T> && "element_size is too large");
+    assert(bitsizeof<T> % element_size == 0 && "bitsize of T not divisible by element_size");
     if (element_size == bitsizeof<T>)
         return value;
     return replicate_element<T>(element_size * 2, static_cast<T>(value | (value << element_size)));
diff --git a/src/dynarmic/src/dynarmic/mcl/integer_of_size.hpp b/src/dynarmic/src/dynarmic/mcl/integer_of_size.hpp
index 8bdecc955d..1d54e9e3ef 100644
--- a/src/dynarmic/src/dynarmic/mcl/integer_of_size.hpp
+++ b/src/dynarmic/src/dynarmic/mcl/integer_of_size.hpp
@@ -5,7 +5,7 @@
 
 #pragma once
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 namespace mcl {
 
diff --git a/src/dynarmic/src/dynarmic/mcl/intrusive_list.hpp b/src/dynarmic/src/dynarmic/mcl/intrusive_list.hpp
index 3b1c1d6699..30b9961f71 100644
--- a/src/dynarmic/src/dynarmic/mcl/intrusive_list.hpp
+++ b/src/dynarmic/src/dynarmic/mcl/intrusive_list.hpp
@@ -9,7 +9,7 @@
 #include <iterator>
 #include <memory>
 #include <type_traits>
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 namespace mcl {
 
@@ -114,7 +114,7 @@ public:
 
     reference operator*() const
     {
-        DEBUG_ASSERT(!node->is_sentinel());
+        assert(!node->is_sentinel());
         return static_cast<reference>(*node);
     }
     pointer operator->() const
@@ -215,7 +215,7 @@ public:
      */
     void pop_front()
     {
-        DEBUG_ASSERT(!empty());
+        assert(!empty());
         erase(begin());
     }
 
@@ -225,7 +225,7 @@ public:
      */
     void pop_back()
     {
-        DEBUG_ASSERT(!empty());
+        assert(!empty());
         erase(--end());
     }
 
@@ -235,7 +235,7 @@ public:
      */
     pointer remove(iterator& it)
     {
-        DEBUG_ASSERT(it != end());
+        assert(it != end());
 
         pointer node = &*it++;
 
@@ -301,7 +301,7 @@ public:
      */
     reference front()
     {
-        DEBUG_ASSERT(!empty());
+        assert(!empty());
         return *begin();
     }
 
@@ -311,7 +311,7 @@ public:
      */
     const_reference front() const
     {
-        DEBUG_ASSERT(!empty());
+        assert(!empty());
         return *begin();
     }
 
@@ -321,7 +321,7 @@ public:
      */
     reference back()
     {
-        DEBUG_ASSERT(!empty());
+        assert(!empty());
         return *--end();
     }
 
@@ -331,7 +331,7 @@ public:
      */
     const_reference back() const
     {
-        DEBUG_ASSERT(!empty());
+        assert(!empty());
         return *--end();
     }
 
diff --git a/src/dynarmic/tests/A32/fuzz_arm.cpp b/src/dynarmic/tests/A32/fuzz_arm.cpp
index e9834a6663..b5c0ff47db 100644
--- a/src/dynarmic/tests/A32/fuzz_arm.cpp
+++ b/src/dynarmic/tests/A32/fuzz_arm.cpp
@@ -16,7 +16,7 @@
 
 #include <catch2/catch_test_macros.hpp>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/tests/fuzz_util.h"
 #include "dynarmic/tests/rand_int.h"
@@ -65,7 +65,7 @@ bool AnyLocationDescriptorForTerminalHas(IR::Terminal terminal, Fn fn) {
         } else if constexpr (std::is_same_v<T, IR::Term::CheckHalt>) {
             return AnyLocationDescriptorForTerminalHas(t.else_, fn);
         } else {
-            ASSERT(false && "Invalid terminal type");
+            assert(false && "Invalid terminal type");
             return false;
         }
     }, terminal);
@@ -273,7 +273,7 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
             } else if (bitstring.substr(0, 8) == "11110100") {
                 bitstring.replace(0, 8, "11111001");
             } else {
-                UNREACHABLE(); // "Unhandled ASIMD instruction: {} {}", fn, bs);
+                std::terminate(); //unreachable // "Unhandled ASIMD instruction: {} {}", fn, bs);
             }
             if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
                 invalid.emplace_back(InstructionGenerator{bitstring.c_str()});
diff --git a/src/dynarmic/tests/A32/fuzz_thumb.cpp b/src/dynarmic/tests/A32/fuzz_thumb.cpp
index 7fef968b95..421752e075 100644
--- a/src/dynarmic/tests/A32/fuzz_thumb.cpp
+++ b/src/dynarmic/tests/A32/fuzz_thumb.cpp
@@ -17,7 +17,7 @@
 
 #include <catch2/catch_test_macros.hpp>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/tests/rand_int.h"
 #include "dynarmic/tests/unicorn_emu/a32_unicorn.h"
@@ -76,7 +76,7 @@ public:
             inst = bits | (random & ~mask);
         } while (!is_valid(inst));
 
-        ASSERT((inst & mask) == bits);
+        assert((inst & mask) == bits);
 
         return static_cast<u16>(inst);
     }
@@ -89,7 +89,7 @@ public:
             inst = bits | (random & ~mask);
         } while (!is_valid(inst));
 
-        ASSERT((inst & mask) == bits);
+        assert((inst & mask) == bits);
 
         return inst;
     }
diff --git a/src/dynarmic/tests/A32/test_arm_instructions.cpp b/src/dynarmic/tests/A32/test_arm_instructions.cpp
index 5a27cd499c..c7501130cc 100644
--- a/src/dynarmic/tests/A32/test_arm_instructions.cpp
+++ b/src/dynarmic/tests/A32/test_arm_instructions.cpp
@@ -44,7 +44,7 @@ TEST_CASE("arm: Opt Failure: Const folding in MostSignificantWord", "[arm][A32]"
     test_env.ticks_left = 6;
     CheckedRun([&]() { jit.Run(); });
 
-    // If we don't trigger the GetCarryFromOp ASSERT, we're fine.
+    // If we don't trigger the GetCarryFromOp assert, we're fine.
 }
 
 TEST_CASE("arm: Unintended modification in SetCFlag", "[arm][A32]") {
diff --git a/src/dynarmic/tests/A32/test_thumb_instructions.cpp b/src/dynarmic/tests/A32/test_thumb_instructions.cpp
index 6aa1b7389b..f461806384 100644
--- a/src/dynarmic/tests/A32/test_thumb_instructions.cpp
+++ b/src/dynarmic/tests/A32/test_thumb_instructions.cpp
@@ -7,7 +7,7 @@
  */
 
 #include <catch2/catch_test_macros.hpp>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/tests/A32/testenv.h"
 #include "dynarmic/tests/native/testenv.h"
diff --git a/src/dynarmic/tests/A32/testenv.h b/src/dynarmic/tests/A32/testenv.h
index 6f303a58e9..fe60615dfe 100644
--- a/src/dynarmic/tests/A32/testenv.h
+++ b/src/dynarmic/tests/A32/testenv.h
@@ -14,8 +14,8 @@
 #include <string>
 #include <vector>
 
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 #include "dynarmic/interface/A32/a32.h"
 
 template<typename InstructionType_, u32 infinite_loop_u32>
@@ -98,11 +98,11 @@ public:
     }
 
     void CallSVC(std::uint32_t swi) override {
-        UNREACHABLE(); //ASSERT(false && "CallSVC({})", swi);
+        std::terminate(); //unreachable //assert(false && "CallSVC({})", swi);
     }
 
     void ExceptionRaised(u32 pc, Dynarmic::A32::Exception /*exception*/) override {
-        UNREACHABLE(); //ASSERT(false && "ExceptionRaised({:08x}) code = {:08x}", pc, *MemoryReadCode(pc));
+        std::terminate(); //unreachable //assert(false && "ExceptionRaised({:08x}) code = {:08x}", pc, *MemoryReadCode(pc));
     }
 
     void AddTicks(std::uint64_t ticks) override {
@@ -187,11 +187,11 @@ public:
     }
 
     void CallSVC(std::uint32_t swi) override {
-        UNREACHABLE(); //ASSERT(false && "CallSVC({})", swi);
+        std::terminate(); //unreachable //assert(false && "CallSVC({})", swi);
     }
 
     void ExceptionRaised(std::uint32_t pc, Dynarmic::A32::Exception) override {
-        UNREACHABLE(); //ASSERT(false && "ExceptionRaised({:016x})", pc);
+        std::terminate(); //unreachable //assert(false && "ExceptionRaised({:016x})", pc);
     }
 
     void AddTicks(std::uint64_t ticks) override {
diff --git a/src/dynarmic/tests/A64/fibonacci.cpp b/src/dynarmic/tests/A64/fibonacci.cpp
index d706118cd2..12c4170f66 100644
--- a/src/dynarmic/tests/A64/fibonacci.cpp
+++ b/src/dynarmic/tests/A64/fibonacci.cpp
@@ -11,7 +11,7 @@
 #include <ankerl/unordered_dense.h>
 
 #include <catch2/catch_test_macros.hpp>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 #include <oaknut/oaknut.hpp>
 
 #include "dynarmic/interface/A64/a64.h"
diff --git a/src/dynarmic/tests/A64/fp_min_max.cpp b/src/dynarmic/tests/A64/fp_min_max.cpp
index 313b5e5117..cb27342ff9 100644
--- a/src/dynarmic/tests/A64/fp_min_max.cpp
+++ b/src/dynarmic/tests/A64/fp_min_max.cpp
@@ -9,7 +9,7 @@
 #include <vector>
 
 #include <catch2/catch_test_macros.hpp>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/tests/A64/testenv.h"
 #include "dynarmic/tests/native/testenv.h"
diff --git a/src/dynarmic/tests/A64/fuzz_with_unicorn.cpp b/src/dynarmic/tests/A64/fuzz_with_unicorn.cpp
index 749cc77126..90df625143 100644
--- a/src/dynarmic/tests/A64/fuzz_with_unicorn.cpp
+++ b/src/dynarmic/tests/A64/fuzz_with_unicorn.cpp
@@ -12,7 +12,7 @@
 #include <vector>
 
 #include <catch2/catch_test_macros.hpp>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/tests/fuzz_util.h"
 #include "dynarmic/tests/rand_int.h"
diff --git a/src/dynarmic/tests/A64/testenv.h b/src/dynarmic/tests/A64/testenv.h
index 2b8733a177..db8eaa3fa1 100644
--- a/src/dynarmic/tests/A64/testenv.h
+++ b/src/dynarmic/tests/A64/testenv.h
@@ -9,8 +9,8 @@
 #pragma once
 
 #include <ankerl/unordered_dense.h>
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <cassert>
+#include "common/common_types.h"
 #include "dynarmic/interface/A64/a64.h"
 
 using Vector = Dynarmic::A64::Vector;
@@ -106,11 +106,11 @@ public:
     }
 
     void CallSVC(std::uint32_t swi) override {
-        UNREACHABLE(); //ASSERT(false && "CallSVC({})", swi);
+        std::terminate(); //unreachable //assert(false && "CallSVC({})", swi);
     }
 
     void ExceptionRaised(u64 pc, Dynarmic::A64::Exception /*exception*/) override {
-        UNREACHABLE(); //ASSERT(false && "ExceptionRaised({:016x})", pc);
+        std::terminate(); //unreachable //assert(false && "ExceptionRaised({:016x})", pc);
     }
 
     void AddTicks(std::uint64_t ticks) override {
@@ -205,11 +205,11 @@ public:
     }
 
     void CallSVC(std::uint32_t swi) override {
-        UNREACHABLE(); //ASSERT(false && "CallSVC({})", swi);
+        std::terminate(); //unreachable //assert(false && "CallSVC({})", swi);
     }
 
     void ExceptionRaised(u64 pc, Dynarmic::A64::Exception) override {
-        UNREACHABLE(); //ASSERT(false && "ExceptionRaised({:016x})", pc);
+        std::terminate(); //unreachable //assert(false && "ExceptionRaised({:016x})", pc);
     }
 
     void AddTicks(std::uint64_t ticks) override {
diff --git a/src/dynarmic/tests/decoder_tests.cpp b/src/dynarmic/tests/decoder_tests.cpp
index 1b406fd915..4148536b46 100644
--- a/src/dynarmic/tests/decoder_tests.cpp
+++ b/src/dynarmic/tests/decoder_tests.cpp
@@ -11,7 +11,7 @@
 #include <iostream>
 
 #include <catch2/catch_test_macros.hpp>
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 #include "dynarmic/frontend/A32/decoder/asimd.h"
 #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h"
@@ -24,7 +24,7 @@ TEST_CASE("ASIMD Decoder: Ensure table order correctness", "[decode][a32][.]") {
     const auto table = A32::GetASIMDDecodeTable<A32::TranslatorVisitor>();
 
     const auto get_ir = [](const A32::ASIMDMatcher<A32::TranslatorVisitor>& matcher, u32 instruction) {
-        ASSERT(matcher.Matches(instruction));
+        assert(matcher.Matches(instruction));
 
         const A32::LocationDescriptor location{0, {}, {}};
         IR::Block block{location};
diff --git a/src/dynarmic/tests/fp/FPToFixed.cpp b/src/dynarmic/tests/fp/FPToFixed.cpp
index e16e4460ed..5df0a066fa 100644
--- a/src/dynarmic/tests/fp/FPToFixed.cpp
+++ b/src/dynarmic/tests/fp/FPToFixed.cpp
@@ -10,7 +10,7 @@
 #include <vector>
 
 #include <catch2/catch_test_macros.hpp>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/tests/rand_int.h"
 #include "dynarmic/common/fp/fpcr.h"
diff --git a/src/dynarmic/tests/fp/mantissa_util_tests.cpp b/src/dynarmic/tests/fp/mantissa_util_tests.cpp
index 9d16c3624c..259e30edc7 100644
--- a/src/dynarmic/tests/fp/mantissa_util_tests.cpp
+++ b/src/dynarmic/tests/fp/mantissa_util_tests.cpp
@@ -10,7 +10,7 @@
 #include <vector>
 
 #include <catch2/catch_test_macros.hpp>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/tests/rand_int.h"
 #include "dynarmic/common/fp/mantissa_util.h"
diff --git a/src/dynarmic/tests/fp/unpacked_tests.cpp b/src/dynarmic/tests/fp/unpacked_tests.cpp
index a4f10d1273..4fdd4ccc13 100644
--- a/src/dynarmic/tests/fp/unpacked_tests.cpp
+++ b/src/dynarmic/tests/fp/unpacked_tests.cpp
@@ -10,7 +10,7 @@
 #include <vector>
 
 #include <catch2/catch_test_macros.hpp>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/tests/rand_int.h"
 #include "dynarmic/common/fp/fpcr.h"
diff --git a/src/dynarmic/tests/fuzz_util.cpp b/src/dynarmic/tests/fuzz_util.cpp
index 05f0a9e865..f671e44208 100644
--- a/src/dynarmic/tests/fuzz_util.cpp
+++ b/src/dynarmic/tests/fuzz_util.cpp
@@ -12,7 +12,7 @@
 
 #include <fmt/format.h>
 #include <fmt/ostream.h>
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
 #include "dynarmic/tests/rand_int.h"
 #include "dynarmic/common/fp/fpcr.h"
@@ -40,7 +40,7 @@ u32 RandomFpcr() {
 
 InstructionGenerator::InstructionGenerator(const char* format) {
     const size_t format_len = std::strlen(format);
-    ASSERT(format_len == 16 || format_len == 32);
+    assert(format_len == 16 || format_len == 32);
 
     if (format_len == 16) {
         // Begin with 16 zeros
diff --git a/src/dynarmic/tests/fuzz_util.h b/src/dynarmic/tests/fuzz_util.h
index a0b8666969..b14b9a4362 100644
--- a/src/dynarmic/tests/fuzz_util.h
+++ b/src/dynarmic/tests/fuzz_util.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -11,7 +11,7 @@
 #include <array>
 #include <iosfwd>
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 using Vector = std::array<u64, 2>;
 
diff --git a/src/dynarmic/tests/print_info.cpp b/src/dynarmic/tests/print_info.cpp
index 19e2ca38b2..6d6109d849 100644
--- a/src/dynarmic/tests/print_info.cpp
+++ b/src/dynarmic/tests/print_info.cpp
@@ -19,7 +19,7 @@
 #include <fmt/ostream.h>
 #include <fmt/ranges.h>
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/llvm_disassemble.h"
 #include "dynarmic/frontend/A32/a32_location_descriptor.h"
@@ -57,7 +57,7 @@ std::string_view GetNameOfA64Instruction(u32 instruction) {
 }
 
 void PrintA32Instruction(u32 instruction) {
-    fmt::print("{:08x} {}\n", instruction, Common::DisassembleAArch32(false, 0, (u8*)&instruction, sizeof(instruction)));
+    fmt::print("{:08x} {}\n", instruction, Dynarmic::Common::DisassembleAArch32(false, 0, (u8*)&instruction, sizeof(instruction)));
     fmt::print("Name: {}\n", GetNameOfA32Instruction(instruction));
 
     const A32::LocationDescriptor location{0, {}, {}};
@@ -75,7 +75,7 @@ void PrintA32Instruction(u32 instruction) {
 }
 
 void PrintA64Instruction(u32 instruction) {
-    fmt::print("{:08x} {}\n", instruction, Common::DisassembleAArch64(instruction));
+    fmt::print("{:08x} {}\n", instruction, Dynarmic::Common::DisassembleAArch64(instruction));
     fmt::print("Name: {}\n", GetNameOfA64Instruction(instruction));
 
     const A64::LocationDescriptor location{0, {}};
@@ -97,7 +97,7 @@ void PrintThumbInstruction(u32 instruction) {
     if (inst_size == 4)
         instruction = mcl::bit::swap_halves_32(instruction);
 
-    fmt::print("{:08x} {}\n", instruction, Common::DisassembleAArch32(true, 0, (u8*)&instruction, inst_size));
+    fmt::print("{:08x} {}\n", instruction, Dynarmic::Common::DisassembleAArch32(true, 0, (u8*)&instruction, inst_size));
 
     const A32::LocationDescriptor location{0, A32::PSR{0x1F0}, {}};
     IR::Block ir_block{location};
diff --git a/src/dynarmic/tests/rsqrt_test.cpp b/src/dynarmic/tests/rsqrt_test.cpp
index 6af71ede64..5dd52f26da 100644
--- a/src/dynarmic/tests/rsqrt_test.cpp
+++ b/src/dynarmic/tests/rsqrt_test.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -9,7 +9,7 @@
 #include <catch2/benchmark/catch_benchmark.hpp>
 #include <catch2/catch_test_macros.hpp>
 #include <fmt/printf.h>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/common/fp/fpcr.h"
 #include "dynarmic/common/fp/fpsr.h"
diff --git a/src/dynarmic/tests/test_generator.cpp b/src/dynarmic/tests/test_generator.cpp
index 43203c3e13..b469d327d5 100644
--- a/src/dynarmic/tests/test_generator.cpp
+++ b/src/dynarmic/tests/test_generator.cpp
@@ -17,7 +17,7 @@
 #include <vector>
 
 #include "dynarmic/mcl/bit.hpp"
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "./A32/testenv.h"
 #include "./A64/testenv.h"
@@ -301,7 +301,7 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
             } else if (bitstring.substr(0, 8) == "11110100") {
                 bitstring.replace(0, 8, "11111001");
             } else {
-                UNREACHABLE(); // "Unhandled ASIMD instruction: {} {}", fn, bs);
+                std::terminate(); //unreachable // "Unhandled ASIMD instruction: {} {}", fn, bs);
             }
             if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
                 invalid.emplace_back(InstructionGenerator{bitstring.c_str()});
diff --git a/src/dynarmic/tests/test_reader.cpp b/src/dynarmic/tests/test_reader.cpp
index dd7fccc7d7..1c2cba1c44 100644
--- a/src/dynarmic/tests/test_reader.cpp
+++ b/src/dynarmic/tests/test_reader.cpp
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -13,7 +13,7 @@
 #include <vector>
 
 #include <fmt/format.h>
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "./A32/testenv.h"
 #include "./A64/testenv.h"
diff --git a/src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp b/src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp
index 9a17bc5582..8c1da903ce 100644
--- a/src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp
+++ b/src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp
@@ -10,10 +10,10 @@
 #include <fmt/format.h>
 #include "dynarmic/mcl/bit.hpp"
 #include "dynarmic/tests/unicorn_emu/a32_unicorn.h"
-#include "dynarmic/common/assert.h"
+#include <cassert>
 #include "dynarmic/tests/A32/testenv.h"
 
-#define CHECKED(expr) do if ((expr)) ASSERT(false && "Call " #expr " failed with error\n"); while (0)
+#define CHECKED(expr) do if ((expr)) assert(false && "Call " #expr " failed with error\n"); while (0)
 
 constexpr u32 BEGIN_ADDRESS = 0;
 constexpr u32 END_ADDRESS = ~u32(0);
@@ -336,7 +336,7 @@ bool A32Unicorn<TestEnvironment>::MemoryWriteHook(uc_engine* /*uc*/, uc_mem_type
         this_->testenv.MemoryWrite64(start_address, value);
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     return true;
diff --git a/src/dynarmic/tests/unicorn_emu/a32_unicorn.h b/src/dynarmic/tests/unicorn_emu/a32_unicorn.h
index d94724d9f2..98c03db76c 100644
--- a/src/dynarmic/tests/unicorn_emu/a32_unicorn.h
+++ b/src/dynarmic/tests/unicorn_emu/a32_unicorn.h
@@ -19,7 +19,7 @@
 #    include <unicorn/unicorn.h>
 #endif
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/tests/A32/testenv.h"
 
diff --git a/src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp b/src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp
index c8aa404199..cab3d5d45b 100644
--- a/src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp
+++ b/src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp
@@ -8,9 +8,9 @@
 
 #include <fmt/format.h>
 #include "dynarmic/tests/unicorn_emu/a64_unicorn.h"
-#include "dynarmic/common/assert.h"
+#include <cassert>
 
-#define CHECKED(expr) do if ((expr)) ASSERT(false && "Call " #expr " failed with error\n"); while (0)
+#define CHECKED(expr) do if ((expr)) assert(false && "Call " #expr " failed with error\n"); while (0)
 
 constexpr u64 BEGIN_ADDRESS = 0;
 constexpr u64 END_ADDRESS = ~u64(0);
@@ -242,7 +242,7 @@ bool A64Unicorn::MemoryWriteHook(uc_engine* /*uc*/, uc_mem_type /*type*/, u64 st
         this_->testenv.MemoryWrite64(start_address, value);
         break;
     default:
-        UNREACHABLE();
+        std::terminate(); //unreachable
     }
 
     return true;
diff --git a/src/dynarmic/tests/unicorn_emu/a64_unicorn.h b/src/dynarmic/tests/unicorn_emu/a64_unicorn.h
index 1bc5b1cb8e..091be950ed 100644
--- a/src/dynarmic/tests/unicorn_emu/a64_unicorn.h
+++ b/src/dynarmic/tests/unicorn_emu/a64_unicorn.h
@@ -19,7 +19,7 @@
 #    include <unicorn/unicorn.h>
 #endif
 
-#include "dynarmic/common/common_types.h"
+#include "common/common_types.h"
 
 #include "dynarmic/tests/A64/testenv.h"