Ops

Use shift operations for dynamic bit extraction for better performance
Fix IsScaled dynamic indexing reading wrong bit source
2026-04-10 03:18:55 +02:00 · 2026-04-02 14:56:52 +02:00 · 2026-04-02 14:54:12 +02:00 · 2026-04-02 14:54:12 +02:00 · 2026-04-02 06:06:46 +02:00 · 2026-04-02 06:06:16 +02:00
21 changed files with 2890 additions and 1645 deletions
--- a/dist/icon_variations/aprilfools2026.svg
+++ b/dist/icon_variations/aprilfools2026.svg
--- a/dist/icon_variations/aprilfools2026_bgcolor
+++ b/dist/icon_variations/aprilfools2026_bgcolor
@ -0,0 +1 @@
+#43fcfcff
--- a/docs/Deps.md
+++ b/docs/Deps.md
@ -334,7 +334,7 @@ pacman -Syuu --needed --noconfirm $packages
 <summary>HaikuOS</summary>

 ```sh
-pkgman install git cmake patch libfmt_devel nlohmann_json lz4_devel opus_devel boost1.89_devel vulkan_devel qt6_base_devel qt6_declarative_devel libsdl2_devel ffmpeg7_devel libx11_devel enet_devel catch2_devel quazip1_qt5_devel qt6_5compat_devel glslang qt6_devel qt6_charts_devel
+pkgman install git cmake patch libfmt_devel nlohmann_json lz4_devel opus_devel boost1.90_devel vulkan_devel qt6_base_devel qt6_declarative_devel libsdl2_devel ffmpeg7_devel libx11_devel enet_devel catch2_devel quazip1_qt5_devel qt6_5compat_devel glslang qt6_devel qt6_charts_devel
 ```

 [Caveats](./Caveats.md#haikuos).
--- a/docs/user/Multiplayer.md
+++ b/docs/user/Multiplayer.md
@ -56,7 +56,7 @@ Use this when you need to connect to a multiplayer room for LDN functionality in
 - Multiplayer Options Configured in Eden Settings
 - Network Access

-## Steps
+### Steps
 There are 2 primary methods that you can use to connect to an existing room, depending on how the room is hosted.

 - Joining a Public Lobby
@ -70,7 +70,7 @@ There are 2 primary methods that you can use to connect to an existing room, dep

 </aside>

-### Joining a Public Lobby
+## Joining a Public Lobby
 1. Open Eden and navigate to *Multiplayer → Browse Public Game Lobby*.
 2. The **Public Room Browser** will now open and display a list of publicly accessible rooms.  Find one you want to connect to and double click it.
    
@ -90,7 +90,7 @@ If the hoster has not made the lobby public, or you don't want to find it in the

 ---

-# Hosting a Multiplayer Room
+## Hosting a Multiplayer Room
 Use this guide for when you want to host a multiplayer lobby to play with others in Eden.  In order to have someone access the room from outside your local network, see the *Access Your Multiplayer Room Externally* section for next steps.

 **Click [Here](https://evilperson1337.notion.site/Hosting-a-Multiplayer-Room-2c357c2edaf6819481dbe8a99926cea2) for a version of this guide with images & visual elements.**
@ -100,7 +100,7 @@ Use this guide for when you want to host a multiplayer lobby to play with others
 - Network Access
 - Ability to allow programs through the firewall on your device.

-## Steps
+### Steps
 1. Open Eden and navigate to *Emulation → Multiplayer → Create Room.*    
 2. Fill out the following information in the popup dialog box.
    
@ -120,7 +120,7 @@ Use this guide for when you want to host a multiplayer lobby to play with others

 ---

-# Access Your Multiplayer Room Externally
+## Access Your Multiplayer Room Externally
 Quite often the person with whom you want to play is located off of your internal network (LAN).  If you want to host a room and play with them you will need to get your devices to communicate with each other.  This guide will go over your options on how to do this so that you can play together.

 **Click [Here](https://evilperson1337.notion.site/Access-Your-Multiplayer-Room-Externally-2c357c2edaf681c0ab2ce2ee624d809d) for a version of this guide with images & visual elements.**
@ -129,9 +129,9 @@ Quite often the person with whom you want to play is located off of your interna
 - Eden set up and Functioning
 - Network Access

-## Options
+### Options

-### Port Forwarding
+#### Port Forwarding

 - **Difficulty Level**: High
    
@ -148,8 +148,9 @@ The process works by creating a static mapping—often called a “port-forward

 For our purposes we would pick the port we want to expose (*e.g. 24872*) and we would access our router's configuration and create a port-forward rule to send the traffic from an external connection to your local machine over our specified port (*24872)*.  The exact way to do so, varies greatly by router manufacturer - and sometimes require contacting your ISP to do so depending on your agreement.  You can look up your router on [*portforward.com*](https://portforward.com/router.htm) which may have instructions on how to do so for your specific equipment.  If it is not there, you will have to use Google/ChatGPT to determine the steps for your equipment.

+Remember you can't have one port open for multiple devices at the same time - you must only host from one device (or do more convoluted networking which we will not cover here).

-### Use a Tunnelling Service
+#### Use a Tunnelling Service
 - **Difficulty Level**: Easy
    
    <aside>
@ -167,7 +168,7 @@ For our purposes we would spawn the listener for the port that way chose when ho
 - [*Playit.GG*](https://playit.gg/)


-### Use a VPN Service
+#### Use a VPN Service

 - **Difficulty**: Easy

@ -189,7 +190,7 @@ The VPN solution is a good compromise between the tunnelling solution and port f

 ---

-# Finding the Server Information for a Multiplayer Room
+## Finding the Server Information for a Multiplayer Room
 Use this guide when you need to determine the connection information for the Public Multiplayer Lobby you are connected to.

 **Click [Here](https://evilperson1337.notion.site/Finding-the-Server-Information-for-a-Multiplayer-Room-2c557c2edaf6809e94e8ed3429b9eb26) for a version of this guide with images & visual elements.**
@ -198,7 +199,7 @@ Use this guide when you need to determine the connection information for the Pub
 - Eden set up and configured
 - Internet Access

-## Steps
+### Steps

 ### Method 1: Grabbing the Address from the Log File
 1. Open Eden and Connect to the room you want to identify.
@ -222,7 +223,7 @@ Use this guide when you need to determine the connection information for the Pub
 2. Open the terminal supported by your operating system.
 3. Run one of the following commands, replacing *<Name>* with the name of the server from step 1.
    
-    ### PowerShell Command [Windows Users]
+    #### PowerShell Command [Windows Users]
    
    ```powershell
    # Calls the API to get the address and port information
@ -235,7 +236,7 @@ Use this guide when you need to determine the connection information for the Pub
    #}
    ```
    
-    ### CURL Command [MacOS/Linux Users] **Requires jq*
+    #### CURL Command [MacOS/Linux Users] **Requires jq*
    
    ```bash
    # Calls the API to get the address and port information
@ -252,7 +253,7 @@ Use this guide when you need to determine the connection information for the Pub

 ---

-# Multiplayer for Local Co-Op Games
+## Multiplayer for Local Co-Op Games
 Use this guide when you want to play with a friend on a different system for games that only support local co-op.

 **Click [Here](https://evilperson1337.notion.site/Multiplayer-for-Local-Co-Op-Games-2c657c2edaf680c59975ec6b52022a2d) for a version of this guide with images & visual elements.**
@ -271,7 +272,7 @@ In either situation at its core, we are emulating an input device on the host ma
    - Parsec is free to use for personal, non-commercial use.  For instructions on how to set up an account and install the client you should refer to the Parsec documentation on it's site.
 - Parsec client installed on your machine and remote (friend's) machine

-## Steps
+### Steps

 <aside>

@ -294,3 +295,22 @@ This guide will assume you are the one hosting the game and go over things *Pars
 10. Set up the remote player's controller.
 11. Hit **OK** to apply the changes.
 12. Launch the game you want to play and enter the co-op mode.  How this works depends on the game, so you will have to look in the menus or online to find out.
+
+## Metaserver troubleshooting
+
+If you can't connect to the metaserver, it's likely your ISP is blocking the requests.
+
+### Linux and Steamdeck
+
+Most Linux systems and Steamdeck should allow to modify the base `/etc/hosts` file, this should fix the DNS lookup issue; hence add the following to said file:
+```
+28.165.181.135 api.ynet-fun.xyz api.ynet-fun.xyz
+```
+
+### Zapret
+
+In `lists/list-general.txt` add the following:
+```
+api.ynet-fun.xyz
+ynet-fun.xyz
+```
--- a/src/core/tools/renderdoc.cpp
+++ b/src/core/tools/renderdoc.cpp
@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later

 // SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
@ -51,10 +51,12 @@ void RenderdocAPI::ToggleCapture() {
    if (!rdoc_api) [[unlikely]] {
        return;
    }
+
+    auto* api = static_cast<RENDERDOC_API_1_6_0*>(rdoc_api);
    if (!is_capturing) {
-        rdoc_api->StartFrameCapture(NULL, NULL);
+        api->StartFrameCapture(NULL, NULL);
    } else {
-        rdoc_api->EndFrameCapture(NULL, NULL);
+        api->EndFrameCapture(NULL, NULL);
    }
    is_capturing = !is_capturing;
 }
--- a/src/core/tools/renderdoc.h
+++ b/src/core/tools/renderdoc.h
@ -6,8 +6,6 @@

 #pragma once

-struct RENDERDOC_API_1_7_0;
-
 namespace Tools {

 class RenderdocAPI {
@ -18,7 +16,7 @@ public:
    void ToggleCapture();

 private:
-    RENDERDOC_API_1_7_0* rdoc_api{};
+    void* rdoc_api{};
    bool is_capturing{false};
 };

--- a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp
@ -316,8 +316,8 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
        return current_location->index;
    }

-    ASSERT(!ValueInfo(*current_location).realized);
-    ASSERT(ValueInfo(*current_location).locked);
+    ASSERT(!bool(ValueInfo(*current_location).realized));
+    ASSERT(bool(ValueInfo(*current_location).locked));

    if constexpr (required_kind == HostLoc::Kind::Gpr) {
        const int new_location_index = AllocateRegister(gprs, gpr_order);
--- a/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.h
+++ b/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.h
@ -50,7 +50,7 @@ public:
    }
    inline void ReadLock() noexcept {
        ASSERT(size_t(is_being_used_count) + 1 < (std::numeric_limits<decltype(is_being_used_count)>::max)());
-        ASSERT(!is_scratch);
+        ASSERT(!bool(is_scratch));
        is_being_used_count++;
    }
    inline void WriteLock() noexcept {
--- a/src/dynarmic/src/dynarmic/frontend/A32/decoder/arm.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/decoder/arm.h
@ -36,25 +36,19 @@ inline size_t ToFastLookupIndexArm(u32 instruction) noexcept {
 }  // namespace detail

 template<typename V>
-constexpr ArmDecodeTable<V> GetArmDecodeTable() noexcept {
-    std::vector<ArmMatcher<V>> list = {
+static ArmDecodeTable<V> GetArmDecodeTable() noexcept {
+    ArmDecodeTable<V> table{};
+    for (size_t i = 0; i < table.size(); ++i) {
+        // PLEASE HEAP ELLIDE
+        for (auto const& e : std::vector<ArmMatcher<V>>{
 #define INST(fn, name, bitstring) DYNARMIC_DECODER_GET_MATCHER(ArmMatcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)),
 #include "./arm.inc"
 #undef INST
-    };
-
-    // If a matcher has more bits in its mask it is more specific, so it should come first.
-    std::stable_sort(list.begin(), list.end(), [](const auto& matcher1, const auto& matcher2) {
-        return mcl::bit::count_ones(matcher1.GetMask()) > mcl::bit::count_ones(matcher2.GetMask());
-    });
-
-    ArmDecodeTable<V> table{};
-    for (size_t i = 0; i < table.size(); ++i) {
-        for (auto matcher : list) {
-            const auto expect = detail::ToFastLookupIndexArm(matcher.GetExpected());
-            const auto mask = detail::ToFastLookupIndexArm(matcher.GetMask());
+        }) {
+            auto const expect = detail::ToFastLookupIndexArm(e.GetExpected());
+            auto const mask = detail::ToFastLookupIndexArm(e.GetMask());
            if ((i & mask) == expect) {
-                table[i].push_back(matcher);
+                table[i].push_back(e);
            }
        }
    }
@ -62,7 +56,7 @@ constexpr ArmDecodeTable<V> GetArmDecodeTable() noexcept {
 }

 template<typename V>
-std::optional<std::reference_wrapper<const ArmMatcher<V>>> DecodeArm(u32 instruction) noexcept {
+static std::optional<std::reference_wrapper<const ArmMatcher<V>>> DecodeArm(u32 instruction) noexcept {
    alignas(64) static const auto table = GetArmDecodeTable<V>();
    const auto matches_instruction = [instruction](const auto& matcher) {
        return matcher.Matches(instruction);
@ -73,7 +67,7 @@ std::optional<std::reference_wrapper<const ArmMatcher<V>>> DecodeArm(u32 instruc
 }

 template<typename V>
-std::optional<std::string_view> GetNameARM(u32 inst) noexcept {
+static std::optional<std::string_view> GetNameARM(u32 inst) noexcept {
    std::vector<std::pair<std::string_view, ArmMatcher<V>>> list = {
 #define INST(fn, name, bitstring) { name, DYNARMIC_DECODER_GET_MATCHER(ArmMatcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)) },
 #include "./arm.inc"
--- a/src/dynarmic/src/dynarmic/frontend/A32/decoder/arm.inc
+++ b/src/dynarmic/src/dynarmic/frontend/A32/decoder/arm.inc
@ -1,316 +1,265 @@
-// Barrier instructions
-INST(arm_DMB,           "DMB",                 "1111010101111111111100000101oooo") // v7
-INST(arm_DSB,           "DSB",                 "1111010101111111111100000100oooo") // v7
-INST(arm_ISB,           "ISB",                 "1111010101111111111100000110oooo") // v7
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+// DO NOT REORDER

-// Branch instructions
-INST(arm_BLX_imm,       "BLX (imm)",           "1111101hvvvvvvvvvvvvvvvvvvvvvvvv") // v5
-INST(arm_BLX_reg,       "BLX (reg)",           "cccc000100101111111111110011mmmm") // v5
-INST(arm_B,             "B",                   "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv") // v1
-INST(arm_BL,            "BL",                  "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv") // v1
-INST(arm_BX,            "BX",                  "cccc000100101111111111110001mmmm") // v4T
-INST(arm_BXJ,           "BXJ",                 "cccc000100101111111111110010mmmm") // v5J
-
-// CRC32 instructions
-INST(arm_CRC32,         "CRC32",               "cccc00010zz0nnnndddd00000100mmmm") // v8
-INST(arm_CRC32C,        "CRC32C",              "cccc00010zz0nnnndddd00100100mmmm") // v8
-
-// Coprocessor instructions
-INST(arm_CDP,           "CDP",                 "cccc1110ooooNNNNDDDDppppooo0MMMM") // v2  (CDP2:  v5)
-INST(arm_LDC,           "LDC",                 "cccc110pudw1nnnnDDDDppppvvvvvvvv") // v2  (LDC2:  v5)
-INST(arm_MCR,           "MCR",                 "cccc1110ooo0NNNNttttppppooo1MMMM") // v2  (MCR2:  v5)
-INST(arm_MCRR,          "MCRR",                "cccc11000100uuuuttttppppooooMMMM") // v5E (MCRR2: v6)
-INST(arm_MRC,           "MRC",                 "cccc1110ooo1NNNNttttppppooo1MMMM") // v2  (MRC2:  v5)
-INST(arm_MRRC,          "MRRC",                "cccc11000101uuuuttttppppooooMMMM") // v5E (MRRC2: v6)
-INST(arm_STC,           "STC",                 "cccc110pudw0nnnnDDDDppppvvvvvvvv") // v2  (STC2:  v5)
-
-// Data Processing instructions
-INST(arm_ADC_imm,       "ADC (imm)",           "cccc0010101Snnnnddddrrrrvvvvvvvv") // v1
-INST(arm_ADC_reg,       "ADC (reg)",           "cccc0000101Snnnnddddvvvvvrr0mmmm") // v1
-INST(arm_ADC_rsr,       "ADC (rsr)",           "cccc0000101Snnnnddddssss0rr1mmmm") // v1
-INST(arm_ADD_imm,       "ADD (imm)",           "cccc0010100Snnnnddddrrrrvvvvvvvv") // v1
-INST(arm_ADD_reg,       "ADD (reg)",           "cccc0000100Snnnnddddvvvvvrr0mmmm") // v1
-INST(arm_ADD_rsr,       "ADD (rsr)",           "cccc0000100Snnnnddddssss0rr1mmmm") // v1
-INST(arm_AND_imm,       "AND (imm)",           "cccc0010000Snnnnddddrrrrvvvvvvvv") // v1
-INST(arm_AND_reg,       "AND (reg)",           "cccc0000000Snnnnddddvvvvvrr0mmmm") // v1
-INST(arm_AND_rsr,       "AND (rsr)",           "cccc0000000Snnnnddddssss0rr1mmmm") // v1
-INST(arm_BIC_imm,       "BIC (imm)",           "cccc0011110Snnnnddddrrrrvvvvvvvv") // v1
-INST(arm_BIC_reg,       "BIC (reg)",           "cccc0001110Snnnnddddvvvvvrr0mmmm") // v1
-INST(arm_BIC_rsr,       "BIC (rsr)",           "cccc0001110Snnnnddddssss0rr1mmmm") // v1
-INST(arm_CMN_imm,       "CMN (imm)",           "cccc00110111nnnn0000rrrrvvvvvvvv") // v1
-INST(arm_CMN_reg,       "CMN (reg)",           "cccc00010111nnnn0000vvvvvrr0mmmm") // v1
-INST(arm_CMN_rsr,       "CMN (rsr)",           "cccc00010111nnnn0000ssss0rr1mmmm") // v1
-INST(arm_CMP_imm,       "CMP (imm)",           "cccc00110101nnnn0000rrrrvvvvvvvv") // v1
-INST(arm_CMP_reg,       "CMP (reg)",           "cccc00010101nnnn0000vvvvvrr0mmmm") // v1
-INST(arm_CMP_rsr,       "CMP (rsr)",           "cccc00010101nnnn0000ssss0rr1mmmm") // v1
-INST(arm_EOR_imm,       "EOR (imm)",           "cccc0010001Snnnnddddrrrrvvvvvvvv") // v1
-INST(arm_EOR_reg,       "EOR (reg)",           "cccc0000001Snnnnddddvvvvvrr0mmmm") // v1
-INST(arm_EOR_rsr,       "EOR (rsr)",           "cccc0000001Snnnnddddssss0rr1mmmm") // v1
-INST(arm_MOV_imm,       "MOV (imm)",           "cccc0011101S0000ddddrrrrvvvvvvvv") // v1
-INST(arm_MOV_reg,       "MOV (reg)",           "cccc0001101S0000ddddvvvvvrr0mmmm") // v1
-INST(arm_MOV_rsr,       "MOV (rsr)",           "cccc0001101S0000ddddssss0rr1mmmm") // v1
-INST(arm_MVN_imm,       "MVN (imm)",           "cccc0011111S0000ddddrrrrvvvvvvvv") // v1
-INST(arm_MVN_reg,       "MVN (reg)",           "cccc0001111S0000ddddvvvvvrr0mmmm") // v1
-INST(arm_MVN_rsr,       "MVN (rsr)",           "cccc0001111S0000ddddssss0rr1mmmm") // v1
-INST(arm_ORR_imm,       "ORR (imm)",           "cccc0011100Snnnnddddrrrrvvvvvvvv") // v1
-INST(arm_ORR_reg,       "ORR (reg)",           "cccc0001100Snnnnddddvvvvvrr0mmmm") // v1
-INST(arm_ORR_rsr,       "ORR (rsr)",           "cccc0001100Snnnnddddssss0rr1mmmm") // v1
-INST(arm_RSB_imm,       "RSB (imm)",           "cccc0010011Snnnnddddrrrrvvvvvvvv") // v1
-INST(arm_RSB_reg,       "RSB (reg)",           "cccc0000011Snnnnddddvvvvvrr0mmmm") // v1
-INST(arm_RSB_rsr,       "RSB (rsr)",           "cccc0000011Snnnnddddssss0rr1mmmm") // v1
-INST(arm_RSC_imm,       "RSC (imm)",           "cccc0010111Snnnnddddrrrrvvvvvvvv") // v1
-INST(arm_RSC_reg,       "RSC (reg)",           "cccc0000111Snnnnddddvvvvvrr0mmmm") // v1
-INST(arm_RSC_rsr,       "RSC (rsr)",           "cccc0000111Snnnnddddssss0rr1mmmm") // v1
-INST(arm_SBC_imm,       "SBC (imm)",           "cccc0010110Snnnnddddrrrrvvvvvvvv") // v1
-INST(arm_SBC_reg,       "SBC (reg)",           "cccc0000110Snnnnddddvvvvvrr0mmmm") // v1
-INST(arm_SBC_rsr,       "SBC (rsr)",           "cccc0000110Snnnnddddssss0rr1mmmm") // v1
-INST(arm_SUB_imm,       "SUB (imm)",           "cccc0010010Snnnnddddrrrrvvvvvvvv") // v1
-INST(arm_SUB_reg,       "SUB (reg)",           "cccc0000010Snnnnddddvvvvvrr0mmmm") // v1
-INST(arm_SUB_rsr,       "SUB (rsr)",           "cccc0000010Snnnnddddssss0rr1mmmm") // v1
-INST(arm_TEQ_imm,       "TEQ (imm)",           "cccc00110011nnnn0000rrrrvvvvvvvv") // v1
-INST(arm_TEQ_reg,       "TEQ (reg)",           "cccc00010011nnnn0000vvvvvrr0mmmm") // v1
-INST(arm_TEQ_rsr,       "TEQ (rsr)",           "cccc00010011nnnn0000ssss0rr1mmmm") // v1
-INST(arm_TST_imm,       "TST (imm)",           "cccc00110001nnnn0000rrrrvvvvvvvv") // v1
-INST(arm_TST_reg,       "TST (reg)",           "cccc00010001nnnn0000vvvvvrr0mmmm") // v1
-INST(arm_TST_rsr,       "TST (rsr)",           "cccc00010001nnnn0000ssss0rr1mmmm") // v1
-
-// Exception Generating instructions
-INST(arm_BKPT,          "BKPT",                "cccc00010010vvvvvvvvvvvv0111vvvv") // v5
-INST(arm_SVC,           "SVC",                 "cccc1111vvvvvvvvvvvvvvvvvvvvvvvv") // v1
-INST(arm_UDF,           "UDF",                 "111001111111------------1111----")
-
-// Extension instructions
-INST(arm_SXTB,          "SXTB",                "cccc011010101111ddddrr000111mmmm") // v6
-INST(arm_SXTB16,        "SXTB16",              "cccc011010001111ddddrr000111mmmm") // v6
-INST(arm_SXTH,          "SXTH",                "cccc011010111111ddddrr000111mmmm") // v6
-INST(arm_SXTAB,         "SXTAB",               "cccc01101010nnnnddddrr000111mmmm") // v6
-INST(arm_SXTAB16,       "SXTAB16",             "cccc01101000nnnnddddrr000111mmmm") // v6
-INST(arm_SXTAH,         "SXTAH",               "cccc01101011nnnnddddrr000111mmmm") // v6
-INST(arm_UXTB,          "UXTB",                "cccc011011101111ddddrr000111mmmm") // v6
-INST(arm_UXTB16,        "UXTB16",              "cccc011011001111ddddrr000111mmmm") // v6
-INST(arm_UXTH,          "UXTH",                "cccc011011111111ddddrr000111mmmm") // v6
-INST(arm_UXTAB,         "UXTAB",               "cccc01101110nnnnddddrr000111mmmm") // v6
-INST(arm_UXTAB16,       "UXTAB16",             "cccc01101100nnnnddddrr000111mmmm") // v6
-INST(arm_UXTAH,         "UXTAH",               "cccc01101111nnnnddddrr000111mmmm") // v6
-
-// Hint instructions
-INST(arm_PLD_imm,       "PLD (imm)",           "11110101uz01nnnn1111iiiiiiiiiiii") // v5E for PLD; v7 for PLDW
-INST(arm_PLD_reg,       "PLD (reg)",           "11110111uz01nnnn1111iiiiitt0mmmm") // v5E for PLD; v7 for PLDW
-INST(arm_SEV,           "SEV",                 "----0011001000001111000000000100") // v6K
-INST(arm_SEVL,          "SEVL",                "----0011001000001111000000000101") // v8
-INST(arm_WFE,           "WFE",                 "----0011001000001111000000000010") // v6K
-INST(arm_WFI,           "WFI",                 "----0011001000001111000000000011") // v6K
-INST(arm_YIELD,         "YIELD",               "----0011001000001111000000000001") // v6K
-INST(arm_NOP,           "Reserved Hint",       "----0011001000001111------------")
+INST(arm_CLREX, "CLREX", "11110101011111111111000000011111")
+INST(arm_SETEND, "SETEND", "1111000100000001000000e000000000")
+INST(arm_DMB, "DMB", "1111010101111111111100000101oooo")
+INST(arm_DSB, "DSB", "1111010101111111111100000100oooo")
+INST(arm_ISB, "ISB", "1111010101111111111100000110oooo")
+INST(arm_SEV, "SEV", "----0011001000001111000000000100")
+INST(arm_SEVL, "SEVL", "----0011001000001111000000000101")
+INST(arm_WFE, "WFE", "----0011001000001111000000000010")
+INST(arm_WFI, "WFI", "----0011001000001111000000000011")
+INST(arm_YIELD, "YIELD", "----0011001000001111000000000001")
+INST(arm_NOP, "NOP", "----0011001000001111000000000000")
+INST(arm_RFE, "RFE", "1111100--0-1----0000101000000000")
+INST(arm_BLX_reg, "BLX (reg)", "cccc000100101111111111110011mmmm")
+INST(arm_BX, "BX", "cccc000100101111111111110001mmmm")
+INST(arm_BXJ, "BXJ", "cccc000100101111111111110010mmmm")
 INST(arm_NOP, "Reserved Hint", "----001100100000111100000000----")
-
-// Synchronization Primitive instructions
-INST(arm_CLREX,         "CLREX",               "11110101011111111111000000011111") // v6K
-INST(arm_SWP,           "SWP",                 "cccc00010000nnnntttt00001001uuuu") // v2S (v6: Deprecated)
-INST(arm_SWPB,          "SWPB",                "cccc00010100nnnntttt00001001uuuu") // v2S (v6: Deprecated)
-INST(arm_STL,           "STL",                 "cccc00011000nnnn111111001001tttt") // v8
-INST(arm_STLEX,         "STLEX",               "cccc00011000nnnndddd11101001tttt") // v8
-INST(arm_STREX,         "STREX",               "cccc00011000nnnndddd11111001mmmm") // v6
-INST(arm_LDA,           "LDA",                 "cccc00011001nnnndddd110010011111") // v8
-INST(arm_LDAEX,         "LDAEX",               "cccc00011001nnnndddd111010011111") // v8
-INST(arm_LDREX,         "LDREX",               "cccc00011001nnnndddd111110011111") // v6
-INST(arm_STLEXD,        "STLEXD",              "cccc00011010nnnndddd11101001mmmm") // v8
-INST(arm_STREXD,        "STREXD",              "cccc00011010nnnndddd11111001mmmm") // v6K
-INST(arm_LDAEXD,        "LDAEXD",              "cccc00011011nnnndddd111010011111") // v8
-INST(arm_LDREXD,        "LDREXD",              "cccc00011011nnnndddd111110011111") // v6K
-INST(arm_STLB,          "STLB",                "cccc00011100nnnn111111001001tttt") // v8
-INST(arm_STLEXB,        "STLEXB",              "cccc00011100nnnndddd11101001mmmm") // v8
-INST(arm_STREXB,        "STREXB",              "cccc00011100nnnndddd11111001mmmm") // v6K
-INST(arm_LDAB,          "LDAB",                "cccc00011101nnnndddd110010011111") // v8
-INST(arm_LDAEXB,        "LDAEXB",              "cccc00011101nnnndddd111010011111") // v8
-INST(arm_LDREXB,        "LDREXB",              "cccc00011101nnnndddd111110011111") // v6K
-INST(arm_STLH,          "STLH",                "cccc00011110nnnn111111001001mmmm") // v8
-INST(arm_STLEXH,        "STLEXH",              "cccc00011110nnnndddd11101001mmmm") // v8
-INST(arm_STREXH,        "STREXH",              "cccc00011110nnnndddd11111001mmmm") // v6K
-INST(arm_LDAH,          "LDAH",                "cccc00011111nnnndddd110010011111") // v8
-INST(arm_LDAEXH,        "LDAEXH",              "cccc00011111nnnndddd111010011111") // v8
-INST(arm_LDREXH,        "LDREXH",              "cccc00011111nnnndddd111110011111") // v6K
-
-// Load/Store instructions
-INST(arm_LDRBT,         "LDRBT (A1)",          "----0100-111--------------------") // v1
-INST(arm_LDRBT,         "LDRBT (A2)",          "----0110-111---------------0----") // v1
-INST(arm_LDRHT,         "LDRHT (A1)",          "----0000-111------------1011----") // v6T2
-INST(arm_LDRHT,         "LDRHT (A1)",          "----0000-1111111--------1011----") // v6T2
-INST(arm_LDRHT,         "LDRHT (A2)",          "----0000-011--------00001011----") // v6T2
-INST(arm_LDRSBT,        "LDRSBT (A1)",         "----0000-111------------1101----") // v6T2
-INST(arm_LDRSBT,        "LDRSBT (A2)",         "----0000-011--------00001101----") // v6T2
-INST(arm_LDRSHT,        "LDRSHT (A1)",         "----0000-111------------1111----") // v6T2
-INST(arm_LDRSHT,        "LDRSHT (A2)",         "----0000-011--------00001111----") // v6T2
-INST(arm_LDRT,          "LDRT (A1)",           "----0100-011--------------------") // v1
-INST(arm_LDRT,          "LDRT (A2)",           "----0110-011---------------0----") // v1
-INST(arm_STRBT,         "STRBT (A1)",          "----0100-110--------------------") // v1
-INST(arm_STRBT,         "STRBT (A2)",          "----0110-110---------------0----") // v1
-INST(arm_STRHT,         "STRHT (A1)",          "----0000-110------------1011----") // v6T2
-INST(arm_STRHT,         "STRHT (A2)",          "----0000-010--------00001011----") // v6T2
-INST(arm_STRT,          "STRT (A1)",           "----0100-010--------------------") // v1
-INST(arm_STRT,          "STRT (A2)",           "----0110-010---------------0----") // v1
-INST(arm_LDR_lit,       "LDR (lit)",           "cccc0101u0011111ttttvvvvvvvvvvvv") // v1
-INST(arm_LDR_imm,       "LDR (imm)",           "cccc010pu0w1nnnnttttvvvvvvvvvvvv") // v1
-INST(arm_LDR_reg,       "LDR (reg)",           "cccc011pu0w1nnnnttttvvvvvrr0mmmm") // v1
-INST(arm_LDRB_lit,      "LDRB (lit)",          "cccc0101u1011111ttttvvvvvvvvvvvv") // v1
-INST(arm_LDRB_imm,      "LDRB (imm)",          "cccc010pu1w1nnnnttttvvvvvvvvvvvv") // v1
-INST(arm_LDRB_reg,      "LDRB (reg)",          "cccc011pu1w1nnnnttttvvvvvrr0mmmm") // v1
-INST(arm_LDRD_lit,      "LDRD (lit)",          "cccc0001u1001111ttttvvvv1101vvvv") // v5E
-INST(arm_LDRD_imm,      "LDRD (imm)",          "cccc000pu1w0nnnnttttvvvv1101vvvv") // v5E
-INST(arm_LDRD_reg,      "LDRD (reg)",          "cccc000pu0w0nnnntttt00001101mmmm") // v5E
-INST(arm_LDRH_lit,      "LDRH (lit)",          "cccc000pu1w11111ttttvvvv1011vvvv") // v4
-INST(arm_LDRH_imm,      "LDRH (imm)",          "cccc000pu1w1nnnnttttvvvv1011vvvv") // v4
-INST(arm_LDRH_reg,      "LDRH (reg)",          "cccc000pu0w1nnnntttt00001011mmmm") // v4
-INST(arm_LDRSB_lit,     "LDRSB (lit)",         "cccc0001u1011111ttttvvvv1101vvvv") // v4
-INST(arm_LDRSB_imm,     "LDRSB (imm)",         "cccc000pu1w1nnnnttttvvvv1101vvvv") // v4
-INST(arm_LDRSB_reg,     "LDRSB (reg)",         "cccc000pu0w1nnnntttt00001101mmmm") // v4
-INST(arm_LDRSH_lit,     "LDRSH (lit)",         "cccc0001u1011111ttttvvvv1111vvvv") // v4
-INST(arm_LDRSH_imm,     "LDRSH (imm)",         "cccc000pu1w1nnnnttttvvvv1111vvvv") // v4
-INST(arm_LDRSH_reg,     "LDRSH (reg)",         "cccc000pu0w1nnnntttt00001111mmmm") // v4
-INST(arm_STR_imm,       "STR (imm)",           "cccc010pu0w0nnnnttttvvvvvvvvvvvv") // v1
-INST(arm_STR_reg,       "STR (reg)",           "cccc011pu0w0nnnnttttvvvvvrr0mmmm") // v1
-INST(arm_STRB_imm,      "STRB (imm)",          "cccc010pu1w0nnnnttttvvvvvvvvvvvv") // v1
-INST(arm_STRB_reg,      "STRB (reg)",          "cccc011pu1w0nnnnttttvvvvvrr0mmmm") // v1
-INST(arm_STRD_imm,      "STRD (imm)",          "cccc000pu1w0nnnnttttvvvv1111vvvv") // v5E
-INST(arm_STRD_reg,      "STRD (reg)",          "cccc000pu0w0nnnntttt00001111mmmm") // v5E
-INST(arm_STRH_imm,      "STRH (imm)",          "cccc000pu1w0nnnnttttvvvv1011vvvv") // v4
-INST(arm_STRH_reg,      "STRH (reg)",          "cccc000pu0w0nnnntttt00001011mmmm") // v4
-
-// Load/Store Multiple instructions
-INST(arm_LDM,           "LDM",                 "cccc100010w1nnnnxxxxxxxxxxxxxxxx") // v1
-INST(arm_LDMDA,         "LDMDA",               "cccc100000w1nnnnxxxxxxxxxxxxxxxx") // v1
-INST(arm_LDMDB,         "LDMDB",               "cccc100100w1nnnnxxxxxxxxxxxxxxxx") // v1
-INST(arm_LDMIB,         "LDMIB",               "cccc100110w1nnnnxxxxxxxxxxxxxxxx") // v1
-INST(arm_LDM_usr,       "LDM (usr reg)",       "----100--101--------------------") // v1
-INST(arm_LDM_eret,      "LDM (exce ret)",      "----100--1-1----1---------------") // v1
-INST(arm_STM,           "STM",                 "cccc100010w0nnnnxxxxxxxxxxxxxxxx") // v1
-INST(arm_STMDA,         "STMDA",               "cccc100000w0nnnnxxxxxxxxxxxxxxxx") // v1
-INST(arm_STMDB,         "STMDB",               "cccc100100w0nnnnxxxxxxxxxxxxxxxx") // v1
-INST(arm_STMIB,         "STMIB",               "cccc100110w0nnnnxxxxxxxxxxxxxxxx") // v1
-INST(arm_STM_usr,       "STM (usr reg)",       "----100--100--------------------") // v1
-
-// Miscellaneous instructions
-INST(arm_BFC,           "BFC",                 "cccc0111110vvvvvddddvvvvv0011111") // v6T2
-INST(arm_BFI,           "BFI",                 "cccc0111110vvvvvddddvvvvv001nnnn") // v6T2
-INST(arm_CLZ,           "CLZ",                 "cccc000101101111dddd11110001mmmm") // v5
-INST(arm_MOVT,          "MOVT",                "cccc00110100vvvvddddvvvvvvvvvvvv") // v6T2
-INST(arm_MOVW,          "MOVW",                "cccc00110000vvvvddddvvvvvvvvvvvv") // v6T2
-INST(arm_NOP,           "NOP",                 "----0011001000001111000000000000") // v6K
-INST(arm_SBFX,          "SBFX",                "cccc0111101wwwwwddddvvvvv101nnnn") // v6T2
-INST(arm_SEL,           "SEL",                 "cccc01101000nnnndddd11111011mmmm") // v6
-INST(arm_UBFX,          "UBFX",                "cccc0111111wwwwwddddvvvvv101nnnn") // v6T2
-
-// Unsigned Sum of Absolute Differences instructions
-INST(arm_USAD8,         "USAD8",               "cccc01111000dddd1111mmmm0001nnnn") // v6
-INST(arm_USADA8,        "USADA8",              "cccc01111000ddddaaaammmm0001nnnn") // v6
-
-// Packing instructions
-INST(arm_PKHBT,         "PKHBT",               "cccc01101000nnnnddddvvvvv001mmmm") // v6K
-INST(arm_PKHTB,         "PKHTB",               "cccc01101000nnnnddddvvvvv101mmmm") // v6K
-
-// Reversal instructions
-INST(arm_RBIT,          "RBIT",                "cccc011011111111dddd11110011mmmm") // v6T2
-INST(arm_REV,           "REV",                 "cccc011010111111dddd11110011mmmm") // v6
-INST(arm_REV16,         "REV16",               "cccc011010111111dddd11111011mmmm") // v6
-INST(arm_REVSH,         "REVSH",               "cccc011011111111dddd11111011mmmm") // v6
-
-// Saturation instructions
-INST(arm_SSAT,          "SSAT",                "cccc0110101vvvvvddddvvvvvr01nnnn") // v6
-INST(arm_SSAT16,        "SSAT16",              "cccc01101010vvvvdddd11110011nnnn") // v6
-INST(arm_USAT,          "USAT",                "cccc0110111vvvvvddddvvvvvr01nnnn") // v6
-INST(arm_USAT16,        "USAT16",              "cccc01101110vvvvdddd11110011nnnn") // v6
-
-// Divide instructions
-INST(arm_SDIV,          "SDIV",                "cccc01110001dddd1111mmmm0001nnnn") // v7a
-INST(arm_UDIV,          "UDIV",                "cccc01110011dddd1111mmmm0001nnnn") // v7a
-
-// Multiply (Normal) instructions
-INST(arm_MLA,           "MLA",                 "cccc0000001Sddddaaaammmm1001nnnn") // v2
-INST(arm_MLS,           "MLS",                 "cccc00000110ddddaaaammmm1001nnnn") // v6T2
-INST(arm_MUL,           "MUL",                 "cccc0000000Sdddd0000mmmm1001nnnn") // v2
-
-// Multiply (Long) instructions
-INST(arm_SMLAL,         "SMLAL",               "cccc0000111Sddddaaaammmm1001nnnn") // v3M
-INST(arm_SMULL,         "SMULL",               "cccc0000110Sddddaaaammmm1001nnnn") // v3M
-INST(arm_UMAAL,         "UMAAL",               "cccc00000100ddddaaaammmm1001nnnn") // v6
-INST(arm_UMLAL,         "UMLAL",               "cccc0000101Sddddaaaammmm1001nnnn") // v3M
-INST(arm_UMULL,         "UMULL",               "cccc0000100Sddddaaaammmm1001nnnn") // v3M
-
-// Multiply (Halfword) instructions
-INST(arm_SMLALxy,       "SMLALXY",             "cccc00010100ddddaaaammmm1xy0nnnn") // v5xP
-INST(arm_SMLAxy,        "SMLAXY",              "cccc00010000ddddaaaammmm1xy0nnnn") // v5xP
-INST(arm_SMULxy,        "SMULXY",              "cccc00010110dddd0000mmmm1xy0nnnn") // v5xP
-
-// Multiply (Word by Halfword) instructions
-INST(arm_SMLAWy,        "SMLAWY",              "cccc00010010ddddaaaammmm1y00nnnn") // v5xP
-INST(arm_SMULWy,        "SMULWY",              "cccc00010010dddd0000mmmm1y10nnnn") // v5xP
-
-// Multiply (Most Significant Word) instructions
-INST(arm_SMMUL,         "SMMUL",               "cccc01110101dddd1111mmmm00R1nnnn") // v6
-INST(arm_SMMLA,         "SMMLA",               "cccc01110101ddddaaaammmm00R1nnnn") // v6
-INST(arm_SMMLS,         "SMMLS",               "cccc01110101ddddaaaammmm11R1nnnn") // v6
-
-// Multiply (Dual) instructions
-INST(arm_SMLAD,         "SMLAD",               "cccc01110000ddddaaaammmm00M1nnnn") // v6
-INST(arm_SMLALD,        "SMLALD",              "cccc01110100ddddaaaammmm00M1nnnn") // v6
-INST(arm_SMLSD,         "SMLSD",               "cccc01110000ddddaaaammmm01M1nnnn") // v6
-INST(arm_SMLSLD,        "SMLSLD",              "cccc01110100ddddaaaammmm01M1nnnn") // v6
-INST(arm_SMUAD,         "SMUAD",               "cccc01110000dddd1111mmmm00M1nnnn") // v6
-INST(arm_SMUSD,         "SMUSD",               "cccc01110000dddd1111mmmm01M1nnnn") // v6
-
-// Parallel Add/Subtract (Modulo) instructions
-INST(arm_SADD8,         "SADD8",               "cccc01100001nnnndddd11111001mmmm") // v6
-INST(arm_SADD16,        "SADD16",              "cccc01100001nnnndddd11110001mmmm") // v6
-INST(arm_SASX,          "SASX",                "cccc01100001nnnndddd11110011mmmm") // v6
-INST(arm_SSAX,          "SSAX",                "cccc01100001nnnndddd11110101mmmm") // v6
-INST(arm_SSUB8,         "SSUB8",               "cccc01100001nnnndddd11111111mmmm") // v6
-INST(arm_SSUB16,        "SSUB16",              "cccc01100001nnnndddd11110111mmmm") // v6
-INST(arm_UADD8,         "UADD8",               "cccc01100101nnnndddd11111001mmmm") // v6
-INST(arm_UADD16,        "UADD16",              "cccc01100101nnnndddd11110001mmmm") // v6
-INST(arm_UASX,          "UASX",                "cccc01100101nnnndddd11110011mmmm") // v6
-INST(arm_USAX,          "USAX",                "cccc01100101nnnndddd11110101mmmm") // v6
-INST(arm_USUB8,         "USUB8",               "cccc01100101nnnndddd11111111mmmm") // v6
-INST(arm_USUB16,        "USUB16",              "cccc01100101nnnndddd11110111mmmm") // v6
-
-// Parallel Add/Subtract (Saturating) instructions
-INST(arm_QADD8,         "QADD8",               "cccc01100010nnnndddd11111001mmmm") // v6
-INST(arm_QADD16,        "QADD16",              "cccc01100010nnnndddd11110001mmmm") // v6
-INST(arm_QASX,          "QASX",                "cccc01100010nnnndddd11110011mmmm") // v6
-INST(arm_QSAX,          "QSAX",                "cccc01100010nnnndddd11110101mmmm") // v6
-INST(arm_QSUB8,         "QSUB8",               "cccc01100010nnnndddd11111111mmmm") // v6
-INST(arm_QSUB16,        "QSUB16",              "cccc01100010nnnndddd11110111mmmm") // v6
-INST(arm_UQADD8,        "UQADD8",              "cccc01100110nnnndddd11111001mmmm") // v6
-INST(arm_UQADD16,       "UQADD16",             "cccc01100110nnnndddd11110001mmmm") // v6
-INST(arm_UQASX,         "UQASX",               "cccc01100110nnnndddd11110011mmmm") // v6
-INST(arm_UQSAX,         "UQSAX",               "cccc01100110nnnndddd11110101mmmm") // v6
-INST(arm_UQSUB8,        "UQSUB8",              "cccc01100110nnnndddd11111111mmmm") // v6
-INST(arm_UQSUB16,       "UQSUB16",             "cccc01100110nnnndddd11110111mmmm") // v6
-
-// Parallel Add/Subtract (Halving) instructions
-INST(arm_SHADD8,        "SHADD8",              "cccc01100011nnnndddd11111001mmmm") // v6
-INST(arm_SHADD16,       "SHADD16",             "cccc01100011nnnndddd11110001mmmm") // v6
-INST(arm_SHASX,         "SHASX",               "cccc01100011nnnndddd11110011mmmm") // v6
-INST(arm_SHSAX,         "SHSAX",               "cccc01100011nnnndddd11110101mmmm") // v6
-INST(arm_SHSUB8,        "SHSUB8",              "cccc01100011nnnndddd11111111mmmm") // v6
-INST(arm_SHSUB16,       "SHSUB16",             "cccc01100011nnnndddd11110111mmmm") // v6
-INST(arm_UHADD8,        "UHADD8",              "cccc01100111nnnndddd11111001mmmm") // v6
-INST(arm_UHADD16,       "UHADD16",             "cccc01100111nnnndddd11110001mmmm") // v6
-INST(arm_UHASX,         "UHASX",               "cccc01100111nnnndddd11110011mmmm") // v6
-INST(arm_UHSAX,         "UHSAX",               "cccc01100111nnnndddd11110101mmmm") // v6
-INST(arm_UHSUB8,        "UHSUB8",              "cccc01100111nnnndddd11111111mmmm") // v6
-INST(arm_UHSUB16,       "UHSUB16",             "cccc01100111nnnndddd11110111mmmm") // v6
-
-// Saturated Add/Subtract instructions
-INST(arm_QADD,          "QADD",                "cccc00010000nnnndddd00000101mmmm") // v5xP
-INST(arm_QSUB,          "QSUB",                "cccc00010010nnnndddd00000101mmmm") // v5xP
-INST(arm_QDADD,         "QDADD",               "cccc00010100nnnndddd00000101mmmm") // v5xP
-INST(arm_QDSUB,         "QDSUB",               "cccc00010110nnnndddd00000101mmmm") // v5xP
-
-// Status Register Access instructions
-INST(arm_CPS,           "CPS",                 "111100010000---00000000---0-----") // v6
-INST(arm_SETEND,        "SETEND",              "1111000100000001000000e000000000") // v6
-INST(arm_MRS,           "MRS",                 "cccc000100001111dddd000000000000") // v3
-INST(arm_MSR_imm,       "MSR (imm)",           "cccc00110010mmmm1111rrrrvvvvvvvv") // v3
-INST(arm_MSR_reg,       "MSR (reg)",           "cccc00010010mmmm111100000000nnnn") // v3
-INST(arm_RFE,           "RFE",                 "1111100--0-1----0000101000000000") // v6
-INST(arm_SRS,           "SRS",                 "1111100--1-0110100000101000-----") // v6
+INST(arm_MRS, "MRS", "cccc000100001111dddd000000000000")
+INST(arm_SRS, "SRS", "1111100--1-0110100000101000-----")
+INST(arm_CPS, "CPS", "111100010000---00000000---0-----")
+INST(arm_STL, "STL", "cccc00011000nnnn111111001001tttt")
+INST(arm_LDA, "LDA", "cccc00011001nnnndddd110010011111")
+INST(arm_LDAEX, "LDAEX", "cccc00011001nnnndddd111010011111")
+INST(arm_LDREX, "LDREX", "cccc00011001nnnndddd111110011111")
+INST(arm_LDAEXD, "LDAEXD", "cccc00011011nnnndddd111010011111")
+INST(arm_LDREXD, "LDREXD", "cccc00011011nnnndddd111110011111")
+INST(arm_STLB, "STLB", "cccc00011100nnnn111111001001tttt")
+INST(arm_LDAB, "LDAB", "cccc00011101nnnndddd110010011111")
+INST(arm_LDAEXB, "LDAEXB", "cccc00011101nnnndddd111010011111")
+INST(arm_LDREXB, "LDREXB", "cccc00011101nnnndddd111110011111")
+INST(arm_STLH, "STLH", "cccc00011110nnnn111111001001mmmm")
+INST(arm_LDAH, "LDAH", "cccc00011111nnnndddd110010011111")
+INST(arm_LDAEXH, "LDAEXH", "cccc00011111nnnndddd111010011111")
+INST(arm_LDREXH, "LDREXH", "cccc00011111nnnndddd111110011111")
+INST(arm_CLZ, "CLZ", "cccc000101101111dddd11110001mmmm")
+INST(arm_RBIT, "RBIT", "cccc011011111111dddd11110011mmmm")
+INST(arm_REV, "REV", "cccc011010111111dddd11110011mmmm")
+INST(arm_REV16, "REV16", "cccc011010111111dddd11111011mmmm")
+INST(arm_REVSH, "REVSH", "cccc011011111111dddd11111011mmmm")
+INST(arm_MSR_reg, "MSR (reg)", "cccc00010010mmmm111100000000nnnn")
+INST(arm_SXTB, "SXTB", "cccc011010101111ddddrr000111mmmm")
+INST(arm_SXTB16, "SXTB16", "cccc011010001111ddddrr000111mmmm")
+INST(arm_SXTH, "SXTH", "cccc011010111111ddddrr000111mmmm")
+INST(arm_UXTB, "UXTB", "cccc011011101111ddddrr000111mmmm")
+INST(arm_UXTB16, "UXTB16", "cccc011011001111ddddrr000111mmmm")
+INST(arm_UXTH, "UXTH", "cccc011011111111ddddrr000111mmmm")
+INST(arm_UDF, "UDF", "111001111111------------1111----")
+INST(arm_NOP, "Reserved Hint", "----0011001000001111------------")
+INST(arm_SWP, "SWP", "cccc00010000nnnntttt00001001uuuu")
+INST(arm_SWPB, "SWPB", "cccc00010100nnnntttt00001001uuuu")
+INST(arm_STLEX, "STLEX", "cccc00011000nnnndddd11101001tttt")
+INST(arm_STREX, "STREX", "cccc00011000nnnndddd11111001mmmm")
+INST(arm_STLEXD, "STLEXD", "cccc00011010nnnndddd11101001mmmm")
+INST(arm_STREXD, "STREXD", "cccc00011010nnnndddd11111001mmmm")
+INST(arm_STLEXB, "STLEXB", "cccc00011100nnnndddd11101001mmmm")
+INST(arm_STREXB, "STREXB", "cccc00011100nnnndddd11111001mmmm")
+INST(arm_STLEXH, "STLEXH", "cccc00011110nnnndddd11101001mmmm")
+INST(arm_STREXH, "STREXH", "cccc00011110nnnndddd11111001mmmm")
+INST(arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm")
+INST(arm_USAD8, "USAD8", "cccc01111000dddd1111mmmm0001nnnn")
+INST(arm_SSAT16, "SSAT16", "cccc01101010vvvvdddd11110011nnnn")
+INST(arm_USAT16, "USAT16", "cccc01101110vvvvdddd11110011nnnn")
+INST(arm_SDIV, "SDIV", "cccc01110001dddd1111mmmm0001nnnn")
+INST(arm_UDIV, "UDIV", "cccc01110011dddd1111mmmm0001nnnn")
+INST(arm_SADD8, "SADD8", "cccc01100001nnnndddd11111001mmmm")
+INST(arm_SADD16, "SADD16", "cccc01100001nnnndddd11110001mmmm")
+INST(arm_SASX, "SASX", "cccc01100001nnnndddd11110011mmmm")
+INST(arm_SSAX, "SSAX", "cccc01100001nnnndddd11110101mmmm")
+INST(arm_SSUB8, "SSUB8", "cccc01100001nnnndddd11111111mmmm")
+INST(arm_SSUB16, "SSUB16", "cccc01100001nnnndddd11110111mmmm")
+INST(arm_UADD8, "UADD8", "cccc01100101nnnndddd11111001mmmm")
+INST(arm_UADD16, "UADD16", "cccc01100101nnnndddd11110001mmmm")
+INST(arm_UASX, "UASX", "cccc01100101nnnndddd11110011mmmm")
+INST(arm_USAX, "USAX", "cccc01100101nnnndddd11110101mmmm")
+INST(arm_USUB8, "USUB8", "cccc01100101nnnndddd11111111mmmm")
+INST(arm_USUB16, "USUB16", "cccc01100101nnnndddd11110111mmmm")
+INST(arm_QADD8, "QADD8", "cccc01100010nnnndddd11111001mmmm")
+INST(arm_QADD16, "QADD16", "cccc01100010nnnndddd11110001mmmm")
+INST(arm_QASX, "QASX", "cccc01100010nnnndddd11110011mmmm")
+INST(arm_QSAX, "QSAX", "cccc01100010nnnndddd11110101mmmm")
+INST(arm_QSUB8, "QSUB8", "cccc01100010nnnndddd11111111mmmm")
+INST(arm_QSUB16, "QSUB16", "cccc01100010nnnndddd11110111mmmm")
+INST(arm_UQADD8, "UQADD8", "cccc01100110nnnndddd11111001mmmm")
+INST(arm_UQADD16, "UQADD16", "cccc01100110nnnndddd11110001mmmm")
+INST(arm_UQASX, "UQASX", "cccc01100110nnnndddd11110011mmmm")
+INST(arm_UQSAX, "UQSAX", "cccc01100110nnnndddd11110101mmmm")
+INST(arm_UQSUB8, "UQSUB8", "cccc01100110nnnndddd11111111mmmm")
+INST(arm_UQSUB16, "UQSUB16", "cccc01100110nnnndddd11110111mmmm")
+INST(arm_SHADD8, "SHADD8", "cccc01100011nnnndddd11111001mmmm")
+INST(arm_SHADD16, "SHADD16", "cccc01100011nnnndddd11110001mmmm")
+INST(arm_SHASX, "SHASX", "cccc01100011nnnndddd11110011mmmm")
+INST(arm_SHSAX, "SHSAX", "cccc01100011nnnndddd11110101mmmm")
+INST(arm_SHSUB8, "SHSUB8", "cccc01100011nnnndddd11111111mmmm")
+INST(arm_SHSUB16, "SHSUB16", "cccc01100011nnnndddd11110111mmmm")
+INST(arm_UHADD8, "UHADD8", "cccc01100111nnnndddd11111001mmmm")
+INST(arm_UHADD16, "UHADD16", "cccc01100111nnnndddd11110001mmmm")
+INST(arm_UHASX, "UHASX", "cccc01100111nnnndddd11110011mmmm")
+INST(arm_UHSAX, "UHSAX", "cccc01100111nnnndddd11110101mmmm")
+INST(arm_UHSUB8, "UHSUB8", "cccc01100111nnnndddd11111111mmmm")
+INST(arm_UHSUB16, "UHSUB16", "cccc01100111nnnndddd11110111mmmm")
+INST(arm_QADD, "QADD", "cccc00010000nnnndddd00000101mmmm")
+INST(arm_QSUB, "QSUB", "cccc00010010nnnndddd00000101mmmm")
+INST(arm_QDADD, "QDADD", "cccc00010100nnnndddd00000101mmmm")
+INST(arm_QDSUB, "QDSUB", "cccc00010110nnnndddd00000101mmmm")
+INST(arm_PLD_reg, "PLD (reg)", "11110111uz01nnnn1111iiiiitt0mmmm")
+INST(arm_LDRHT, "LDRHT (A1)", "----0000-1111111--------1011----")
+INST(arm_LDRHT, "LDRHT (A2)", "----0000-011--------00001011----")
+INST(arm_LDRSBT, "LDRSBT (A2)", "----0000-011--------00001101----")
+INST(arm_LDRSHT, "LDRSHT (A2)", "----0000-011--------00001111----")
+INST(arm_STRHT, "STRHT (A2)", "----0000-010--------00001011----")
+INST(arm_LDRD_lit, "LDRD (lit)", "cccc0001u1001111ttttvvvv1101vvvv")
+INST(arm_LDRSB_lit, "LDRSB (lit)", "cccc0001u1011111ttttvvvv1101vvvv")
+INST(arm_LDRSH_lit, "LDRSH (lit)", "cccc0001u1011111ttttvvvv1111vvvv")
+INST(arm_MUL, "MUL", "cccc0000000Sdddd0000mmmm1001nnnn")
+INST(arm_SMULWy, "SMULWY", "cccc00010010dddd0000mmmm1y10nnnn")
+INST(arm_SMMUL, "SMMUL", "cccc01110101dddd1111mmmm00R1nnnn")
+INST(arm_SMUAD, "SMUAD", "cccc01110000dddd1111mmmm00M1nnnn")
+INST(arm_SMUSD, "SMUSD", "cccc01110000dddd1111mmmm01M1nnnn")
+INST(arm_CRC32, "CRC32", "cccc00010zz0nnnndddd00000100mmmm")
+INST(arm_CRC32C, "CRC32C", "cccc00010zz0nnnndddd00100100mmmm")
+INST(arm_CMN_rsr, "CMN (rsr)", "cccc00010111nnnn0000ssss0rr1mmmm")
+INST(arm_CMP_rsr, "CMP (rsr)", "cccc00010101nnnn0000ssss0rr1mmmm")
+INST(arm_TEQ_rsr, "TEQ (rsr)", "cccc00010011nnnn0000ssss0rr1mmmm")
+INST(arm_TST_rsr, "TST (rsr)", "cccc00010001nnnn0000ssss0rr1mmmm")
+INST(arm_SXTAB, "SXTAB", "cccc01101010nnnnddddrr000111mmmm")
+INST(arm_SXTAB16, "SXTAB16", "cccc01101000nnnnddddrr000111mmmm")
+INST(arm_SXTAH, "SXTAH", "cccc01101011nnnnddddrr000111mmmm")
+INST(arm_UXTAB, "UXTAB", "cccc01101110nnnnddddrr000111mmmm")
+INST(arm_UXTAB16, "UXTAB16", "cccc01101100nnnnddddrr000111mmmm")
+INST(arm_UXTAH, "UXTAH", "cccc01101111nnnnddddrr000111mmmm")
+INST(arm_PLD_imm, "PLD (imm)", "11110101uz01nnnn1111iiiiiiiiiiii")
+INST(arm_BFC, "BFC", "cccc0111110vvvvvddddvvvvv0011111")
+INST(arm_SMULxy, "SMULXY", "cccc00010110dddd0000mmmm1xy0nnnn")
+INST(arm_CMN_reg, "CMN (reg)", "cccc00010111nnnn0000vvvvvrr0mmmm")
+INST(arm_CMP_reg, "CMP (reg)", "cccc00010101nnnn0000vvvvvrr0mmmm")
+INST(arm_MOV_rsr, "MOV (rsr)", "cccc0001101S0000ddddssss0rr1mmmm")
+INST(arm_MVN_rsr, "MVN (rsr)", "cccc0001111S0000ddddssss0rr1mmmm")
+INST(arm_TEQ_reg, "TEQ (reg)", "cccc00010011nnnn0000vvvvvrr0mmmm")
+INST(arm_TST_reg, "TST (reg)", "cccc00010001nnnn0000vvvvvrr0mmmm")
+INST(arm_LDRD_reg, "LDRD (reg)", "cccc000pu0w0nnnntttt00001101mmmm")
+INST(arm_LDRH_lit, "LDRH (lit)", "cccc000pu1w11111ttttvvvv1011vvvv")
+INST(arm_LDRH_reg, "LDRH (reg)", "cccc000pu0w1nnnntttt00001011mmmm")
+INST(arm_LDRSB_reg, "LDRSB (reg)", "cccc000pu0w1nnnntttt00001101mmmm")
+INST(arm_LDRSH_reg, "LDRSH (reg)", "cccc000pu0w1nnnntttt00001111mmmm")
+INST(arm_STRD_reg, "STRD (reg)", "cccc000pu0w0nnnntttt00001111mmmm")
+INST(arm_STRH_reg, "STRH (reg)", "cccc000pu0w0nnnntttt00001011mmmm")
+INST(arm_CMN_imm, "CMN (imm)", "cccc00110111nnnn0000rrrrvvvvvvvv")
+INST(arm_CMP_imm, "CMP (imm)", "cccc00110101nnnn0000rrrrvvvvvvvv")
+INST(arm_MOV_reg, "MOV (reg)", "cccc0001101S0000ddddvvvvvrr0mmmm")
+INST(arm_MVN_reg, "MVN (reg)", "cccc0001111S0000ddddvvvvvrr0mmmm")
+INST(arm_TEQ_imm, "TEQ (imm)", "cccc00110011nnnn0000rrrrvvvvvvvv")
+INST(arm_TST_imm, "TST (imm)", "cccc00110001nnnn0000rrrrvvvvvvvv")
+INST(arm_BKPT, "BKPT", "cccc00010010vvvvvvvvvvvv0111vvvv")
+INST(arm_USADA8, "USADA8", "cccc01111000ddddaaaammmm0001nnnn")
+INST(arm_MLS, "MLS", "cccc00000110ddddaaaammmm1001nnnn")
+INST(arm_UMAAL, "UMAAL", "cccc00000100ddddaaaammmm1001nnnn")
+INST(arm_MSR_imm, "MSR (imm)", "cccc00110010mmmm1111rrrrvvvvvvvv")
+INST(arm_MOV_imm, "MOV (imm)", "cccc0011101S0000ddddrrrrvvvvvvvv")
+INST(arm_MVN_imm, "MVN (imm)", "cccc0011111S0000ddddrrrrvvvvvvvv")
+INST(arm_LDRHT, "LDRHT (A1)", "----0000-111------------1011----")
+INST(arm_LDRSBT, "LDRSBT (A1)", "----0000-111------------1101----")
+INST(arm_LDRSHT, "LDRSHT (A1)", "----0000-111------------1111----")
+INST(arm_STRHT, "STRHT (A1)", "----0000-110------------1011----")
+INST(arm_LDR_lit, "LDR (lit)", "cccc0101u0011111ttttvvvvvvvvvvvv")
+INST(arm_LDRB_lit, "LDRB (lit)", "cccc0101u1011111ttttvvvvvvvvvvvv")
+INST(arm_PKHBT, "PKHBT", "cccc01101000nnnnddddvvvvv001mmmm")
+INST(arm_PKHTB, "PKHTB", "cccc01101000nnnnddddvvvvv101mmmm")
+INST(arm_MLA, "MLA", "cccc0000001Sddddaaaammmm1001nnnn")
+INST(arm_SMLAL, "SMLAL", "cccc0000111Sddddaaaammmm1001nnnn")
+INST(arm_SMULL, "SMULL", "cccc0000110Sddddaaaammmm1001nnnn")
+INST(arm_UMLAL, "UMLAL", "cccc0000101Sddddaaaammmm1001nnnn")
+INST(arm_UMULL, "UMULL", "cccc0000100Sddddaaaammmm1001nnnn")
+INST(arm_SMLAWy, "SMLAWY", "cccc00010010ddddaaaammmm1y00nnnn")
+INST(arm_SMMLA, "SMMLA", "cccc01110101ddddaaaammmm00R1nnnn")
+INST(arm_SMMLS, "SMMLS", "cccc01110101ddddaaaammmm11R1nnnn")
+INST(arm_SMLAD, "SMLAD", "cccc01110000ddddaaaammmm00M1nnnn")
+INST(arm_SMLALD, "SMLALD", "cccc01110100ddddaaaammmm00M1nnnn")
+INST(arm_SMLSD, "SMLSD", "cccc01110000ddddaaaammmm01M1nnnn")
+INST(arm_SMLSLD, "SMLSLD", "cccc01110100ddddaaaammmm01M1nnnn")
+INST(arm_BFI, "BFI", "cccc0111110vvvvvddddvvvvv001nnnn")
+INST(arm_SBFX, "SBFX", "cccc0111101wwwwwddddvvvvv101nnnn")
+INST(arm_UBFX, "UBFX", "cccc0111111wwwwwddddvvvvv101nnnn")
+INST(arm_SMLALxy, "SMLALXY", "cccc00010100ddddaaaammmm1xy0nnnn")
+INST(arm_SMLAxy, "SMLAXY", "cccc00010000ddddaaaammmm1xy0nnnn")
+INST(arm_ADC_rsr, "ADC (rsr)", "cccc0000101Snnnnddddssss0rr1mmmm")
+INST(arm_ADD_rsr, "ADD (rsr)", "cccc0000100Snnnnddddssss0rr1mmmm")
+INST(arm_AND_rsr, "AND (rsr)", "cccc0000000Snnnnddddssss0rr1mmmm")
+INST(arm_BIC_rsr, "BIC (rsr)", "cccc0001110Snnnnddddssss0rr1mmmm")
+INST(arm_EOR_rsr, "EOR (rsr)", "cccc0000001Snnnnddddssss0rr1mmmm")
+INST(arm_ORR_rsr, "ORR (rsr)", "cccc0001100Snnnnddddssss0rr1mmmm")
+INST(arm_RSB_rsr, "RSB (rsr)", "cccc0000011Snnnnddddssss0rr1mmmm")
+INST(arm_RSC_rsr, "RSC (rsr)", "cccc0000111Snnnnddddssss0rr1mmmm")
+INST(arm_SBC_rsr, "SBC (rsr)", "cccc0000110Snnnnddddssss0rr1mmmm")
+INST(arm_SUB_rsr, "SUB (rsr)", "cccc0000010Snnnnddddssss0rr1mmmm")
+INST(arm_LDRD_imm, "LDRD (imm)", "cccc000pu1w0nnnnttttvvvv1101vvvv")
+INST(arm_LDRH_imm, "LDRH (imm)", "cccc000pu1w1nnnnttttvvvv1011vvvv")
+INST(arm_LDRSB_imm, "LDRSB (imm)", "cccc000pu1w1nnnnttttvvvv1101vvvv")
+INST(arm_LDRSH_imm, "LDRSH (imm)", "cccc000pu1w1nnnnttttvvvv1111vvvv")
+INST(arm_STRD_imm, "STRD (imm)", "cccc000pu1w0nnnnttttvvvv1111vvvv")
+INST(arm_STRH_imm, "STRH (imm)", "cccc000pu1w0nnnnttttvvvv1011vvvv")
+INST(arm_SSAT, "SSAT", "cccc0110101vvvvvddddvvvvvr01nnnn")
+INST(arm_USAT, "USAT", "cccc0110111vvvvvddddvvvvvr01nnnn")
+INST(arm_MCRR, "MCRR", "cccc11000100uuuuttttppppooooMMMM")
+INST(arm_MRRC, "MRRC", "cccc11000101uuuuttttppppooooMMMM")
+INST(arm_ADC_reg, "ADC (reg)", "cccc0000101Snnnnddddvvvvvrr0mmmm")
+INST(arm_ADD_reg, "ADD (reg)", "cccc0000100Snnnnddddvvvvvrr0mmmm")
+INST(arm_AND_reg, "AND (reg)", "cccc0000000Snnnnddddvvvvvrr0mmmm")
+INST(arm_BIC_reg, "BIC (reg)", "cccc0001110Snnnnddddvvvvvrr0mmmm")
+INST(arm_EOR_reg, "EOR (reg)", "cccc0000001Snnnnddddvvvvvrr0mmmm")
+INST(arm_ORR_reg, "ORR (reg)", "cccc0001100Snnnnddddvvvvvrr0mmmm")
+INST(arm_RSB_reg, "RSB (reg)", "cccc0000011Snnnnddddvvvvvrr0mmmm")
+INST(arm_RSC_reg, "RSC (reg)", "cccc0000111Snnnnddddvvvvvrr0mmmm")
+INST(arm_SBC_reg, "SBC (reg)", "cccc0000110Snnnnddddvvvvvrr0mmmm")
+INST(arm_SUB_reg, "SUB (reg)", "cccc0000010Snnnnddddvvvvvrr0mmmm")
+INST(arm_LDRBT, "LDRBT (A2)", "----0110-111---------------0----")
+INST(arm_LDRT, "LDRT (A2)", "----0110-011---------------0----")
+INST(arm_STRBT, "STRBT (A2)", "----0110-110---------------0----")
+INST(arm_STRT, "STRT (A2)", "----0110-010---------------0----")
+INST(arm_MOVT, "MOVT", "cccc00110100vvvvddddvvvvvvvvvvvv")
+INST(arm_MOVW, "MOVW", "cccc00110000vvvvddddvvvvvvvvvvvv")
+INST(arm_BLX_imm, "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv")
+INST(arm_ADC_imm, "ADC (imm)", "cccc0010101Snnnnddddrrrrvvvvvvvv")
+INST(arm_ADD_imm, "ADD (imm)", "cccc0010100Snnnnddddrrrrvvvvvvvv")
+INST(arm_AND_imm, "AND (imm)", "cccc0010000Snnnnddddrrrrvvvvvvvv")
+INST(arm_BIC_imm, "BIC (imm)", "cccc0011110Snnnnddddrrrrvvvvvvvv")
+INST(arm_EOR_imm, "EOR (imm)", "cccc0010001Snnnnddddrrrrvvvvvvvv")
+INST(arm_ORR_imm, "ORR (imm)", "cccc0011100Snnnnddddrrrrvvvvvvvv")
+INST(arm_RSB_imm, "RSB (imm)", "cccc0010011Snnnnddddrrrrvvvvvvvv")
+INST(arm_RSC_imm, "RSC (imm)", "cccc0010111Snnnnddddrrrrvvvvvvvv")
+INST(arm_SBC_imm, "SBC (imm)", "cccc0010110Snnnnddddrrrrvvvvvvvv")
+INST(arm_SUB_imm, "SUB (imm)", "cccc0010010Snnnnddddrrrrvvvvvvvv")
+INST(arm_LDRBT, "LDRBT (A1)", "----0100-111--------------------")
+INST(arm_LDRT, "LDRT (A1)", "----0100-011--------------------")
+INST(arm_STRBT, "STRBT (A1)", "----0100-110--------------------")
+INST(arm_STRT, "STRT (A1)", "----0100-010--------------------")
+INST(arm_LDM, "LDM", "cccc100010w1nnnnxxxxxxxxxxxxxxxx")
+INST(arm_LDMDA, "LDMDA", "cccc100000w1nnnnxxxxxxxxxxxxxxxx")
+INST(arm_LDMDB, "LDMDB", "cccc100100w1nnnnxxxxxxxxxxxxxxxx")
+INST(arm_LDMIB, "LDMIB", "cccc100110w1nnnnxxxxxxxxxxxxxxxx")
+INST(arm_STM, "STM", "cccc100010w0nnnnxxxxxxxxxxxxxxxx")
+INST(arm_STMDA, "STMDA", "cccc100000w0nnnnxxxxxxxxxxxxxxxx")
+INST(arm_STMDB, "STMDB", "cccc100100w0nnnnxxxxxxxxxxxxxxxx")
+INST(arm_STMIB, "STMIB", "cccc100110w0nnnnxxxxxxxxxxxxxxxx")
+INST(arm_MCR, "MCR", "cccc1110ooo0NNNNttttppppooo1MMMM")
+INST(arm_MRC, "MRC", "cccc1110ooo1NNNNttttppppooo1MMMM")
+INST(arm_LDR_reg, "LDR (reg)", "cccc011pu0w1nnnnttttvvvvvrr0mmmm")
+INST(arm_LDRB_reg, "LDRB (reg)", "cccc011pu1w1nnnnttttvvvvvrr0mmmm")
+INST(arm_STR_reg, "STR (reg)", "cccc011pu0w0nnnnttttvvvvvrr0mmmm")
+INST(arm_STRB_reg, "STRB (reg)", "cccc011pu1w0nnnnttttvvvvvrr0mmmm")
+INST(arm_LDM_usr, "LDM (usr reg)", "----100--101--------------------")
+INST(arm_LDM_eret, "LDM (exce ret)", "----100--1-1----1---------------")
+INST(arm_STM_usr, "STM (usr reg)", "----100--100--------------------")
+INST(arm_CDP, "CDP", "cccc1110ooooNNNNDDDDppppooo0MMMM")
+INST(arm_LDR_imm, "LDR (imm)", "cccc010pu0w1nnnnttttvvvvvvvvvvvv")
+INST(arm_LDRB_imm, "LDRB (imm)", "cccc010pu1w1nnnnttttvvvvvvvvvvvv")
+INST(arm_STR_imm, "STR (imm)", "cccc010pu0w0nnnnttttvvvvvvvvvvvv")
+INST(arm_STRB_imm, "STRB (imm)", "cccc010pu1w0nnnnttttvvvvvvvvvvvv")
+INST(arm_B, "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv")
+INST(arm_BL, "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv")
+INST(arm_LDC, "LDC", "cccc110pudw1nnnnDDDDppppvvvvvvvv")
+INST(arm_STC, "STC", "cccc110pudw0nnnnDDDDppppvvvvvvvv")
+INST(arm_SVC, "SVC", "cccc1111vvvvvvvvvvvvvvvvvvvvvvvv")
--- a/src/dynarmic/src/dynarmic/frontend/A32/decoder/asimd.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/decoder/asimd.h
@ -27,50 +27,12 @@ template<typename Visitor>
 using ASIMDMatcher = Decoder::Matcher<Visitor, u32>;

 template<typename V>
-std::vector<ASIMDMatcher<V>> GetASIMDDecodeTable() noexcept {
-    std::vector<std::pair<const char*, ASIMDMatcher<V>>> table = {
-#define INST(fn, name, bitstring) { name, DYNARMIC_DECODER_GET_MATCHER(ASIMDMatcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)) },
+static std::optional<std::reference_wrapper<const ASIMDMatcher<V>>> DecodeASIMD(u32 instruction) noexcept {
+    alignas(64) static const auto table = std::array{
+#define INST(fn, name, bitstring) DYNARMIC_DECODER_GET_MATCHER(ASIMDMatcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)),
 #include "./asimd.inc"
 #undef INST
    };
-    // Exceptions to the rule of thumb.
-    const std::set<std::string> comes_first{
-        "VBIC, VMOV, VMVN, VORR (immediate)",
-        "VEXT",
-        "VTBL",
-        "VTBX",
-        "VDUP (scalar)",
-    };
-    const std::set<std::string> comes_last{
-        "VMLA (scalar)",
-        "VMLAL (scalar)",
-        "VQDMLAL/VQDMLSL (scalar)",
-        "VMUL (scalar)",
-        "VMULL (scalar)",
-        "VQDMULL (scalar)",
-        "VQDMULH (scalar)",
-        "VQRDMULH (scalar)",
-    };
-    const auto sort_begin = std::stable_partition(table.begin(), table.end(), [&](const auto& e) {
-        return comes_first.count(e.first) > 0;
-    });
-    const auto sort_end = std::stable_partition(table.begin(), table.end(), [&](const auto& e) {
-        return comes_last.count(e.first) == 0;
-    });
-    // If a matcher has more bits in its mask it is more specific, so it should come first.
-    std::stable_sort(sort_begin, sort_end, [](const auto& a, const auto& b) {
-        return mcl::bit::count_ones(a.second.GetMask()) > mcl::bit::count_ones(b.second.GetMask());
-    });
-    std::vector<ASIMDMatcher<V>> final_table;
-    std::transform(table.cbegin(), table.cend(), std::back_inserter(final_table), [](auto const& e) {
-        return e.second;
-    });
-    return final_table;
-}
-
-template<typename V>
-std::optional<std::reference_wrapper<const ASIMDMatcher<V>>> DecodeASIMD(u32 instruction) noexcept {
-    alignas(64) static const auto table = GetASIMDDecodeTable<V>();
    auto iter = std::find_if(table.begin(), table.end(), [instruction](const auto& matcher) {
        return matcher.Matches(instruction);
    });
@ -78,7 +40,7 @@ std::optional<std::reference_wrapper<const ASIMDMatcher<V>>> DecodeASIMD(u32 ins
 }

 template<typename V>
-std::optional<std::string_view> GetNameASIMD(u32 inst) noexcept {
+static std::optional<std::string_view> GetNameASIMD(u32 inst) noexcept {
    std::vector<std::pair<std::string_view, ASIMDMatcher<V>>> list = {
 #define INST(fn, name, bitstring) { name, DYNARMIC_DECODER_GET_MATCHER(ASIMDMatcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)) },
 #include "./asimd.inc"
--- a/src/dynarmic/src/dynarmic/frontend/A32/decoder/asimd.inc
+++ b/src/dynarmic/src/dynarmic/frontend/A32/decoder/asimd.inc
@ -1,172 +1,151 @@
-// Three registers of the same length
-INST(asimd_VHADD,           "VHADD",                    "1111001U0Dzznnnndddd0000NQM0mmmm") // ASIMD
-INST(asimd_VQADD,           "VQADD",                    "1111001U0Dzznnnndddd0000NQM1mmmm") // ASIMD
-INST(asimd_VRHADD,          "VRHADD",                   "1111001U0Dzznnnndddd0001NQM0mmmm") // ASIMD
-INST(asimd_VAND_reg,        "VAND (register)",          "111100100D00nnnndddd0001NQM1mmmm") // ASIMD
-INST(asimd_VBIC_reg,        "VBIC (register)",          "111100100D01nnnndddd0001NQM1mmmm") // ASIMD
-INST(asimd_VORR_reg,        "VORR (register)",          "111100100D10nnnndddd0001NQM1mmmm") // ASIMD
-INST(asimd_VORN_reg,        "VORN (register)",          "111100100D11nnnndddd0001NQM1mmmm") // ASIMD
-INST(asimd_VEOR_reg,        "VEOR (register)",          "111100110D00nnnndddd0001NQM1mmmm") // ASIMD
-INST(asimd_VBSL,            "VBSL",                     "111100110D01nnnndddd0001NQM1mmmm") // ASIMD
-INST(asimd_VBIT,            "VBIT",                     "111100110D10nnnndddd0001NQM1mmmm") // ASIMD
-INST(asimd_VBIF,            "VBIF",                     "111100110D11nnnndddd0001NQM1mmmm") // ASIMD
-INST(asimd_VHSUB,           "VHSUB",                    "1111001U0Dzznnnndddd0010NQM0mmmm") // ASIMD
-INST(asimd_VQSUB,           "VQSUB",                    "1111001U0Dzznnnndddd0010NQM1mmmm") // ASIMD
-INST(asimd_VCGT_reg,        "VCGT (register)",          "1111001U0Dzznnnndddd0011NQM0mmmm") // ASIMD
-INST(asimd_VCGE_reg,        "VCGE (register)",          "1111001U0Dzznnnndddd0011NQM1mmmm") // ASIMD
-INST(asimd_VSHL_reg,        "VSHL (register)",          "1111001U0Dzznnnndddd0100NQM0mmmm") // ASIMD
-INST(asimd_VQSHL_reg,       "VQSHL (register)",         "1111001U0Dzznnnndddd0100NQM1mmmm") // ASIMD
-INST(asimd_VRSHL,           "VRSHL",                    "1111001U0Dzznnnndddd0101NQM0mmmm") // ASIMD
-//INST(asimd_VQRSHL,          "VQRSHL",                   "1111001U0-CC--------0101---1----") // ASIMD
-INST(asimd_VMAX,            "VMAX/VMIN (integer)",      "1111001U0Dzznnnnmmmm0110NQMommmm") // ASIMD
-INST(asimd_VABD,            "VABD",                     "1111001U0Dzznnnndddd0111NQM0mmmm") // ASIMD
-INST(asimd_VABA,            "VABA",                     "1111001U0Dzznnnndddd0111NQM1mmmm") // ASIMD
-INST(asimd_VADD_int,        "VADD (integer)",           "111100100Dzznnnndddd1000NQM0mmmm") // ASIMD
-INST(asimd_VSUB_int,        "VSUB (integer)",           "111100110Dzznnnndddd1000NQM0mmmm") // ASIMD
-INST(asimd_VTST,            "VTST",                     "111100100Dzznnnndddd1000NQM1mmmm") // ASIMD
-INST(asimd_VCEQ_reg,        "VCEG (register)",          "111100110Dzznnnndddd1000NQM1mmmm") // ASIMD
-INST(asimd_VMLA,            "VMLA/VMLS",                "1111001o0Dzznnnndddd1001NQM0mmmm") // ASIMD
-INST(asimd_VMUL,            "VMUL",                     "1111001P0Dzznnnndddd1001NQM1mmmm") // ASIMD
-INST(asimd_VPMAX_int,       "VPMAX/VPMIN (integer)",    "1111001U0Dzznnnndddd1010NQMommmm") // ASIMD
-INST(v8_VMAXNM,             "VMAXNM",                   "111100110D0znnnndddd1111NQM1mmmm") // v8
-INST(v8_VMINNM,             "VMINNM",                   "111100110D1znnnndddd1111NQM1mmmm") // v8
-INST(asimd_VQDMULH,         "VQDMULH",                  "111100100Dzznnnndddd1011NQM0mmmm") // ASIMD
-INST(asimd_VQRDMULH,        "VQRDMULH",                 "111100110Dzznnnndddd1011NQM0mmmm") // ASIMD
-INST(asimd_VPADD,           "VPADD",                    "111100100Dzznnnndddd1011NQM1mmmm") // ASIMD
-INST(asimd_VFMA,            "VFMA",                     "111100100D0znnnndddd1100NQM1mmmm") // ASIMD
-INST(asimd_VFMS,            "VFMS",                     "111100100D1znnnndddd1100NQM1mmmm") // ASIMD
-INST(asimd_VADD_float,      "VADD (floating-point)",    "111100100D0znnnndddd1101NQM0mmmm") // ASIMD
-INST(asimd_VSUB_float,      "VSUB (floating-point)",    "111100100D1znnnndddd1101NQM0mmmm") // ASIMD
-INST(asimd_VPADD_float,     "VPADD (floating-point)",   "111100110D0znnnndddd1101NQM0mmmm") // ASIMD
-INST(asimd_VABD_float,      "VABD (floating-point)",    "111100110D1znnnndddd1101NQM0mmmm") // ASIMD
-INST(asimd_VMLA_float,      "VMLA (floating-point)",    "111100100D0znnnndddd1101NQM1mmmm") // ASIMD
-INST(asimd_VMLS_float,      "VMLS (floating-point)",    "111100100D1znnnndddd1101NQM1mmmm") // ASIMD
-INST(asimd_VMUL_float,      "VMUL (floating-point)",    "111100110D0znnnndddd1101NQM1mmmm") // ASIMD
-INST(asimd_VCEQ_reg_float,  "VCEQ (register)",          "111100100D0znnnndddd1110NQM0mmmm") // ASIMD
-INST(asimd_VCGE_reg_float,  "VCGE (register)",          "111100110D0znnnndddd1110NQM0mmmm") // ASIMD
-INST(asimd_VCGT_reg_float,  "VCGT (register)",          "111100110D1znnnndddd1110NQM0mmmm") // ASIMD
-INST(asimd_VACGE,           "VACGE",                    "111100110Doznnnndddd1110NQM1mmmm") // ASIMD
-INST(asimd_VMAX_float,      "VMAX (floating-point)",    "111100100D0znnnndddd1111NQM0mmmm") // ASIMD
-INST(asimd_VMIN_float,      "VMIN (floating-point)",    "111100100D1znnnndddd1111NQM0mmmm") // ASIMD
-INST(asimd_VPMAX_float,     "VPMAX (floating-point)",   "111100110D0znnnndddd1111NQM0mmmm") // ASIMD
-INST(asimd_VPMIN_float,     "VPMIN (floating-point)",   "111100110D1znnnndddd1111NQM0mmmm") // ASIMD
-INST(asimd_VRECPS,          "VRECPS",                   "111100100D0znnnndddd1111NQM1mmmm") // ASIMD
-INST(asimd_VRSQRTS,         "VRSQRTS",                  "111100100D1znnnndddd1111NQM1mmmm") // ASIMD
-INST(v8_SHA256H,            "SHA256H",                  "111100110D00nnnndddd1100NQM0mmmm") // v8
-INST(v8_SHA256H2,           "SHA256H2",                 "111100110D01nnnndddd1100NQM0mmmm") // v8
-INST(v8_SHA256SU1,          "SHA256SU1",                "111100110D10nnnndddd1100NQM0mmmm") // v8
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+// DO NOT REORDER

-// Three registers of different lengths
-INST(asimd_VADDL,           "VADDL/VADDW",              "1111001U1Dzznnnndddd000oN0M0mmmm") // ASIMD
-INST(asimd_VSUBL,           "VSUBL/VSUBW",              "1111001U1Dzznnnndddd001oN0M0mmmm") // ASIMD
-//INST(asimd_VADDHN,          "VADDHN",                   "111100101-----------0100-0-0----") // ASIMD
-//INST(asimd_VRADDHN,         "VRADDHN",                  "111100111-----------0100-0-0----") // ASIMD
-INST(asimd_VABAL,           "VABAL",                    "1111001U1Dzznnnndddd0101N0M0mmmm") // ASIMD
-//INST(asimd_VSUBHN,          "VSUBHN",                   "111100101-----------0110-0-0----") // ASIMD
-//INST(asimd_VRSUBHN,         "VRSUBHN",                  "111100111-----------0110-0-0----") // ASIMD
-INST(asimd_VABDL,           "VABDL",                    "1111001U1Dzznnnndddd0111N0M0mmmm") // ASIMD
-INST(asimd_VMLAL,           "VMLAL/VMLSL",              "1111001U1Dzznnnndddd10o0N0M0mmmm") // ASIMD
-//INST(asimd_VQDMLAL,         "VQDMLAL",                  "111100101-----------10-1-0-0----") // ASIMD
-INST(asimd_VMULL,           "VMULL",                    "1111001U1Dzznnnndddd11P0N0M0mmmm") // ASIMD
-//INST(asimd_VQDMULL,         "VQDMULL",                  "111100101-----------1101-0-0----") // ASIMD
-
-// Two registers and a scalar
-INST(asimd_VMLA_scalar,     "VMLA (scalar)",            "1111001Q1Dzznnnndddd0o0FN1M0mmmm") // ASIMD
-INST(asimd_VMLAL_scalar,    "VMLAL (scalar)",           "1111001U1dzznnnndddd0o10N1M0mmmm") // ASIMD
-//INST(asimd_VQDMLAL_scalar,  "VQDMLAL/VQDMLSL (scalar)", "111100101-BB--------0x11-1-0----") // ASIMD
-INST(asimd_VMUL_scalar,     "VMUL (scalar)",            "1111001Q1Dzznnnndddd100FN1M0mmmm") // ASIMD
-INST(asimd_VMULL_scalar,    "VMULL (scalar)",           "1111001U1Dzznnnndddd1010N1M0mmmm") // ASIMD
-INST(asimd_VQDMULL_scalar,  "VQDMULL (scalar)",         "111100101Dzznnnndddd1011N1M0mmmm") // ASIMD
-INST(asimd_VQDMULH_scalar,  "VQDMULH (scalar)",         "1111001Q1Dzznnnndddd1100N1M0mmmm") // ASIMD
-INST(asimd_VQRDMULH_scalar, "VQRDMULH (scalar)",        "1111001Q1Dzznnnndddd1101N1M0mmmm") // ASIMD
-
-// Two registers and a shift amount
-INST(asimd_SHR,             "SHR",                      "1111001U1Diiiiiidddd0000LQM1mmmm") // ASIMD
-INST(asimd_SRA,             "SRA",                      "1111001U1Diiiiiidddd0001LQM1mmmm") // ASIMD
-INST(asimd_VRSHR,           "VRSHR",                    "1111001U1Diiiiiidddd0010LQM1mmmm") // ASIMD
-INST(asimd_VRSRA,           "VRSRA",                    "1111001U1Diiiiiidddd0011LQM1mmmm") // ASIMD
-INST(asimd_VSRI,            "VSRI",                     "111100111Diiiiiidddd0100LQM1mmmm") // ASIMD
-INST(asimd_VSHL,            "VSHL",                     "111100101Diiiiiidddd0101LQM1mmmm") // ASIMD
-INST(asimd_VSLI,            "VSLI",                     "111100111Diiiiiidddd0101LQM1mmmm") // ASIMD
-INST(asimd_VQSHL,           "VQSHL" ,                   "1111001U1Diiiiiidddd011oLQM1mmmm") // ASIMD
-INST(asimd_VSHRN,           "VSHRN",                    "111100101Diiiiiidddd100000M1mmmm") // ASIMD
-INST(asimd_VRSHRN,          "VRSHRN",                   "111100101Diiiiiidddd100001M1mmmm") // ASIMD
-INST(asimd_VQSHRUN,         "VQSHRUN",                  "111100111Diiiiiidddd100000M1mmmm") // ASIMD
-INST(asimd_VQRSHRUN,        "VQRSHRUN",                 "111100111Diiiiiidddd100001M1mmmm") // ASIMD
-INST(asimd_VQSHRN,          "VQSHRN",                   "1111001U1Diiiiiidddd100100M1mmmm") // ASIMD
-INST(asimd_VQRSHRN,         "VQRSHRN",                  "1111001U1Diiiiiidddd100101M1mmmm") // ASIMD
-INST(asimd_VSHLL,           "VSHLL",                    "1111001U1Diiiiiidddd101000M1mmmm") // ASIMD
-INST(asimd_VCVT_fixed,      "VCVT (fixed-point)",       "1111001U1Diiiiiidddd111o0QM1mmmm") // ASIMD
-
-// Two registers, miscellaneous
-INST(asimd_VREV,            "VREV{16,32,64}",           "111100111D11zz00dddd000ooQM0mmmm") // ASIMD
-INST(asimd_VPADDL,          "VPADDL",                   "111100111D11zz00dddd0010oQM0mmmm") // ASIMD
-INST(asimd_VCLS,            "VCLS",                     "111100111D11zz00dddd01000QM0mmmm") // ASIMD
-INST(asimd_VCLZ,            "VCLZ",                     "111100111D11zz00dddd01001QM0mmmm") // ASIMD
-INST(asimd_VCNT,            "VCNT",                     "111100111D11zz00dddd01010QM0mmmm") // ASIMD
-INST(asimd_VMVN_reg,        "VMVN_reg",                 "111100111D11zz00dddd01011QM0mmmm") // ASIMD
-INST(asimd_VPADAL,          "VPADAL",                   "111100111D11zz00dddd0110oQM0mmmm") // ASIMD
-INST(asimd_VQABS,           "VQABS",                    "111100111D11zz00dddd01110QM0mmmm") // ASIMD
-INST(asimd_VQNEG,           "VQNEG",                    "111100111D11zz00dddd01111QM0mmmm") // ASIMD
-INST(asimd_VCGT_zero,       "VCGT (zero)",              "111100111D11zz01dddd0F000QM0mmmm") // ASIMD
-INST(asimd_VCGE_zero,       "VCGE (zero)",              "111100111D11zz01dddd0F001QM0mmmm") // ASIMD
-INST(asimd_VCEQ_zero,       "VCEQ (zero)",              "111100111D11zz01dddd0F010QM0mmmm") // ASIMD
-INST(asimd_VCLE_zero,       "VCLE (zero)",              "111100111D11zz01dddd0F011QM0mmmm") // ASIMD
-INST(asimd_VCLT_zero,       "VCLT (zero)",              "111100111D11zz01dddd0F100QM0mmmm") // ASIMD
-INST(arm_UDF,               "UNALLOCATED",              "111100111-11--01----01101--0----") // v8
-INST(asimd_VABS,            "VABS",                     "111100111D11zz01dddd0F110QM0mmmm") // ASIMD
-INST(asimd_VNEG,            "VNEG",                     "111100111D11zz01dddd0F111QM0mmmm") // ASIMD
-INST(asimd_VSWP,            "VSWP",                     "111100111D110010dddd00000QM0mmmm") // ASIMD
-INST(arm_UDF,               "UNALLOCATED",              "111100111-11--10----00000--0----") // ASIMD
-INST(asimd_VTRN,            "VTRN",                     "111100111D11zz10dddd00001QM0mmmm") // ASIMD
-INST(asimd_VUZP,            "VUZP",                     "111100111D11zz10dddd00010QM0mmmm") // ASIMD
-INST(asimd_VZIP,            "VZIP",                     "111100111D11zz10dddd00011QM0mmmm") // ASIMD
-INST(asimd_VMOVN,           "VMOVN",                    "111100111D11zz10dddd001000M0mmmm") // ASIMD
-INST(asimd_VQMOVUN,         "VQMOVUN",                  "111100111D11zz10dddd001001M0mmmm") // ASIMD
-INST(asimd_VQMOVN,          "VQMOVN",                   "111100111D11zz10dddd00101oM0mmmm") // ASIMD
-INST(asimd_VSHLL_max,       "VSHLL_max",                "111100111D11zz10dddd001100M0mmmm") // ASIMD
-INST(v8_VRINTN,             "VRINTN",                   "111100111D11zz10dddd01000QM0mmmm") // v8
-INST(v8_VRINTX,             "VRINTX",                   "111100111D11zz10dddd01001QM0mmmm") // v8
-INST(v8_VRINTA,             "VRINTA",                   "111100111D11zz10dddd01010QM0mmmm") // v8
-INST(v8_VRINTZ,             "VRINTZ",                   "111100111D11zz10dddd01011QM0mmmm") // v8
-INST(v8_VRINTM,             "VRINTM",                   "111100111D11zz10dddd01101QM0mmmm") // v8
-INST(v8_VRINTP,             "VRINTP",                   "111100111D11zz10dddd01111QM0mmmm") // v8
-INST(asimd_VCVT_half,       "VCVT (half-precision)",    "111100111D11zz10dddd011o00M0mmmm") // ASIMD
-INST(arm_UDF,               "UNALLOCATED",              "111100111-11--10----011-01-0----") // ASIMD
-INST(v8_VCVTA,              "VCVTA",                    "111100111D11zz11dddd0000oQM0mmmm") // v8
-INST(v8_VCVTN,              "VCVTN",                    "111100111D11zz11dddd0001oQM0mmmm") // v8
-INST(v8_VCVTP,              "VCVTP",                    "111100111D11zz11dddd0010oQM0mmmm") // v8
-INST(v8_VCVTM,              "VCVTM",                    "111100111D11zz11dddd0011oQM0mmmm") // v8
-INST(asimd_VRECPE,          "VRECPE",                   "111100111D11zz11dddd010F0QM0mmmm") // ASIMD
-INST(asimd_VRSQRTE,         "VRSQRTE",                  "111100111D11zz11dddd010F1QM0mmmm") // ASIMD
-INST(asimd_VCVT_integer,    "VCVT (integer)",           "111100111D11zz11dddd011oUQM0mmmm") // ASIMD
-
-// Two registers, cryptography
-INST(v8_AESE,               "AESE",                     "111100111D11zz00dddd001100M0mmmm") // v8
-INST(v8_AESD,               "AESD",                     "111100111D11zz00dddd001101M0mmmm") // v8
-INST(v8_AESMC,              "AESMC",                    "111100111D11zz00dddd001110M0mmmm") // v8
-INST(v8_AESIMC,             "AESIMC",                   "111100111D11zz00dddd001111M0mmmm") // v8
-INST(arm_UDF,               "UNALLOCATED",              "111100111-11--01----001010-0----") // v8
-INST(arm_UDF,               "UNALLOCATED (SHA1H)",      "111100111-11--01----001011-0----") // v8
-INST(arm_UDF,               "UNALLOCATED (SHA1SU1)",    "111100111-11--10----001110-0----") // v8
-INST(v8_SHA256SU0,          "SHA256SU0",                "111100111D11zz10dddd001111M0mmmm") // v8
-
-// One register and modified immediate
-INST(asimd_VMOV_imm,        "VBIC, VMOV, VMVN, VORR (immediate)",  "1111001a1D000bcdVVVVmmmm0Qo1efgh") // ASIMD
-
-// Miscellaneous
-INST(asimd_VEXT,            "VEXT",                     "111100101D11nnnnddddiiiiNQM0mmmm") // ASIMD
-INST(asimd_VTBL,            "VTBL",                     "111100111D11nnnndddd10zzN0M0mmmm") // ASIMD
-INST(asimd_VTBX,            "VTBX",                     "111100111D11nnnndddd10zzN1M0mmmm") // ASIMD
-INST(asimd_VDUP_scalar,     "VDUP (scalar)",            "111100111D11iiiidddd11000QM0mmmm") // ASIMD
-INST(arm_UDF,               "UNALLOCATED",              "111100111-11--------11-----0----") // ASIMD
-
-// Advanced SIMD load/store structures
-INST(v8_VST_multiple,       "VST{1-4} (multiple)",      "111101000D00nnnnddddxxxxzzaammmm") // v8
-INST(v8_VLD_multiple,       "VLD{1-4} (multiple)",      "111101000D10nnnnddddxxxxzzaammmm") // v8
-INST(arm_UDF,               "UNALLOCATED",              "111101000--0--------1011--------") // v8
-INST(arm_UDF,               "UNALLOCATED",              "111101000--0--------11----------") // v8
-INST(arm_UDF,               "UNALLOCATED",              "111101001-00--------11----------") // v8
-INST(v8_VLD_all_lanes,      "VLD{1-4} (all lanes)",     "111101001D10nnnndddd11nnzzTammmm") // v8
-INST(v8_VST_single,         "VST{1-4} (single)",        "111101001D00nnnnddddzzNNaaaammmm") // v8
-INST(v8_VLD_single,         "VLD{1-4} (single)",        "111101001D10nnnnddddzzNNaaaammmm") // v8
+INST(asimd_VMOV_imm, "VBIC, VMOV, VMVN, VORR (immediate)", "1111001a1D000bcdVVVVmmmm0Qo1efgh")
+INST(asimd_VEXT, "VEXT", "111100101D11nnnnddddiiiiNQM0mmmm")
+INST(asimd_VTBL, "VTBL", "111100111D11nnnndddd10zzN0M0mmmm")
+INST(asimd_VTBX, "VTBX", "111100111D11nnnndddd10zzN1M0mmmm")
+INST(asimd_VDUP_scalar, "VDUP (scalar)", "111100111D11iiiidddd11000QM0mmmm")
+INST(asimd_VSWP, "VSWP", "111100111D110010dddd00000QM0mmmm")
+INST(asimd_VMOVN, "VMOVN", "111100111D11zz10dddd001000M0mmmm")
+INST(asimd_VQMOVUN, "VQMOVUN", "111100111D11zz10dddd001001M0mmmm")
+INST(asimd_VSHLL_max, "VSHLL_max", "111100111D11zz10dddd001100M0mmmm")
+INST(v8_AESE, "AESE", "111100111D11zz00dddd001100M0mmmm")
+INST(v8_AESD, "AESD", "111100111D11zz00dddd001101M0mmmm")
+INST(v8_AESMC, "AESMC", "111100111D11zz00dddd001110M0mmmm")
+INST(v8_AESIMC, "AESIMC", "111100111D11zz00dddd001111M0mmmm")
+INST(arm_UDF, "UNALLOCATED", "111100111-11--01----001010-0----")
+INST(arm_UDF, "UNALLOCATED (SHA1H)", "111100111-11--01----001011-0----")
+INST(arm_UDF, "UNALLOCATED (SHA1SU1)", "111100111-11--10----001110-0----")
+INST(v8_SHA256SU0, "SHA256SU0", "111100111D11zz10dddd001111M0mmmm")
+INST(asimd_VCLS, "VCLS", "111100111D11zz00dddd01000QM0mmmm")
+INST(asimd_VCLZ, "VCLZ", "111100111D11zz00dddd01001QM0mmmm")
+INST(asimd_VCNT, "VCNT", "111100111D11zz00dddd01010QM0mmmm")
+INST(asimd_VMVN_reg, "VMVN_reg", "111100111D11zz00dddd01011QM0mmmm")
+INST(asimd_VQABS, "VQABS", "111100111D11zz00dddd01110QM0mmmm")
+INST(asimd_VQNEG, "VQNEG", "111100111D11zz00dddd01111QM0mmmm")
+INST(arm_UDF, "UNALLOCATED", "111100111-11--01----01101--0----")
+INST(arm_UDF, "UNALLOCATED", "111100111-11--10----00000--0----")
+INST(asimd_VTRN, "VTRN", "111100111D11zz10dddd00001QM0mmmm")
+INST(asimd_VUZP, "VUZP", "111100111D11zz10dddd00010QM0mmmm")
+INST(asimd_VZIP, "VZIP", "111100111D11zz10dddd00011QM0mmmm")
+INST(asimd_VQMOVN, "VQMOVN", "111100111D11zz10dddd00101oM0mmmm")
+INST(v8_VRINTN, "VRINTN", "111100111D11zz10dddd01000QM0mmmm")
+INST(v8_VRINTX, "VRINTX", "111100111D11zz10dddd01001QM0mmmm")
+INST(v8_VRINTA, "VRINTA", "111100111D11zz10dddd01010QM0mmmm")
+INST(v8_VRINTZ, "VRINTZ", "111100111D11zz10dddd01011QM0mmmm")
+INST(v8_VRINTM, "VRINTM", "111100111D11zz10dddd01101QM0mmmm")
+INST(v8_VRINTP, "VRINTP", "111100111D11zz10dddd01111QM0mmmm")
+INST(asimd_VCVT_half, "VCVT (half-precision)", "111100111D11zz10dddd011o00M0mmmm")
+INST(arm_UDF, "UNALLOCATED", "111100111-11--10----011-01-0----")
+INST(asimd_VPADDL, "VPADDL", "111100111D11zz00dddd0010oQM0mmmm")
+INST(asimd_VPADAL, "VPADAL", "111100111D11zz00dddd0110oQM0mmmm")
+INST(asimd_VCGT_zero, "VCGT (zero)", "111100111D11zz01dddd0F000QM0mmmm")
+INST(asimd_VCGE_zero, "VCGE (zero)", "111100111D11zz01dddd0F001QM0mmmm")
+INST(asimd_VCEQ_zero, "VCEQ (zero)", "111100111D11zz01dddd0F010QM0mmmm")
+INST(asimd_VCLE_zero, "VCLE (zero)", "111100111D11zz01dddd0F011QM0mmmm")
+INST(asimd_VCLT_zero, "VCLT (zero)", "111100111D11zz01dddd0F100QM0mmmm")
+INST(asimd_VABS, "VABS", "111100111D11zz01dddd0F110QM0mmmm")
+INST(asimd_VNEG, "VNEG", "111100111D11zz01dddd0F111QM0mmmm")
+INST(v8_VCVTA, "VCVTA", "111100111D11zz11dddd0000oQM0mmmm")
+INST(v8_VCVTN, "VCVTN", "111100111D11zz11dddd0001oQM0mmmm")
+INST(v8_VCVTP, "VCVTP", "111100111D11zz11dddd0010oQM0mmmm")
+INST(v8_VCVTM, "VCVTM", "111100111D11zz11dddd0011oQM0mmmm")
+INST(asimd_VRECPE, "VRECPE", "111100111D11zz11dddd010F0QM0mmmm")
+INST(asimd_VRSQRTE, "VRSQRTE", "111100111D11zz11dddd010F1QM0mmmm")
+INST(asimd_VREV, "VREV{16,32,64}", "111100111D11zz00dddd000ooQM0mmmm")
+INST(asimd_VCVT_integer, "VCVT (integer)", "111100111D11zz11dddd011oUQM0mmmm")
+INST(asimd_VAND_reg, "VAND (register)", "111100100D00nnnndddd0001NQM1mmmm")
+INST(asimd_VBIC_reg, "VBIC (register)", "111100100D01nnnndddd0001NQM1mmmm")
+INST(asimd_VORR_reg, "VORR (register)", "111100100D10nnnndddd0001NQM1mmmm")
+INST(asimd_VORN_reg, "VORN (register)", "111100100D11nnnndddd0001NQM1mmmm")
+INST(asimd_VEOR_reg, "VEOR (register)", "111100110D00nnnndddd0001NQM1mmmm")
+INST(asimd_VBSL, "VBSL", "111100110D01nnnndddd0001NQM1mmmm")
+INST(asimd_VBIT, "VBIT", "111100110D10nnnndddd0001NQM1mmmm")
+INST(asimd_VBIF, "VBIF", "111100110D11nnnndddd0001NQM1mmmm")
+INST(v8_SHA256H, "SHA256H", "111100110D00nnnndddd1100NQM0mmmm")
+INST(v8_SHA256H2, "SHA256H2", "111100110D01nnnndddd1100NQM0mmmm")
+INST(v8_SHA256SU1, "SHA256SU1", "111100110D10nnnndddd1100NQM0mmmm")
+INST(asimd_VSHRN, "VSHRN", "111100101Diiiiiidddd100000M1mmmm")
+INST(asimd_VRSHRN, "VRSHRN", "111100101Diiiiiidddd100001M1mmmm")
+INST(asimd_VQSHRUN, "VQSHRUN", "111100111Diiiiiidddd100000M1mmmm")
+INST(asimd_VQRSHRUN, "VQRSHRUN", "111100111Diiiiiidddd100001M1mmmm")
+INST(v8_VMAXNM, "VMAXNM", "111100110D0znnnndddd1111NQM1mmmm")
+INST(v8_VMINNM, "VMINNM", "111100110D1znnnndddd1111NQM1mmmm")
+INST(asimd_VFMA, "VFMA", "111100100D0znnnndddd1100NQM1mmmm")
+INST(asimd_VFMS, "VFMS", "111100100D1znnnndddd1100NQM1mmmm")
+INST(asimd_VADD_float, "VADD (floating-point)", "111100100D0znnnndddd1101NQM0mmmm")
+INST(asimd_VSUB_float, "VSUB (floating-point)", "111100100D1znnnndddd1101NQM0mmmm")
+INST(asimd_VPADD_float, "VPADD (floating-point)", "111100110D0znnnndddd1101NQM0mmmm")
+INST(asimd_VABD_float, "VABD (floating-point)", "111100110D1znnnndddd1101NQM0mmmm")
+INST(asimd_VMLA_float, "VMLA (floating-point)", "111100100D0znnnndddd1101NQM1mmmm")
+INST(asimd_VMLS_float, "VMLS (floating-point)", "111100100D1znnnndddd1101NQM1mmmm")
+INST(asimd_VMUL_float, "VMUL (floating-point)", "111100110D0znnnndddd1101NQM1mmmm")
+INST(asimd_VCEQ_reg_float, "VCEQ (register)", "111100100D0znnnndddd1110NQM0mmmm")
+INST(asimd_VCGE_reg_float, "VCGE (register)", "111100110D0znnnndddd1110NQM0mmmm")
+INST(asimd_VCGT_reg_float, "VCGT (register)", "111100110D1znnnndddd1110NQM0mmmm")
+INST(asimd_VMAX_float, "VMAX (floating-point)", "111100100D0znnnndddd1111NQM0mmmm")
+INST(asimd_VMIN_float, "VMIN (floating-point)", "111100100D1znnnndddd1111NQM0mmmm")
+INST(asimd_VPMAX_float, "VPMAX (floating-point)", "111100110D0znnnndddd1111NQM0mmmm")
+INST(asimd_VPMIN_float, "VPMIN (floating-point)", "111100110D1znnnndddd1111NQM0mmmm")
+INST(asimd_VRECPS, "VRECPS", "111100100D0znnnndddd1111NQM1mmmm")
+INST(asimd_VRSQRTS, "VRSQRTS", "111100100D1znnnndddd1111NQM1mmmm")
+INST(asimd_VQSHRN, "VQSHRN", "1111001U1Diiiiiidddd100100M1mmmm")
+INST(asimd_VQRSHRN, "VQRSHRN", "1111001U1Diiiiiidddd100101M1mmmm")
+INST(asimd_VSHLL, "VSHLL", "1111001U1Diiiiiidddd101000M1mmmm")
+INST(asimd_VADD_int, "VADD (integer)", "111100100Dzznnnndddd1000NQM0mmmm")
+INST(asimd_VSUB_int, "VSUB (integer)", "111100110Dzznnnndddd1000NQM0mmmm")
+INST(asimd_VTST, "VTST", "111100100Dzznnnndddd1000NQM1mmmm")
+INST(asimd_VCEQ_reg, "VCEG (register)", "111100110Dzznnnndddd1000NQM1mmmm")
+INST(asimd_VQDMULH, "VQDMULH", "111100100Dzznnnndddd1011NQM0mmmm")
+INST(asimd_VQRDMULH, "VQRDMULH", "111100110Dzznnnndddd1011NQM0mmmm")
+INST(asimd_VPADD, "VPADD", "111100100Dzznnnndddd1011NQM1mmmm")
+INST(asimd_VACGE, "VACGE", "111100110Doznnnndddd1110NQM1mmmm")
+INST(asimd_VABAL, "VABAL", "1111001U1Dzznnnndddd0101N0M0mmmm")
+INST(asimd_VABDL, "VABDL", "1111001U1Dzznnnndddd0111N0M0mmmm")
+INST(asimd_VSRI, "VSRI", "111100111Diiiiiidddd0100LQM1mmmm")
+INST(asimd_VSHL, "VSHL", "111100101Diiiiiidddd0101LQM1mmmm")
+INST(asimd_VSLI, "VSLI", "111100111Diiiiiidddd0101LQM1mmmm")
+INST(arm_UDF, "UNALLOCATED", "111100111-11--------11-----0----")
+INST(arm_UDF, "UNALLOCATED", "111101000--0--------1011--------")
+INST(asimd_VHADD, "VHADD", "1111001U0Dzznnnndddd0000NQM0mmmm")
+INST(asimd_VQADD, "VQADD", "1111001U0Dzznnnndddd0000NQM1mmmm")
+INST(asimd_VRHADD, "VRHADD", "1111001U0Dzznnnndddd0001NQM0mmmm")
+INST(asimd_VHSUB, "VHSUB", "1111001U0Dzznnnndddd0010NQM0mmmm")
+INST(asimd_VQSUB, "VQSUB", "1111001U0Dzznnnndddd0010NQM1mmmm")
+INST(asimd_VCGT_reg, "VCGT (register)", "1111001U0Dzznnnndddd0011NQM0mmmm")
+INST(asimd_VCGE_reg, "VCGE (register)", "1111001U0Dzznnnndddd0011NQM1mmmm")
+INST(asimd_VSHL_reg, "VSHL (register)", "1111001U0Dzznnnndddd0100NQM0mmmm")
+INST(asimd_VQSHL_reg, "VQSHL (register)", "1111001U0Dzznnnndddd0100NQM1mmmm")
+INST(asimd_VRSHL, "VRSHL", "1111001U0Dzznnnndddd0101NQM0mmmm")
+INST(asimd_VABD, "VABD", "1111001U0Dzznnnndddd0111NQM0mmmm")
+INST(asimd_VABA, "VABA", "1111001U0Dzznnnndddd0111NQM1mmmm")
+INST(asimd_VMLA, "VMLA/VMLS", "1111001o0Dzznnnndddd1001NQM0mmmm")
+INST(asimd_VMUL, "VMUL", "1111001P0Dzznnnndddd1001NQM1mmmm")
+INST(asimd_VADDL, "VADDL/VADDW", "1111001U1Dzznnnndddd000oN0M0mmmm")
+INST(asimd_VSUBL, "VSUBL/VSUBW", "1111001U1Dzznnnndddd001oN0M0mmmm")
+INST(asimd_VMLAL, "VMLAL/VMLSL", "1111001U1Dzznnnndddd10o0N0M0mmmm")
+INST(asimd_VMULL, "VMULL", "1111001U1Dzznnnndddd11P0N0M0mmmm")
+INST(asimd_SHR, "SHR", "1111001U1Diiiiiidddd0000LQM1mmmm")
+INST(asimd_SRA, "SRA", "1111001U1Diiiiiidddd0001LQM1mmmm")
+INST(asimd_VRSHR, "VRSHR", "1111001U1Diiiiiidddd0010LQM1mmmm")
+INST(asimd_VRSRA, "VRSRA", "1111001U1Diiiiiidddd0011LQM1mmmm")
+INST(asimd_VCVT_fixed, "VCVT (fixed-point)", "1111001U1Diiiiiidddd111o0QM1mmmm")
+INST(arm_UDF, "UNALLOCATED", "111101001-00--------11----------")
+INST(v8_VLD_all_lanes, "VLD{1-4} (all lanes)", "111101001D10nnnndddd11nnzzTammmm")
+INST(asimd_VMAX, "VMAX/VMIN (integer)", "1111001U0Dzznnnnmmmm0110NQMommmm")
+INST(asimd_VPMAX_int, "VPMAX/VPMIN (integer)", "1111001U0Dzznnnndddd1010NQMommmm")
+INST(asimd_VQSHL, "VQSHL", "1111001U1Diiiiiidddd011oLQM1mmmm")
+INST(arm_UDF, "UNALLOCATED", "111101000--0--------11----------")
+INST(v8_VST_multiple, "VST{1-4} (multiple)", "111101000D00nnnnddddxxxxzzaammmm")
+INST(v8_VLD_multiple, "VLD{1-4} (multiple)", "111101000D10nnnnddddxxxxzzaammmm")
+INST(v8_VST_single, "VST{1-4} (single)", "111101001D00nnnnddddzzNNaaaammmm")
+INST(v8_VLD_single, "VLD{1-4} (single)", "111101001D10nnnnddddzzNNaaaammmm")
+INST(asimd_VMLA_scalar, "VMLA (scalar)", "1111001Q1Dzznnnndddd0o0FN1M0mmmm")
+INST(asimd_VMLAL_scalar, "VMLAL (scalar)", "1111001U1dzznnnndddd0o10N1M0mmmm")
+INST(asimd_VMUL_scalar, "VMUL (scalar)", "1111001Q1Dzznnnndddd100FN1M0mmmm")
+INST(asimd_VMULL_scalar, "VMULL (scalar)", "1111001U1Dzznnnndddd1010N1M0mmmm")
+INST(asimd_VQDMULL_scalar, "VQDMULL (scalar)", "111100101Dzznnnndddd1011N1M0mmmm")
+INST(asimd_VQDMULH_scalar, "VQDMULH (scalar)", "1111001Q1Dzznnnndddd1100N1M0mmmm")
+INST(asimd_VQRDMULH_scalar, "VQRDMULH (scalar)", "1111001Q1Dzznnnndddd1101N1M0mmmm")
--- a/src/dynarmic/src/dynarmic/frontend/A32/decoder/thumb16.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/decoder/thumb16.h
@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later

 /* This file is part of the dynarmic project.
@ -24,8 +24,8 @@ template<typename Visitor>
 using Thumb16Matcher = Decoder::Matcher<Visitor, u16>;

 template<typename V>
-std::optional<std::reference_wrapper<const Thumb16Matcher<V>>> DecodeThumb16(u16 instruction) {
-    alignas(64) static const std::vector<Thumb16Matcher<V>> table = {
+static std::optional<std::reference_wrapper<const Thumb16Matcher<V>>> DecodeThumb16(u16 instruction) {
+    alignas(64) static const auto table = std::array{
 #define INST(fn, name, bitstring) DYNARMIC_DECODER_GET_MATCHER(Thumb16Matcher, fn, name, Decoder::detail::StringToArray<16>(bitstring)),
 #include "./thumb16.inc"
 #undef INST
@ -37,7 +37,7 @@ std::optional<std::reference_wrapper<const Thumb16Matcher<V>>> DecodeThumb16(u16
 }

 template<typename V>
-std::optional<std::string_view> GetNameThumb16(u32 inst) noexcept {
+static std::optional<std::string_view> GetNameThumb16(u32 inst) noexcept {
    std::vector<std::pair<std::string_view, Thumb16Matcher<V>>> list = {
 #define INST(fn, name, bitstring) { name, DYNARMIC_DECODER_GET_MATCHER(Thumb16Matcher, fn, name, Decoder::detail::StringToArray<16>(bitstring)) },
 #include "./thumb16.inc"
--- a/src/dynarmic/src/dynarmic/frontend/A32/decoder/thumb32.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/decoder/thumb32.h
@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later

 /* This file is part of the dynarmic project.
@ -23,8 +23,8 @@ template<typename Visitor>
 using Thumb32Matcher = Decoder::Matcher<Visitor, u32>;

 template<typename V>
-std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32 instruction) {
-    alignas(64) static const std::vector<Thumb32Matcher<V>> table = {
+static std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32 instruction) {
+    alignas(64) static const auto table = std::array{
 #define INST(fn, name, bitstring) DYNARMIC_DECODER_GET_MATCHER(Thumb32Matcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)),
 #include "./thumb32.inc"
 #undef INST
@ -36,7 +36,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
 }

 template<typename V>
-std::optional<std::string_view> GetNameThumb32(u32 inst) noexcept {
+static std::optional<std::string_view> GetNameThumb32(u32 inst) noexcept {
    std::vector<std::pair<std::string_view, Thumb32Matcher<V>>> list = {
 #define INST(fn, name, bitstring) { name, DYNARMIC_DECODER_GET_MATCHER(Thumb32Matcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)) },
 #include "./thumb32.inc"
--- a/src/dynarmic/src/dynarmic/frontend/A32/decoder/vfp.h
+++ b/src/dynarmic/src/dynarmic/frontend/A32/decoder/vfp.h
@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later

 /* This file is part of the dynarmic project.
@ -24,7 +24,7 @@ template<typename Visitor>
 using VFPMatcher = Decoder::Matcher<Visitor, u32>;

 template<typename V>
-std::optional<std::reference_wrapper<const VFPMatcher<V>>> DecodeVFP(u32 instruction) {
+static std::optional<std::reference_wrapper<const VFPMatcher<V>>> DecodeVFP(u32 instruction) {
    using Table = std::vector<VFPMatcher<V>>;
    alignas(64) static const struct Tables {
        Table unconditional;
@ -52,7 +52,7 @@ std::optional<std::reference_wrapper<const VFPMatcher<V>>> DecodeVFP(u32 instruc
 }

 template<typename V>
-std::optional<std::string_view> GetNameVFP(u32 inst) noexcept {
+static std::optional<std::string_view> GetNameVFP(u32 inst) noexcept {
    std::vector<std::pair<std::string_view, VFPMatcher<V>>> list = {
 #define INST(fn, name, bitstring) { name, DYNARMIC_DECODER_GET_MATCHER(VFPMatcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)) },
 #include "./vfp.inc"
--- a/src/dynarmic/src/dynarmic/frontend/A64/decoder/a64.h
+++ b/src/dynarmic/src/dynarmic/frontend/A64/decoder/a64.h
@ -36,33 +36,19 @@ inline size_t ToFastLookupIndex(u32 instruction) {
 }  // namespace detail

 template<typename V>
-constexpr DecodeTable<V> GetDecodeTable() {
-    std::vector<std::pair<const char*, Matcher<V>>> list = {
-#define INST(fn, name, bitstring) { name, DYNARMIC_DECODER_GET_MATCHER(Matcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)) },
-#include "./a64.inc"
-#undef INST
-    };
-    // If a matcher has more bits in its mask it is more specific, so it should come first.
-    std::stable_sort(list.begin(), list.end(), [](const auto& a, const auto& b) {
-        // If a matcher has more bits in its mask it is more specific, so it should come first.
-        return mcl::bit::count_ones(a.second.GetMask()) > mcl::bit::count_ones(b.second.GetMask());
-    });
-    // Exceptions to the above rule of thumb.
-    std::stable_partition(list.begin(), list.end(), [&](const auto& e) {
-        return std::set<std::string>{
-            "MOVI, MVNI, ORR, BIC (vector, immediate)",
-            "FMOV (vector, immediate)",
-            "Unallocated SIMD modified immediate",
-        }.count(e.first) > 0;
-    });
+inline DecodeTable<V> GetDecodeTable() {
    DecodeTable<V> table{};
    for (size_t i = 0; i < table.size(); ++i) {
-        for (auto const& e : list) {
-            const auto expect = detail::ToFastLookupIndex(e.second.GetExpected());
-            const auto mask = detail::ToFastLookupIndex(e.second.GetMask());
-            if ((i & mask) == expect) {
-                table[i].push_back(e.second);
-            }
+        // PLEASE HEAP ELLIDE
+        for (auto const& e : std::vector<Matcher<V>>{
+#define INST(fn, name, bitstring) DYNARMIC_DECODER_GET_MATCHER(Matcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)),
+#include "./a64.inc"
+#undef INST
+        }) {
+            const auto expect = detail::ToFastLookupIndex(e.GetExpected());
+            const auto mask = detail::ToFastLookupIndex(e.GetMask());
+            if ((i & mask) == expect)
+                table[i].push_back(e);
        }
    }
    return table;
@ -70,7 +56,7 @@ constexpr DecodeTable<V> GetDecodeTable() {

 /// In practice it must always suceed, otherwise something else unrelated would have gone awry
 template<typename V>
-std::optional<std::reference_wrapper<const Matcher<V>>> Decode(u32 instruction) {
+inline std::optional<std::reference_wrapper<const Matcher<V>>> Decode(u32 instruction) {
    alignas(64) static const auto table = GetDecodeTable<V>();
    const auto& subtable = table[detail::ToFastLookupIndex(instruction)];
    auto iter = std::find_if(subtable.begin(), subtable.end(), [instruction](const auto& matcher) {
@ -82,7 +68,7 @@ std::optional<std::reference_wrapper<const Matcher<V>>> Decode(u32 instruction)
 }

 template<typename V>
-std::optional<std::string_view> GetName(u32 inst) noexcept {
+inline std::optional<std::string_view> GetName(u32 inst) noexcept {
    std::vector<std::pair<std::string_view, Matcher<V>>> list = {
 #define INST(fn, name, bitstring) { name, DYNARMIC_DECODER_GET_MATCHER(Matcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)) },
 #include "./a64.inc"
--- a/src/dynarmic/src/dynarmic/frontend/A64/decoder/a64.inc
+++ b/src/dynarmic/src/dynarmic/frontend/A64/decoder/a64.inc
--- a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp
@ -285,8 +285,13 @@ Id IsScaled(EmitContext& ctx, const IR::Value& index, Id member_index, u32 base_
        if (base_index != 0) {
            index_value = ctx.OpIAdd(ctx.U32[1], index_value, ctx.Const(base_index));
        }
+        const Id word_index{ctx.OpShiftRightLogical(ctx.U32[1], index_value, ctx.Const(5u))};
        const Id bit_index{ctx.OpBitwiseAnd(ctx.U32[1], index_value, ctx.Const(31u))};
-        bit = ctx.OpBitFieldUExtract(ctx.U32[1], index_value, bit_index, ctx.Const(1u));
+        const Id pointer{ctx.OpAccessChain(push_constant_u32, ctx.rescaling_push_constants,
+                                           member_index, word_index)};
+        const Id word{ctx.OpLoad(ctx.U32[1], pointer)};
+        const Id bit_index_mask{ctx.OpShiftLeftLogical(ctx.U32[1], ctx.Const(1u), bit_index)};
+        bit = ctx.OpBitwiseAnd(ctx.U32[1], word, bit_index_mask);
    }
    return ctx.OpINotEqual(ctx.U1, bit, ctx.u32_zero_value);
 }
--- a/src/video_core/host_shaders/CMakeLists.txt
+++ b/src/video_core/host_shaders/CMakeLists.txt
@ -118,8 +118,6 @@ if (NOT GLSLANG_ERROR STREQUAL "")
    set(QUIET_FLAG "")
 endif()

-# Shader files must depend on their directory otherwise *BSD make will spontaneously combust
-file(MAKE_DIRECTORY "${SHADER_DIR}")
 foreach(SOURCE_FILE IN ITEMS ${SHADER_FILES})
    get_filename_component(FILENAME ${SOURCE_FILE} NAME)
    string(REPLACE "." "_" SHADER_NAME ${FILENAME})
@ -135,7 +133,6 @@ foreach(SOURCE_FILE IN ITEMS ${SHADER_FILES})
                ${SOURCE_FILE}
            DEPENDS
                ${INPUT_FILE}
-                ${SHADER_DIR}
                # HEADER_GENERATOR should be included here but msbuild seems to assume it's always modified
        )
        set(SHADER_HEADERS ${SHADER_HEADERS} ${SOURCE_HEADER_FILE})
@ -151,8 +148,6 @@ foreach(SOURCE_FILE IN ITEMS ${SHADER_FILES})
                ${GLSLANGVALIDATOR} -V ${QUIET_FLAG} -I"${FIDELITYFX_INCLUDE_DIR}" ${GLSL_FLAGS} --variable-name ${SPIRV_VARIABLE_NAME} -o ${SPIRV_HEADER_FILE} ${SOURCE_FILE} --target-env ${SPIR_V_VERSION}
            MAIN_DEPENDENCY
                ${SOURCE_FILE}
-            DEPENDS
-                ${SHADER_DIR}
        )
        set(SHADER_HEADERS ${SHADER_HEADERS} ${SPIRV_HEADER_FILE})
    endif()
@ -172,7 +167,6 @@ foreach(FILEPATH IN ITEMS ${FIDELITYFX_FILES})
            ${SOURCE_FILE}
        DEPENDS
            ${INPUT_FILE}
-            ${SHADER_DIR}
            # HEADER_GENERATOR should be included here but msbuild seems to assume it's always modified
    )
    set(SHADER_HEADERS ${SHADER_HEADERS} ${SOURCE_HEADER_FILE})
--- a/src/video_core/texture_cache/texture_cache.h
+++ b/src/video_core/texture_cache/texture_cache.h
@ -2733,8 +2733,10 @@ void TextureCache<P>::PrepareImage(ImageId image_id, bool is_modification, bool
        }
    } else {
        RefreshContents(image, image_id);
+        if (!image.aliased_images.empty()) {
            SynchronizeAliases(image_id);
        }
+    }
    if (is_modification) {
        MarkModification(image);
    }
--- a/tools/gendynarm.cpp
+++ b/tools/gendynarm.cpp
Author	SHA1	Message	Date
MaranBr	90f4acd549	Ops	2026-04-02 14:56:52 +02:00
MaranBr	e6cd1033e9	Use shift operations for dynamic bit extraction for better performance	2026-04-02 14:54:12 +02:00
MaranBr	a8e40bac07	Fix IsScaled dynamic indexing reading wrong bit source	2026-04-02 14:54:12 +02:00
lizzie	d1b7824443	[meta] Restore base icon (#3809 ) Some checks failed tx-src / sources (push) Has been cancelled Details Check Strings / check-strings (push) Has been cancelled Details Merge AFTER april fools Signed-off-by: lizzie lizzie@eden-emu.dev Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3809 Reviewed-by: crueter <crueter@eden-emu.dev> Reviewed-by: CamilleLaVey <camillelavey99@gmail.com> Co-authored-by: lizzie <lizzie@eden-emu.dev> Co-committed-by: lizzie <lizzie@eden-emu.dev>	2026-04-02 06:06:46 +02:00
wildcard	34fa39eae8	[texture_cache] Skip alias synchronization in texture cache when the image has no aliases. (#3740 ) PrepareImage() is on a very hot path and previously called SynchronizeAliases() unconditionally. For most images, aliased_images` is empty, so this created unnecessary overhead, now we only synchronize only when image requires it Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3740 Reviewed-by: CamilleLaVey <camillelavey99@gmail.com> Co-authored-by: wildcard <wildcard@eden-emu.dev> Co-committed-by: wildcard <wildcard@eden-emu.dev>	2026-04-02 06:06:16 +02:00
lizzie	9ace6742d7	[docs] update multiplayer section with metaserver info (#3722 ) Some checks are pending tx-src / sources (push) Waiting to run Details Check Strings / check-strings (push) Waiting to run Details Signed-off-by: lizzie <lizzie@eden-emu.dev> Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3722 Reviewed-by: DraVee <chimera@dravee.dev> Reviewed-by: crueter <crueter@eden-emu.dev> Co-authored-by: lizzie <lizzie@eden-emu.dev> Co-committed-by: lizzie <lizzie@eden-emu.dev>	2026-04-01 21:59:37 +02:00
crueter	79f29abcba	[core] Fix renderdoc API garbage (#3816 ) Signed-off-by: crueter <crueter@eden-emu.dev> Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3816	2026-04-01 21:02:20 +02:00
crueter	3ce5463d2d	[cmake] Remove shader dir regeneration (#3813 ) Some checks are pending tx-src / sources (push) Waiting to run Details Check Strings / check-strings (push) Waiting to run Details We *do not* support BSD make. Period. Signed-off-by: crueter <crueter@eden-emu.dev> Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3813	2026-04-01 08:10:39 +02:00
lizzie	cae70c30fa	[dynarmic] fix GCC 12.2 complaints for regalloc.h (#3812 ) Signed-off-by: lizzie <lizzie@eden-emu.dev> Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3812 Reviewed-by: crueter <crueter@eden-emu.dev> Co-authored-by: lizzie <lizzie@eden-emu.dev> Co-committed-by: lizzie <lizzie@eden-emu.dev>	2026-04-01 07:26:46 +02:00
lizzie	bcceced96d	[dynarmic] fix GetDecoderTable() making the compiler nervous due to the big table that gets made into the stack (#3799 ) issue on stbale gcc debian Signed-off-by: lizzie <lizzie@eden-emu.dev> Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3799 Co-authored-by: lizzie <lizzie@eden-emu.dev> Co-committed-by: lizzie <lizzie@eden-emu.dev>	2026-04-01 07:05:42 +02:00
lizzie	82e374f66c	[meta] April Fools 2026 icon (#3802 ) Some checks are pending tx-src / sources (push) Waiting to run Details Check Strings / check-strings (push) Waiting to run Details art Signed-off-by: lizzie <lizzie@eden-emu.dev> Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3802 Reviewed-by: MaranBr <maranbr@eden-emu.dev> Reviewed-by: crueter <crueter@eden-emu.dev> Co-authored-by: lizzie <lizzie@eden-emu.dev> Co-committed-by: lizzie <lizzie@eden-emu.dev>	2026-04-01 03:07:50 +02:00