diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 88869917fd..431da33559 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -8,10 +8,6 @@
 #include <cstring>
 #include <optional>
 
-#if defined(_MSC_VER) && !defined(__clang__)
-#include <intrin.h>
-#endif
-
 #include "common/assert.h"
 #include "common/bit_util.h"
 #include "common/scope_exit.h"
@@ -28,16 +24,6 @@
 
 namespace Tegra::Engines {
 
-namespace {
-inline void PrefetchLine(const void* addr) {
-#if defined(_MSC_VER) && !defined(__clang__)
-    _mm_prefetch(static_cast<const char*>(addr), _MM_HINT_T0);
-#else
-    __builtin_prefetch(addr, 0, 1);
-#endif
-}
-} // namespace
-
 /// First register id that is actually a Macro call.
 constexpr u32 MacroRegistersStart = 0xE00;
 
@@ -323,34 +309,17 @@ void Maxwell3D::ConsumeSinkImpl() {
     if (control == Regs::ShadowRamControl::Track || control == Regs::ShadowRamControl::TrackWithFilter) {
         for (size_t i = 0; i < sink_size; ++i) {
             const auto [method, value] = method_sink[i];
-            if (i + 1 < sink_size) {
-                const u32 next = method_sink[i + 1].first;
-                PrefetchLine(&regs.reg_array[next]);
-                PrefetchLine(&shadow_state.reg_array[next]);
-                PrefetchLine(&dirty.tables[0][next]);
-            }
             shadow_state.reg_array[method] = value;
             ProcessDirtyRegisters(method, value);
         }
     } else if (control == Regs::ShadowRamControl::Replay) {
         for (size_t i = 0; i < sink_size; ++i) {
             const auto [method, value] = method_sink[i];
-            if (i + 1 < sink_size) {
-                const u32 next = method_sink[i + 1].first;
-                PrefetchLine(&regs.reg_array[next]);
-                PrefetchLine(&shadow_state.reg_array[next]);
-                PrefetchLine(&dirty.tables[0][next]);
-            }
             ProcessDirtyRegisters(method, shadow_state.reg_array[method]);
         }
     } else {
         for (size_t i = 0; i < sink_size; ++i) {
             const auto [method, value] = method_sink[i];
-            if (i + 1 < sink_size) {
-                const u32 next = method_sink[i + 1].first;
-                PrefetchLine(&regs.reg_array[next]);
-                PrefetchLine(&dirty.tables[0][next]);
-            }
             ProcessDirtyRegisters(method, value);
         }
     }