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Signed-off-by: lizzie lizzie@eden-emu.dev Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3195 Reviewed-by: DraVee <dravee@eden-emu.dev> Reviewed-by: Maufeat <sahyno1996@gmail.com> Co-authored-by: lizzie <lizzie@eden-emu.dev> Co-committed-by: lizzie <lizzie@eden-emu.dev>
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docs/dynarmic/Design.md
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docs/dynarmic/Design.md
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# Dynarmic Design Documentation
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Dynarmic is a dynamic recompiler for the ARMv6K architecture. Future plans for dynarmic include
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support for other versions of the ARM architecture, having a interpreter mode, and adding support
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for other architectures.
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Users of this library interact with it primarily through the interface provided in
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[`src/dynarmic/interface`](../src/dynarmic/interface). Users specify how dynarmic's CPU core interacts with
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the rest of their system providing an implementation of the relevant `UserCallbacks` interface.
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Users setup the CPU state using member functions of `Jit`, then call `Jit::Execute` to start CPU
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execution. The callbacks defined on `UserCallbacks` may be called from dynamically generated code,
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so users of the library should not depend on the stack being in a walkable state for unwinding.
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* A32: [`Jit`](../src/dynarmic/interface/A32/a32.h), [`UserCallbacks`](../src/dynarmic/interface/A32/config.h)
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* A64: [`Jit`](../src/dynarmic/interface/A64/a64.h), [`UserCallbacks`](../src/dynarmic/interface/A64/config.h)
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Dynarmic reads instructions from memory by calling `UserCallbacks::MemoryReadCode`. These
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instructions then pass through several stages:
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1. Decoding (Identifying what type of instruction it is and breaking it up into fields)
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2. Translation (Generation of high-level IR from the instruction)
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3. Optimization (Eliminiation of redundant microinstructions, other speed improvements)
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4. Emission (Generation of host-executable code into memory)
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5. Execution (Host CPU jumps to the start of emitted code and runs it)
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Using the A32 frontend with the x64 backend as an example:
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* Decoding is done by [double dispatch](https://en.wikipedia.org/wiki/Visitor_pattern) in
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[`src/frontend/A32/decoder/{arm.h,thumb16.h,thumb32.h}`](../src/dynarmic/frontend/A32/decoder/).
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* Translation is done by the visitors in [`src/dynarmic/frontend/A32/translate/translate_{arm,thumb}.cpp`](../src/dynarmic/frontend/A32/translate/).
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The function [`Translate`](../src/dynarmic/frontend/A32/translate/translate.h) takes a starting memory location,
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some CPU state, and memory reader callback and returns a basic block of IR.
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* The IR can be found under [`src/frontend/ir/`](../src/dynarmic/ir/).
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* Optimizations can be found under [`src/ir_opt/`](../src/dynarmic/ir/opt/).
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* Emission is done by `EmitX64` which can be found in [`src/dynarmic/backend/x64/emit_x64.{h,cpp}`](../src/dynarmic/backend/x64/).
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* Execution is performed by calling `BlockOfCode::RunCode` in [`src/dynarmic/backend/x64/block_of_code.{h,cpp}`](../src/dynarmic/backend/x64/).
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## Decoder
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The decoder is a double dispatch decoder. Each instruction is represented by a line in the relevant
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instruction table. Here is an example line from [`arm.h`](../src/dynarmic/frontend/A32/decoder/arm.h):
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INST(&V::arm_ADC_imm, "ADC (imm)", "cccc0010101Snnnnddddrrrrvvvvvvvv")
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(Details on this instruction can be found in section A8.8.1 of the ARMv7-A manual. This is encoding A1.)
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The first argument to INST is the member function to call on the visitor. The second argument is a user-readable
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instruction name. The third argument is a bit-representation of the instruction.
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### Instruction Bit-Representation
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Each character in the bitstring represents a bit. A `0` means that that bitposition **must** contain a zero. A `1`
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means that that bitposition **must** contain a one. A `-` means we don't care about the value at that bitposition.
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A string of the same character represents a field. In the above example, the first four bits `cccc` represent the
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four-bit-long cond field of the ARM Add with Carry (immediate) instruction.
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The visitor would have to have a function named `arm_ADC_imm` with 6 arguments, one for each field (`cccc`, `S`,
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`nnnn`, `dddd`, `rrrr`, `vvvvvvvv`). If there is a mismatch of field number with argument number, a compile-time
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error results.
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## Translator
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The translator is a visitor that uses the decoder to decode instructions. The translator generates IR code with the
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help of the [`IREmitter` class](../src/dynarmic/ir/ir_emitter.h). An example of a translation function follows:
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bool ArmTranslatorVisitor::arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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u32 imm32 = ArmExpandImm(rotate, imm8);
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// ADC{S}<c> <Rd>, <Rn>, #<imm>
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if (ConditionPassed(cond)) {
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auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.GetCFlag());
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if (d == Reg::PC) {
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ASSERT(!S);
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ir.ALUWritePC(result.result);
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(d, result.result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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}
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}
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return true;
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}
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where `ir` is an instance of the `IRBuilder` class. Each member function of the `IRBuilder` class constructs
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an IR microinstruction.
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## Intermediate Representation
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Dynarmic uses an ordered SSA intermediate representation. It is very vaguely similar to those found in other
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similar projects like redream, nucleus, and xenia. Major differences are: (1) the abundance of context
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microinstructions whereas those projects generally only have two (`load_context`/`store_context`), (2) the
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explicit handling of flags as their own values, and (3) very different basic block edge handling.
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The intention of the context microinstructions and explicit flag handling is to allow for future optimizations. The
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differences in the way edges are handled are a quirk of the current implementation and dynarmic will likely add a
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function analyser in the medium-term future.
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Dynarmic's intermediate representation is typed. Each microinstruction may take zero or more arguments and may
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return zero or more arguments. A subset of the microinstructions available is documented below.
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A complete list of microinstructions can be found in [src/dynarmic/ir/opcodes.inc](../src/dynarmic/ir/opcodes.inc).
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The below lists some commonly used microinstructions.
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### Immediate: Imm{U1,U8,U32,RegRef}
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<u1> ImmU1(u1 value)
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<u8> ImmU8(u8 value)
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<u32> ImmU32(u32 value)
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<RegRef> ImmRegRef(Arm::Reg gpr)
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These instructions take a `bool`, `u8` or `u32` value and wraps it up in an IR node so that they can be used
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by the IR.
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### Context: {Get,Set}Register
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<u32> GetRegister(<RegRef> reg)
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<void> SetRegister(<RegRef> reg, <u32> value)
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Gets and sets `JitState::Reg[reg]`. Note that `SetRegister(Arm::Reg::R15, _)` is disallowed by IRBuilder.
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Use `{ALU,BX}WritePC` instead.
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Note that sequences like `SetRegister(R4, _)` followed by `GetRegister(R4)` are
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optimized away.
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### Context: {Get,Set}{N,Z,C,V}Flag
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<u1> GetNFlag()
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<void> SetNFlag(<u1> value)
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<u1> GetZFlag()
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<void> SetZFlag(<u1> value)
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<u1> GetCFlag()
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<void> SetCFlag(<u1> value)
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<u1> GetVFlag()
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<void> SetVFlag(<u1> value)
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Gets and sets bits in `JitState::Cpsr`. Similarly to registers redundant get/sets are optimized away.
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### Context: BXWritePC
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<void> BXWritePC(<u32> value)
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This should probably be the last instruction in a translation block unless you're doing something fancy.
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This microinstruction sets R15 and CPSR.T as appropriate.
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### Callback: CallSupervisor
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<void> CallSupervisor(<u32> svc_imm32)
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This should probably be the last instruction in a translation block unless you're doing something fancy.
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### Calculation: LastSignificant{Half,Byte}
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<u16> LeastSignificantHalf(<u32> value)
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<u8> LeastSignificantByte(<u32> value)
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Extract a u16 and u8 respectively from a u32.
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### Calculation: MostSignificantBit, IsZero
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<u1> MostSignificantBit(<u32> value)
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<u1> IsZero(<u32> value)
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These are used to implement ARM flags N and Z. These can often be optimized away by the backend into a host flag read.
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### Calculation: LogicalShiftLeft
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(<u32> result, <u1> carry_out) LogicalShiftLeft(<u32> operand, <u8> shift_amount, <u1> carry_in)
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Pseudocode:
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if shift_amount == 0:
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return (operand, carry_in)
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x = operand * (2 ** shift_amount)
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result = Bits<31,0>(x)
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carry_out = Bit<32>(x)
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return (result, carry_out)
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This follows ARM semantics. Note `shift_amount` is not masked to 5 bits (like `SHL` does on x64).
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### Calculation: LogicalShiftRight
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(<u32> result, <u1> carry_out) LogicalShiftLeft(<u32> operand, <u8> shift_amount, <u1> carry_in)
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Pseudocode:
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if shift_amount == 0:
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return (operand, carry_in)
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x = ZeroExtend(operand, from_size: 32, to_size: shift_amount+32)
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result = Bits<shift_amount+31,shift_amount>(x)
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carry_out = Bit<shift_amount-1>(x)
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return (result, carry_out)
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This follows ARM semantics. Note `shift_amount` is not masked to 5 bits (like `SHR` does on x64).
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### Calculation: ArithmeticShiftRight
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(<u32> result, <u1> carry_out) ArithmeticShiftRight(<u32> operand, <u8> shift_amount, <u1> carry_in)
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Pseudocode:
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if shift_amount == 0:
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return (operand, carry_in)
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x = SignExtend(operand, from_size: 32, to_size: shift_amount+32)
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result = Bits<shift_amount+31,shift_amount>(x)
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carry_out = Bit<shift_amount-1>(x)
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return (result, carry_out)
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This follows ARM semantics. Note `shift_amount` is not masked to 5 bits (like `SAR` does on x64).
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### Calcuation: RotateRight
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(<u32> result, <u1> carry_out) RotateRight(<u32> operand, <u8> shift_amount, <u1> carry_in)
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Pseudocode:
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if shift_amount == 0:
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return (operand, carry_in)
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shift_amount %= 32
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result = (operand << shift_amount) | (operand >> (32 - shift_amount))
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carry_out = Bit<31>(result)
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return (result, carry_out)
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### Calculation: AddWithCarry
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(<u32> result, <u1> carry_out, <u1> overflow) AddWithCarry(<u32> a, <u32> b, <u1> carry_in)
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a + b + carry_in
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### Calculation: SubWithCarry
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(<u32> result, <u1> carry_out, <u1> overflow) SubWithCarry(<u32> a, <u32> b, <u1> carry_in)
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This has equivalent semantics to `AddWithCarry(a, Not(b), carry_in)`.
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a - b - !carry_in
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### Calculation: And
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<u32> And(<u32> a, <u32> b)
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### Calculation: Eor
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<u32> Eor(<u32> a, <u32> b)
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Exclusive OR (i.e.: XOR)
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### Calculation: Or
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<u32> Or(<u32> a, <u32> b)
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### Calculation: Not
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<u32> Not(<u32> value)
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### Callback: {Read,Write}Memory{8,16,32,64}
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```c++
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<u8> ReadMemory8(<u32> vaddr)
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<u8> ReadMemory16(<u32> vaddr)
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<u8> ReadMemory32(<u32> vaddr)
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<u8> ReadMemory64(<u32> vaddr)
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<void> WriteMemory8(<u32> vaddr, <u8> value_to_store)
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<void> WriteMemory16(<u32> vaddr, <u16> value_to_store)
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<void> WriteMemory32(<u32> vaddr, <u32> value_to_store)
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<void> WriteMemory64(<u32> vaddr, <u64> value_to_store)
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```
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Memory access.
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### Terminal: Interpret
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```c++
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SetTerm(IR::Term::Interpret{next})
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```
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This terminal instruction calls the interpreter, starting at `next`.
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The interpreter must interpret exactly one instruction.
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### Terminal: ReturnToDispatch
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```c++
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SetTerm(IR::Term::ReturnToDispatch{})
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```
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This terminal instruction returns control to the dispatcher.
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The dispatcher will use the value in R15 to determine what comes next.
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### Terminal: LinkBlock
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|
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```c++
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SetTerm(IR::Term::LinkBlock{next})
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```
|
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This terminal instruction jumps to the basic block described by `next` if we have enough
|
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cycles remaining. If we do not have enough cycles remaining, we return to the
|
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dispatcher, which will return control to the host.
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### Terminal: LinkBlockFast
|
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|
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```c++
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SetTerm(IR::Term::LinkBlockFast{next})
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```
|
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This terminal instruction jumps to the basic block described by `next` unconditionally.
|
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This promises guarantees that must be held at runtime - i.e that the program wont hang,
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### Terminal: PopRSBHint
|
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|
||||
```c++
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SetTerm(IR::Term::PopRSBHint{})
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```
|
||||
|
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This terminal instruction checks the top of the Return Stack Buffer against R15.
|
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If RSB lookup fails, control is returned to the dispatcher.
|
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This is an optimization for faster function calls. A backend that doesn't support
|
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this optimization or doesn't have a RSB may choose to implement this exactly as
|
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`ReturnToDispatch`.
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### Terminal: If
|
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|
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```c++
|
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SetTerm(IR::Term::If{cond, term_then, term_else})
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```
|
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|
||||
This terminal instruction conditionally executes one terminal or another depending
|
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on the run-time state of the ARM flags.
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# Register Allocation (x64 Backend)
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`HostLoc`s contain values. A `HostLoc` ("host value location") is either a host CPU register or a host spill location.
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Values once set cannot be changed. Values can however be moved by the register allocator between `HostLoc`s. This is
|
||||
handled by the register allocator itself and code that uses the register allocator need not and should not move values
|
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between registers.
|
||||
|
||||
The register allocator is based on three concepts: `Use`, `Def` and `Scratch`.
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|
||||
* `Use`: The use of a value.
|
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* `Define`: The definition of a value, this is the only time when a value is set.
|
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* `Scratch`: Allocate a register that can be freely modified as one wishes.
|
||||
|
||||
Note that `Use`ing a value decrements its `use_count` by one. When the `use_count` reaches zero the value is discarded and no longer exists.
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||||
|
||||
The member functions on `RegAlloc` are just a combination of the above concepts.
|
||||
|
||||
The following registers are reserved for internal use and should NOT participate in register allocation:
|
||||
- `%xmm0`, `%xmm1`, `%xmm2`: Used as scratch in exclusive memory access.
|
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- `%rsp`: Stack pointer.
|
||||
- `%r15`: JIT pointer
|
||||
- `%r14`: Page table pointer.
|
||||
- `%r13`: Fastmem pointer.
|
||||
|
||||
The layout convenes `%r15` as the JIT state pointer - while it may be tempting to turn it into a synthetic pointer, keeping an entire register (out of 12 available) is preferable over inlining a directly computed immediate.
|
||||
|
||||
Do NEVER modify `%r15`, we must make it clear that this register is "immutable" for the entirety of the JIT block duration.
|
||||
|
||||
### `Scratch`
|
||||
|
||||
```c++
|
||||
Xbyak::Reg64 ScratchGpr(HostLocList desired_locations = any_gpr);
|
||||
Xbyak::Xmm ScratchXmm(HostLocList desired_locations = any_xmm);
|
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```
|
||||
|
||||
At runtime, allocate one of the registers in `desired_locations`. You are free to modify the register. The register is discarded at the end of the allocation scope.
|
||||
|
||||
### Pure `Use`
|
||||
|
||||
```c++
|
||||
Xbyak::Reg64 UseGpr(Argument& arg);
|
||||
Xbyak::Xmm UseXmm(Argument& arg);
|
||||
OpArg UseOpArg(Argument& arg);
|
||||
void Use(Argument& arg, HostLoc host_loc);
|
||||
```
|
||||
|
||||
At runtime, the value corresponding to `arg` will be placed a register. The actual register is determined by
|
||||
which one of the above functions is called. `UseGpr` places it in an unused GPR, `UseXmm` places it
|
||||
in an unused XMM register, `UseOpArg` might be in a register or might be a memory location, and `Use` allows
|
||||
you to specify a specific register (GPR or XMM) to use.
|
||||
|
||||
This register **must not** have it's value changed.
|
||||
|
||||
### `UseScratch`
|
||||
|
||||
```c++
|
||||
Xbyak::Reg64 UseScratchGpr(Argument& arg);
|
||||
Xbyak::Xmm UseScratchXmm(Argument& arg);
|
||||
void UseScratch(Argument& arg, HostLoc host_loc);
|
||||
```
|
||||
|
||||
At runtime, the value corresponding to `arg` will be placed a register. The actual register is determined by
|
||||
which one of the above functions is called. `UseScratchGpr` places it in an unused GPR, `UseScratchXmm` places it
|
||||
in an unused XMM register, and `UseScratch` allows you to specify a specific register (GPR or XMM) to use.
|
||||
|
||||
The return value is the register allocated to you.
|
||||
|
||||
You are free to modify the value in the register. The register is discarded at the end of the allocation scope.
|
||||
|
||||
### `Define` as register
|
||||
|
||||
A `Define` is the defintion of a value. This is the only time when a value may be set.
|
||||
|
||||
```c++
|
||||
void DefineValue(IR::Inst* inst, const Xbyak::Reg& reg);
|
||||
```
|
||||
|
||||
By calling `DefineValue`, you are stating that you wish to define the value for `inst`, and you have written the
|
||||
value to the specified register `reg`.
|
||||
|
||||
### `Define`ing as an alias of a different value
|
||||
|
||||
Adding a `Define` to an existing value.
|
||||
|
||||
```c++
|
||||
void DefineValue(IR::Inst* inst, Argument& arg);
|
||||
```
|
||||
|
||||
You are declaring that the value for `inst` is the same as the value for `arg`. No host machine instructions are
|
||||
emitted.
|
||||
|
||||
## When to use each?
|
||||
|
||||
* Prefer `Use` to `UseScratch` where possible.
|
||||
* Prefer the `OpArg` variants where possible.
|
||||
* Prefer to **not** use the specific `HostLoc` variants where possible.
|
||||
|
||||
# Return Stack Buffer Optimization (x64 Backend)
|
||||
|
||||
One of the optimizations that dynarmic does is block-linking. Block-linking is done when
|
||||
the destination address of a jump is available at JIT-time. Instead of returning to the
|
||||
dispatcher at the end of a block we can perform block-linking: just jump directly to the
|
||||
next block. This is beneficial because returning to the dispatcher can often be quite
|
||||
expensive.
|
||||
|
||||
What should we do in cases when we can't predict the destination address? The eponymous
|
||||
example is when executing a return statement at the end of a function; the return address
|
||||
is not statically known at compile time.
|
||||
|
||||
We deal with this by using a return stack buffer: When we execute a call instruction,
|
||||
we push our prediction onto the RSB. When we execute a return instruction, we pop a
|
||||
prediction off the RSB. If the prediction is a hit, we immediately jump to the relevant
|
||||
compiled block. Otherwise, we return to the dispatcher.
|
||||
|
||||
This is the essential idea behind this optimization.
|
||||
|
||||
## `UniqueHash`
|
||||
|
||||
One complication dynarmic has is that a compiled block is not uniquely identifiable by
|
||||
the PC alone, but bits in the FPSCR and CPSR are also relevant. We resolve this by
|
||||
computing a 64-bit `UniqueHash` that is guaranteed to uniquely identify a block.
|
||||
|
||||
```c++
|
||||
u64 LocationDescriptor::UniqueHash() const {
|
||||
// This value MUST BE UNIQUE.
|
||||
// This calculation has to match up with EmitX64::EmitTerminalPopRSBHint
|
||||
u64 pc_u64 = u64(arm_pc) << 32;
|
||||
u64 fpscr_u64 = u64(fpscr.Value());
|
||||
u64 t_u64 = cpsr.T() ? 1 : 0;
|
||||
u64 e_u64 = cpsr.E() ? 2 : 0;
|
||||
return pc_u64 | fpscr_u64 | t_u64 | e_u64;
|
||||
}
|
||||
```
|
||||
|
||||
## Our implementation isn't actually a stack
|
||||
|
||||
Dynarmic's RSB isn't actually a stack. It was implemented as a ring buffer because
|
||||
that showed better performance in tests.
|
||||
|
||||
### RSB Structure
|
||||
|
||||
The RSB is implemented as a ring buffer. `rsb_ptr` is the index of the insertion
|
||||
point. Each element in `rsb_location_descriptors` is a `UniqueHash` and they
|
||||
each correspond to an element in `rsb_codeptrs`. `rsb_codeptrs` contains the
|
||||
host addresses for the corresponding the compiled blocks.
|
||||
|
||||
`RSBSize` was chosen by performance testing. Note that this is bigger than the
|
||||
size of the real RSB in hardware (which has 3 entries). Larger RSBs than 8
|
||||
showed degraded performance.
|
||||
|
||||
```c++
|
||||
struct JitState {
|
||||
// ...
|
||||
|
||||
static constexpr size_t RSBSize = 8; // MUST be a power of 2.
|
||||
u32 rsb_ptr = 0;
|
||||
std::array<u64, RSBSize> rsb_location_descriptors;
|
||||
std::array<u64, RSBSize> rsb_codeptrs;
|
||||
void ResetRSB();
|
||||
|
||||
// ...
|
||||
};
|
||||
```
|
||||
|
||||
### RSB Push
|
||||
|
||||
We insert our prediction at the insertion point iff the RSB doesn't already
|
||||
contain a prediction with the same `UniqueHash`.
|
||||
|
||||
```c++
|
||||
void EmitX64::EmitPushRSB(IR::Block&, IR::Inst* inst) {
|
||||
using namespace Xbyak::util;
|
||||
|
||||
ASSERT(inst->GetArg(0).IsImmediate());
|
||||
u64 imm64 = inst->GetArg(0).GetU64();
|
||||
|
||||
Xbyak::Reg64 code_ptr_reg = reg_alloc.ScratchGpr(code, {HostLoc::RCX});
|
||||
Xbyak::Reg64 loc_desc_reg = reg_alloc.ScratchGpr(code);
|
||||
Xbyak::Reg32 index_reg = reg_alloc.ScratchGpr(code).cvt32();
|
||||
u64 code_ptr = unique_hash_to_code_ptr.find(imm64) != unique_hash_to_code_ptr.end()
|
||||
? u64(unique_hash_to_code_ptr[imm64])
|
||||
: u64(code->GetReturnFromRunCodeAddress());
|
||||
|
||||
code->mov(index_reg, dword[code.ABI_JIT_PTR + offsetof(JitState, rsb_ptr)]);
|
||||
code->add(index_reg, 1);
|
||||
code->and_(index_reg, u32(JitState::RSBSize - 1));
|
||||
|
||||
code->mov(loc_desc_reg, u64(imm64));
|
||||
CodePtr patch_location = code->getCurr<CodePtr>();
|
||||
patch_unique_hash_locations[imm64].emplace_back(patch_location);
|
||||
code->mov(code_ptr_reg, u64(code_ptr)); // This line has to match up with EmitX64::Patch.
|
||||
code->EnsurePatchLocationSize(patch_location, 10);
|
||||
|
||||
Xbyak::Label label;
|
||||
for (size_t i = 0; i < JitState::RSBSize; ++i) {
|
||||
code->cmp(loc_desc_reg, qword[code.ABI_JIT_PTR + offsetof(JitState, rsb_location_descriptors) + i * sizeof(u64)]);
|
||||
code->je(label, code->T_SHORT);
|
||||
}
|
||||
|
||||
code->mov(dword[code.ABI_JIT_PTR + offsetof(JitState, rsb_ptr)], index_reg);
|
||||
code->mov(qword[code.ABI_JIT_PTR + index_reg.cvt64() * 8 + offsetof(JitState, rsb_location_descriptors)], loc_desc_reg);
|
||||
code->mov(qword[code.ABI_JIT_PTR + index_reg.cvt64() * 8 + offsetof(JitState, rsb_codeptrs)], code_ptr_reg);
|
||||
code->L(label);
|
||||
}
|
||||
```
|
||||
|
||||
In pseudocode:
|
||||
|
||||
```c++
|
||||
for (i := 0 .. RSBSize-1)
|
||||
if (rsb_location_descriptors[i] == imm64)
|
||||
goto label;
|
||||
rsb_ptr++;
|
||||
rsb_ptr %= RSBSize;
|
||||
rsb_location_desciptors[rsb_ptr] = imm64; //< The UniqueHash
|
||||
rsb_codeptr[rsb_ptr] = /* codeptr corresponding to the UniqueHash */;
|
||||
label:
|
||||
```
|
||||
|
||||
## RSB Pop
|
||||
|
||||
To check if a predicition is in the RSB, we linearly scan the RSB.
|
||||
|
||||
```c++
|
||||
void EmitX64::EmitTerminalPopRSBHint(IR::Term::PopRSBHint, IR::LocationDescriptor initial_location) {
|
||||
using namespace Xbyak::util;
|
||||
|
||||
// This calculation has to match up with IREmitter::PushRSB
|
||||
code->mov(ecx, MJitStateReg(Arm::Reg::PC));
|
||||
code->shl(rcx, 32);
|
||||
code->mov(ebx, dword[code.ABI_JIT_PTR + offsetof(JitState, FPSCR_mode)]);
|
||||
code->or_(ebx, dword[code.ABI_JIT_PTR + offsetof(JitState, CPSR_et)]);
|
||||
code->or_(rbx, rcx);
|
||||
|
||||
code->mov(rax, u64(code->GetReturnFromRunCodeAddress()));
|
||||
for (size_t i = 0; i < JitState::RSBSize; ++i) {
|
||||
code->cmp(rbx, qword[code.ABI_JIT_PTR + offsetof(JitState, rsb_location_descriptors) + i * sizeof(u64)]);
|
||||
code->cmove(rax, qword[code.ABI_JIT_PTR + offsetof(JitState, rsb_codeptrs) + i * sizeof(u64)]);
|
||||
}
|
||||
|
||||
code->jmp(rax);
|
||||
}
|
||||
```
|
||||
|
||||
In pseudocode:
|
||||
|
||||
```c++
|
||||
rbx := ComputeUniqueHash()
|
||||
rax := ReturnToDispatch
|
||||
for (i := 0 .. RSBSize-1)
|
||||
if (rbx == rsb_location_descriptors[i])
|
||||
rax = rsb_codeptrs[i]
|
||||
goto rax
|
||||
```
|
||||
|
||||
# Fast memory (Fastmem)
|
||||
|
||||
The main way of accessing memory in JITed programs is via an invoked function, say "Read()" and "Write()". On our translator, such functions usually take a sizable amounts of code space (push + call + pop). Trash the i-cache (due to an indirect call) and overall make code emission more bloated.
|
||||
|
||||
The solution? Delegate invalid accesses to a dedicated arena, similar to a swap. The main idea behind such mechanism is to allow the OS to transmit page faults from invalid accesses into the JIT translator directly, bypassing address space calls, while this sacrifices i-cache coherency, it allows for smaller code-size and "faster" throguhput.
|
||||
|
||||
Many kernels however, do not support fast signal dispatching (Solaris, OpenBSD, FreeBSD). Only Linux and Windows support relatively "fast" signal dispatching. Hence this feature is better suited for them only.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
In x86_64 for example, when a page fault occurs, the CPU will transmit via control registers and the stack (see `IRETQ`) the appropriate arguments for a page fault handler, the OS then will transform that into something that can be sent into userspace.
|
||||
|
||||
Most modern OSes implement kernel-page-table-isolation, which means a set of system calls will invoke a context switch (not often used syscalls), whereas others are handled by the same process address space (the smaller kernel portion, often used syscalls) without needing a context switch. This effect can be negated on systems with PCID (up to 4096 unique IDs).
|
||||
|
||||
Signal dispatching takes a performance hit from reloading `%cr3` - but Linux does something more clever to avoid reloads: VDSO will take care of the entire thing in the same address space. Making dispatching as costly as an indirect call - without the hazards of increased code size.
|
||||
|
||||
The main downside from this is the constant i-cache trashing and pipeline hazards introduced by the VDSO signal handlers. However on most benchmarks fastmem does perform faster than without (Linux only). This also abuses the fact of continous address space emulation by using an arena - which can then be potentially transparently mapped into a hugepage, reducing TLB walk times.
|
||||
4
docs/dynarmic/Fastmem.svg
Normal file
4
docs/dynarmic/Fastmem.svg
Normal file
File diff suppressed because one or more lines are too long
|
After Width: | Height: | Size: 128 KiB |
4
docs/dynarmic/HostToGuest.svg
Normal file
4
docs/dynarmic/HostToGuest.svg
Normal file
File diff suppressed because one or more lines are too long
|
After Width: | Height: | Size: 98 KiB |
391
docs/dynarmic/README.md
Normal file
391
docs/dynarmic/README.md
Normal file
|
|
@ -0,0 +1,391 @@
|
|||
Dynarmic
|
||||
========
|
||||
|
||||
A dynamic recompiler for ARM.
|
||||
|
||||
Highlight features:
|
||||
|
||||
- Fast dynamic binary translation via Just-in-Time compilation
|
||||
- Clean API
|
||||
- Implemented in modern C++20
|
||||
- Hooks exposed for easy code instrumentation
|
||||
- Code injection support for very fine-grained instrumentation
|
||||
- Support for unusual address space setups (bring-your-own memory system)
|
||||
- Native support for most popular operating systems (Windows, macOS, Linux, FreeBSD, OpenBSD, NetBSD, Android)
|
||||
|
||||
*Please note that an adversarial guest program [can determine if it is being run under dynarmic](#disadvantages-of-dynarmic). Preventing this is not a goal of this project.*
|
||||
|
||||
### Supported guest architectures
|
||||
|
||||
* v3
|
||||
* v4
|
||||
* v4T
|
||||
* v5TE
|
||||
* v6K
|
||||
* v6T2
|
||||
* v7A
|
||||
* 32-bit v8
|
||||
* 64-bit v8
|
||||
|
||||
You can specify the specific guest version using [ArchVersion](src/dynarmic/interface/A32/arch_version.h).
|
||||
|
||||
There are no plans to support v1 or v2.
|
||||
|
||||
### Supported host architectures
|
||||
|
||||
* x86-64
|
||||
* AArch64
|
||||
|
||||
There are no plans to support any 32-bit architecture.
|
||||
|
||||
Important API Changes in v6.x Series
|
||||
------------------------------------
|
||||
|
||||
* **v6.7.0**
|
||||
* To support use cases where one wants to have the guest to have the same address space as the host, `nullptr` is now a valid value for `fastmem_pointer`.
|
||||
**This change is not backwards-compatible.** If you were previously using `nullptr` to represent an invalid fastmem arena, you will now have to use `std::nullopt`.
|
||||
|
||||
|
||||
Documentation
|
||||
-------------
|
||||
|
||||
Design documentation can be found at [./Design.md](./Design.md).
|
||||
|
||||
|
||||
Usage Example
|
||||
-------------
|
||||
|
||||
The below is a minimal example. Bring-your-own memory system.
|
||||
|
||||
```cpp
|
||||
#include <array>
|
||||
#include <cstdint>
|
||||
#include <cstdio>
|
||||
#include <exception>
|
||||
|
||||
#include "dynarmic/interface/A32/a32.h"
|
||||
#include "dynarmic/interface/A32/config.h"
|
||||
|
||||
using u8 = std::uint8_t;
|
||||
using u16 = std::uint16_t;
|
||||
using u32 = std::uint32_t;
|
||||
using u64 = std::uint64_t;
|
||||
|
||||
class MyEnvironment final : public Dynarmic::A32::UserCallbacks {
|
||||
public:
|
||||
u64 ticks_left = 0;
|
||||
std::array<u8, 2048> memory{};
|
||||
|
||||
u8 MemoryRead8(u32 vaddr) override {
|
||||
if (vaddr >= memory.size()) {
|
||||
return 0;
|
||||
}
|
||||
return memory[vaddr];
|
||||
}
|
||||
|
||||
u16 MemoryRead16(u32 vaddr) override {
|
||||
return u16(MemoryRead8(vaddr)) | u16(MemoryRead8(vaddr + 1)) << 8;
|
||||
}
|
||||
|
||||
u32 MemoryRead32(u32 vaddr) override {
|
||||
return u32(MemoryRead16(vaddr)) | u32(MemoryRead16(vaddr + 2)) << 16;
|
||||
}
|
||||
|
||||
u64 MemoryRead64(u32 vaddr) override {
|
||||
return u64(MemoryRead32(vaddr)) | u64(MemoryRead32(vaddr + 4)) << 32;
|
||||
}
|
||||
|
||||
void MemoryWrite8(u32 vaddr, u8 value) override {
|
||||
if (vaddr >= memory.size()) {
|
||||
return;
|
||||
}
|
||||
memory[vaddr] = value;
|
||||
}
|
||||
|
||||
void MemoryWrite16(u32 vaddr, u16 value) override {
|
||||
MemoryWrite8(vaddr, u8(value));
|
||||
MemoryWrite8(vaddr + 1, u8(value >> 8));
|
||||
}
|
||||
|
||||
void MemoryWrite32(u32 vaddr, u32 value) override {
|
||||
MemoryWrite16(vaddr, u16(value));
|
||||
MemoryWrite16(vaddr + 2, u16(value >> 16));
|
||||
}
|
||||
|
||||
void MemoryWrite64(u32 vaddr, u64 value) override {
|
||||
MemoryWrite32(vaddr, u32(value));
|
||||
MemoryWrite32(vaddr + 4, u32(value >> 32));
|
||||
}
|
||||
|
||||
void InterpreterFallback(u32 pc, size_t num_instructions) override {
|
||||
// This is never called in practice.
|
||||
std::terminate();
|
||||
}
|
||||
|
||||
void CallSVC(u32 swi) override {
|
||||
// Do something.
|
||||
}
|
||||
|
||||
void ExceptionRaised(u32 pc, Dynarmic::A32::Exception exception) override {
|
||||
// Do something.
|
||||
}
|
||||
|
||||
void AddTicks(u64 ticks) override {
|
||||
if (ticks > ticks_left) {
|
||||
ticks_left = 0;
|
||||
return;
|
||||
}
|
||||
ticks_left -= ticks;
|
||||
}
|
||||
|
||||
u64 GetTicksRemaining() override {
|
||||
return ticks_left;
|
||||
}
|
||||
};
|
||||
|
||||
int main(int argc, char** argv) {
|
||||
MyEnvironment env;
|
||||
Dynarmic::A32::UserConfig user_config;
|
||||
user_config.callbacks = &env;
|
||||
Dynarmic::A32::Jit cpu{user_config};
|
||||
|
||||
// Execute at least 1 instruction.
|
||||
// (Note: More than one instruction may be executed.)
|
||||
env.ticks_left = 1;
|
||||
|
||||
// Write some code to memory.
|
||||
env.MemoryWrite16(0, 0x0088); // lsls r0, r1, #2
|
||||
env.MemoryWrite16(2, 0xE7FE); // b +#0 (infinite loop)
|
||||
|
||||
// Setup registers.
|
||||
cpu.Regs()[0] = 1;
|
||||
cpu.Regs()[1] = 2;
|
||||
cpu.Regs()[15] = 0; // PC = 0
|
||||
cpu.SetCpsr(0x00000030); // Thumb mode
|
||||
|
||||
// Execute!
|
||||
cpu.Run();
|
||||
|
||||
// Here we would expect cpu.Regs()[0] == 8
|
||||
printf("R0: %u\n", cpu.Regs()[0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
```
|
||||
|
||||
Alternatives to Dynarmic
|
||||
------------------------
|
||||
|
||||
Here are some projects with the same goals as dynarmic:
|
||||
|
||||
* [Unicorn](https://www.unicorn-engine.org/) - Recompiling multi-architecture CPU emulator, based on QEMU
|
||||
* [SkyEye](http://skyeye.sourceforge.net) - Cached interpreter for ARM
|
||||
|
||||
More general alternatives:
|
||||
|
||||
* [tARMac](https://davidsharp.com/tarmac/) - Tarmac's use of armlets was initial inspiration for us to use an intermediate representation
|
||||
* [QEMU](https://www.qemu.org/) - Recompiling multi-architecture system emulator
|
||||
* [VisUAL](https://salmanarif.bitbucket.io/visual/index.html) - Visual ARM UAL emulator intended for education
|
||||
* A wide variety of other recompilers, interpreters and emulators can be found embedded in other projects, here are some we would recommend looking at:
|
||||
* [firebird's recompiler](https://github.com/nspire-emus/firebird) - Takes more of a call-threaded approach to recompilation
|
||||
* [higan's arm7tdmi emulator](https://github.com/higan-emu/higan/tree/master/higan/component/processor/arm7tdmi) - Very clean code-style
|
||||
* [arm-js by ozaki-r](https://github.com/ozaki-r/arm-js) - Emulates ARMv7A and some peripherals of Versatile Express, in the browser
|
||||
|
||||
Disadvantages of Dynarmic
|
||||
-------------------------
|
||||
|
||||
In the pursuit of speed, some behavior not commonly depended upon is elided. Therefore this emulator does not match spec.
|
||||
Please note that this would mean that a guest application can easily determine if it is being run under instrumentation.
|
||||
|
||||
Known examples:
|
||||
|
||||
* Only user-mode is emulated, there is no emulation of any other privilege levels.
|
||||
* FPSR state is approximate.
|
||||
* Misaligned loads/stores are not appropriately trapped in certain cases.
|
||||
* Exclusive monitor behavior may not match any known physical processor.
|
||||
|
||||
No formal verification has been done, and no security assessment has been made.
|
||||
Use this code base at your own risk.
|
||||
|
||||
Legal
|
||||
-----
|
||||
|
||||
dynarmic is under a 0BSD license. See LICENSE.txt for more details.
|
||||
|
||||
dynarmic uses several other libraries, whose licenses are included below:
|
||||
|
||||
### biscuit
|
||||
|
||||
```
|
||||
Copyright 2021 Lioncash/Lioncache
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
IN THE SOFTWARE.
|
||||
```
|
||||
|
||||
### catch
|
||||
|
||||
```
|
||||
Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
Permission is hereby granted, free of charge, to any person or organization
|
||||
obtaining a copy of the software and accompanying documentation covered by
|
||||
this license (the "Software") to use, reproduce, display, distribute,
|
||||
execute, and transmit the Software, and to prepare derivative works of the
|
||||
Software, and to permit third-parties to whom the Software is furnished to
|
||||
do so, all subject to the following:
|
||||
|
||||
The copyright notices in the Software and this entire statement, including
|
||||
the above license grant, this restriction and the following disclaimer,
|
||||
must be included in all copies of the Software, in whole or in part, and
|
||||
all derivative works of the Software, unless such copies or derivative
|
||||
works are solely in the form of machine-executable object code generated by
|
||||
a source language processor.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
DEALINGS IN THE SOFTWARE.
|
||||
```
|
||||
|
||||
### fmt
|
||||
|
||||
```
|
||||
Copyright (c) 2012 - 2016, Victor Zverovich
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
```
|
||||
|
||||
### mcl & oaknut
|
||||
|
||||
```
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2022 merryhime <https://mary.rs>
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
```
|
||||
|
||||
### unordered_dense
|
||||
|
||||
```
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2022 Martin Leitner-Ankerl
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
```
|
||||
|
||||
### xbyak
|
||||
|
||||
```
|
||||
Copyright (c) 2007 MITSUNARI Shigeo
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
Neither the name of the copyright owner nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
-----------------------------------------------------------------------------
|
||||
ソースコード形式かバイナリ形式か、変更するかしないかを問わず、以下の条件を満た
|
||||
す場合に限り、再頒布および使用が許可されます。
|
||||
|
||||
ソースコードを再頒布する場合、上記の著作権表示、本条件一覧、および下記免責条項
|
||||
を含めること。
|
||||
バイナリ形式で再頒布する場合、頒布物に付属のドキュメント等の資料に、上記の著作
|
||||
権表示、本条件一覧、および下記免責条項を含めること。
|
||||
書面による特別の許可なしに、本ソフトウェアから派生した製品の宣伝または販売促進
|
||||
に、著作権者の名前またはコントリビューターの名前を使用してはならない。
|
||||
本ソフトウェアは、著作権者およびコントリビューターによって「現状のまま」提供さ
|
||||
れており、明示黙示を問わず、商業的な使用可能性、および特定の目的に対する適合性
|
||||
に関する暗黙の保証も含め、またそれに限定されない、いかなる保証もありません。
|
||||
著作権者もコントリビューターも、事由のいかんを問わず、 損害発生の原因いかんを
|
||||
問わず、かつ責任の根拠が契約であるか厳格責任であるか（過失その他の）不法行為で
|
||||
あるかを問わず、仮にそのような損害が発生する可能性を知らされていたとしても、
|
||||
本ソフトウェアの使用によって発生した（代替品または代用サービスの調達、使用の
|
||||
喪失、データの喪失、利益の喪失、業務の中断も含め、またそれに限定されない）直接
|
||||
損害、間接損害、偶発的な損害、特別損害、懲罰的損害、または結果損害について、
|
||||
一切責任を負わないものとします。
|
||||
```
|
||||
Loading…
Add table
Add a link
Reference in a new issue