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"A64: ADD" passes (except on PC check)

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Signed-off-by: lizzie <lizzie@eden-emu.dev>
This commit is contained in:
lizzie 2025-11-04 03:41:22 +00:00
parent 28a50d54f0
commit e69dec8779
4 changed files with 31 additions and 9 deletions
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4
src/dynarmic/src/dynarmic/backend/ppc64/a64_interface.cpp
View file

@ -34,6 +34,10 @@ CodePtr A64AddressSpace::GetOrEmit(IR::LocationDescriptor desc) {
}; };
IR::Block ir_block = A64::Translate(A64::LocationDescriptor{desc}, get_code, {conf.define_unpredictable_behaviour, conf.wall_clock_cntpct}); IR::Block ir_block = A64::Translate(A64::LocationDescriptor{desc}, get_code, {conf.define_unpredictable_behaviour, conf.wall_clock_cntpct});
Optimization::Optimize(ir_block, conf, {}); Optimization::Optimize(ir_block, conf, {});
fmt::print("IR:\n");
fmt::print("{}\n", IR::DumpBlock(ir_block));
const EmittedBlockInfo block_info = Emit(std::move(ir_block)); const EmittedBlockInfo block_info = Emit(std::move(ir_block));
block_infos.insert_or_assign(desc.Value(), block_info); block_infos.insert_or_assign(desc.Value(), block_info);

7
src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64.cpp
View file

@ -23,8 +23,11 @@ template<>
void EmitIR<IR::Opcode::Void>(powah::Context&, EmitContext&, IR::Inst*) {} void EmitIR<IR::Opcode::Void>(powah::Context&, EmitContext&, IR::Inst*) {}
template<> template<>
void EmitIR<IR::Opcode::Identity>(powah::Context&, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::Identity>(powah::Context& code, EmitContext& ctx, IR::Inst* inst) {
ASSERT(false && "unimp"); powah::GPR const result = ctx.reg_alloc.ScratchGpr();
powah::GPR const source = ctx.reg_alloc.UseGpr(inst->GetArg(0));
code.MR(result, source);
ctx.reg_alloc.DefineValue(inst, result);
} }
template<> template<>

4
src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a32.cpp
View file

@ -80,7 +80,7 @@ void EmitIR<IR::Opcode::A32GetRegister>(powah::Context& code, EmitContext& ctx,
if (inst->GetArg(0).GetType() == IR::Type::A32Reg) { if (inst->GetArg(0).GetType() == IR::Type::A32Reg) {
powah::GPR const result = ctx.reg_alloc.ScratchGpr(); powah::GPR const result = ctx.reg_alloc.ScratchGpr();
code.ADDI(result, PPC64::RJIT, A32::RegNumber(inst->GetArg(0).GetA32RegRef()) * sizeof(u32)); code.ADDI(result, PPC64::RJIT, A32::RegNumber(inst->GetArg(0).GetA32RegRef()) * sizeof(u32));
code.LD(result, result, offsetof(A32JitState, regs)); code.LWZ(result, result, offsetof(A32JitState, regs));
ctx.reg_alloc.DefineValue(inst, result); ctx.reg_alloc.DefineValue(inst, result);
} else { } else {
ASSERT(false && "unimp"); ASSERT(false && "unimp");
@ -108,7 +108,7 @@ void EmitIR<IR::Opcode::A32SetRegister>(powah::Context& code, EmitContext& ctx,
if (inst->GetArg(0).GetType() == IR::Type::A32Reg) { if (inst->GetArg(0).GetType() == IR::Type::A32Reg) {
powah::GPR const addr = ctx.reg_alloc.ScratchGpr(); powah::GPR const addr = ctx.reg_alloc.ScratchGpr();
code.ADDI(addr, PPC64::RJIT, A32::RegNumber(inst->GetArg(0).GetA32RegRef()) * sizeof(u32)); code.ADDI(addr, PPC64::RJIT, A32::RegNumber(inst->GetArg(0).GetA32RegRef()) * sizeof(u32));
code.STD(value, addr, offsetof(A32JitState, regs)); code.STW(value, addr, offsetof(A32JitState, regs));
} else { } else {
ASSERT(false && "unimp"); ASSERT(false && "unimp");
} }

25
src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a64.cpp
View file

@ -4,7 +4,8 @@
#include <powah_emit.hpp> #include <powah_emit.hpp>
#include <fmt/ostream.h> #include <fmt/ostream.h>
#include "dynarmic/backend/ppc64/a32_core.h" #include "dynarmic/frontend/A64/a64_types.h"
#include "dynarmic/backend/ppc64/a64_core.h"
#include "dynarmic/backend/ppc64/abi.h" #include "dynarmic/backend/ppc64/abi.h"
#include "dynarmic/backend/ppc64/emit_context.h" #include "dynarmic/backend/ppc64/emit_context.h"
#include "dynarmic/backend/ppc64/emit_ppc64.h" #include "dynarmic/backend/ppc64/emit_ppc64.h"
@ -46,8 +47,15 @@ void EmitIR<IR::Opcode::A64GetW>(powah::Context&, EmitContext&, IR::Inst*) {
} }
template<> template<>
void EmitIR<IR::Opcode::A64GetX>(powah::Context&, EmitContext&, IR::Inst*) { void EmitIR<IR::Opcode::A64GetX>(powah::Context& code, EmitContext& ctx, IR::Inst* inst) {
ASSERT(false && "unimp"); if (inst->GetArg(0).GetType() == IR::Type::A64Reg) {
powah::GPR const result = ctx.reg_alloc.ScratchGpr();
code.ADDI(result, PPC64::RJIT, A64::RegNumber(inst->GetArg(0).GetA64RegRef()) * sizeof(u64));
code.LD(result, result, offsetof(A64JitState, regs));
ctx.reg_alloc.DefineValue(inst, result);
} else {
ASSERT(false && "unimp");
}
} }
template<> template<>
@ -86,8 +94,15 @@ void EmitIR<IR::Opcode::A64SetW>(powah::Context&, EmitContext&, IR::Inst*) {
} }
template<> template<>
void EmitIR<IR::Opcode::A64SetX>(powah::Context&, EmitContext&, IR::Inst*) { void EmitIR<IR::Opcode::A64SetX>(powah::Context& code, EmitContext& ctx, IR::Inst* inst) {
ASSERT(false && "unimp"); powah::GPR const value = ctx.reg_alloc.UseGpr(inst->GetArg(1));
if (inst->GetArg(0).GetType() == IR::Type::A64Reg) {
powah::GPR const addr = ctx.reg_alloc.ScratchGpr();
code.ADDI(addr, PPC64::RJIT, A64::RegNumber(inst->GetArg(0).GetA64RegRef()) * sizeof(u64));
code.STD(value, addr, offsetof(A64JitState, regs));
} else {
ASSERT(false && "unimp");
}
} }
template<> template<>