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https://git.eden-emu.dev/eden-emu/eden
synced 2026-05-25 19:47:06 +02:00
[vulkan] Adjusting provoking vertex last.
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parent
0d518e7303
commit
dbcbce57b0
9 changed files with 41 additions and 7 deletions
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@ -84,7 +84,6 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d, DynamicFe
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depth_enabled.Assign(regs.zeta_enable != 0 ? 1 : 0);
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depth_enabled.Assign(regs.zeta_enable != 0 ? 1 : 0);
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depth_format.Assign(static_cast<u32>(regs.zeta.format));
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depth_format.Assign(static_cast<u32>(regs.zeta.format));
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y_negate.Assign(regs.window_origin.mode != Maxwell::WindowOrigin::Mode::UpperLeft ? 1 : 0);
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y_negate.Assign(regs.window_origin.mode != Maxwell::WindowOrigin::Mode::UpperLeft ? 1 : 0);
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provoking_vertex_last.Assign(regs.provoking_vertex == Maxwell::ProvokingVertex::Last ? 1 : 0);
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conservative_raster_enable.Assign(regs.conservative_raster_enable != 0 ? 1 : 0);
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conservative_raster_enable.Assign(regs.conservative_raster_enable != 0 ? 1 : 0);
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smooth_lines.Assign(regs.line_anti_alias_enable != 0 ? 1 : 0);
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smooth_lines.Assign(regs.line_anti_alias_enable != 0 ? 1 : 0);
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alpha_to_coverage_enabled.Assign(regs.anti_alias_alpha_control.alpha_to_coverage != 0 ? 1 : 0);
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alpha_to_coverage_enabled.Assign(regs.anti_alias_alpha_control.alpha_to_coverage != 0 ? 1 : 0);
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@ -214,9 +214,8 @@ struct FixedPipelineState {
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BitField<5, 1, u32> depth_enabled;
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BitField<5, 1, u32> depth_enabled;
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BitField<6, 5, u32> depth_format;
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BitField<6, 5, u32> depth_format;
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BitField<11, 1, u32> y_negate;
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BitField<11, 1, u32> y_negate;
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BitField<12, 1, u32> provoking_vertex_last;
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BitField<12, 1, u32> conservative_raster_enable;
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BitField<13, 1, u32> conservative_raster_enable;
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BitField<13, 1, u32> smooth_lines;
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BitField<14, 1, u32> smooth_lines;
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BitField<15, 1, u32> alpha_to_coverage_enabled;
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BitField<15, 1, u32> alpha_to_coverage_enabled;
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BitField<16, 1, u32> alpha_to_one_enabled;
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BitField<16, 1, u32> alpha_to_one_enabled;
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BitField<17, 3, Tegra::Engines::Maxwell3D::EngineHint> app_stage;
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BitField<17, 3, Tegra::Engines::Maxwell3D::EngineHint> app_stage;
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@ -741,9 +741,7 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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VkPipelineRasterizationProvokingVertexStateCreateInfoEXT provoking_vertex{
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VkPipelineRasterizationProvokingVertexStateCreateInfoEXT provoking_vertex{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_PROVOKING_VERTEX_STATE_CREATE_INFO_EXT,
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_PROVOKING_VERTEX_STATE_CREATE_INFO_EXT,
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.pNext = nullptr,
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.pNext = nullptr,
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.provokingVertexMode = key.state.provoking_vertex_last != 0
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.provokingVertexMode = VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT,
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? VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT
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: VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT,
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};
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};
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if (IsLine(input_assembly_topology) && device.IsExtLineRasterizationSupported()) {
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if (IsLine(input_assembly_topology) && device.IsExtLineRasterizationSupported()) {
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@ -918,6 +916,10 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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}
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}
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}
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}
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if (device.IsExtProvokingVertexSupported()) {
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dynamic_states.push_back(VK_DYNAMIC_STATE_PROVOKING_VERTEX_EXT);
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}
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const VkPipelineDynamicStateCreateInfo dynamic_state_ci{
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const VkPipelineDynamicStateCreateInfo dynamic_state_ci{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
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.pNext = nullptr,
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.pNext = nullptr,
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@ -1042,6 +1042,10 @@ void RasterizerVulkan::UpdateDynamicStates() {
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UpdateLogicOp(regs);
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UpdateLogicOp(regs);
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}
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}
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if (device.IsExtProvokingVertexSupported()) {
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UpdateProvokingVertex(regs);
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}
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if (device.IsExtExtendedDynamicState3EnablesSupported()) {
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if (device.IsExtExtendedDynamicState3EnablesSupported()) {
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using namespace Tegra::Engines;
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using namespace Tegra::Engines;
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if (device.GetDriverID() == VkDriverIdKHR::VK_DRIVER_ID_AMD_OPEN_SOURCE ||
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if (device.GetDriverID() == VkDriverIdKHR::VK_DRIVER_ID_AMD_OPEN_SOURCE ||
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@ -1617,6 +1621,20 @@ void RasterizerVulkan::UpdateFrontFace(Tegra::Engines::Maxwell3D::Regs& regs) {
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[front_face](vk::CommandBuffer cmdbuf) { cmdbuf.SetFrontFaceEXT(front_face); });
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[front_face](vk::CommandBuffer cmdbuf) { cmdbuf.SetFrontFaceEXT(front_face); });
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}
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}
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void RasterizerVulkan::UpdateProvokingVertex(Tegra::Engines::Maxwell3D::Regs& regs) {
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if (!device.IsExtProvokingVertexSupported()) {
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return;
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}
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if (!state_tracker.TouchProvokingVertex()) {
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return;
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}
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const auto mode = regs.provoking_vertex == Maxwell::ProvokingVertex::Last
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? VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT
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: VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT;
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scheduler.Record([mode](vk::CommandBuffer cmdbuf) { cmdbuf.SetProvokingVertexEXT(mode); });
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}
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void RasterizerVulkan::UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs) {
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void RasterizerVulkan::UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs) {
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if (!state_tracker.TouchStencilOp()) {
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if (!state_tracker.TouchStencilOp()) {
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return;
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return;
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@ -186,6 +186,7 @@ private:
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void UpdateAlphaToCoverageEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateAlphaToCoverageEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateAlphaToOneEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateAlphaToOneEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateFrontFace(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateFrontFace(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateProvokingVertex(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateStencilTestEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateStencilTestEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateLogicOp(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateLogicOp(Tegra::Engines::Maxwell3D::Regs& regs);
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@ -166,6 +166,10 @@ void SetupDirtyFrontFace(Tables& tables) {
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table[OFF(window_origin)] = FrontFace;
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table[OFF(window_origin)] = FrontFace;
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}
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}
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void SetupDirtyProvokingVertex(Tables& tables) {
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tables[0][OFF(provoking_vertex)] = ProvokingVertex;
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}
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void SetupDirtyStencilOp(Tables& tables) {
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void SetupDirtyStencilOp(Tables& tables) {
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auto& table = tables[0];
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auto& table = tables[0];
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table[OFF(stencil_front_op.fail)] = StencilOp;
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table[OFF(stencil_front_op.fail)] = StencilOp;
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@ -250,6 +254,7 @@ void StateTracker::SetupTables(Tegra::Control::ChannelState& channel_state) {
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SetupDirtyStateEnable(tables);
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SetupDirtyStateEnable(tables);
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SetupDirtyDepthCompareOp(tables);
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SetupDirtyDepthCompareOp(tables);
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SetupDirtyFrontFace(tables);
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SetupDirtyFrontFace(tables);
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SetupDirtyProvokingVertex(tables);
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SetupDirtyStencilOp(tables);
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SetupDirtyStencilOp(tables);
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SetupDirtyBlending(tables);
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SetupDirtyBlending(tables);
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SetupDirtyViewportSwizzles(tables);
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SetupDirtyViewportSwizzles(tables);
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@ -248,6 +248,10 @@ public:
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return Exchange(Dirty::FrontFace, false);
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return Exchange(Dirty::FrontFace, false);
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}
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}
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bool TouchProvokingVertex() {
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return Exchange(Dirty::ProvokingVertex, false);
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}
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bool TouchStencilOp() {
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bool TouchStencilOp() {
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return Exchange(Dirty::StencilOp, false);
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return Exchange(Dirty::StencilOp, false);
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}
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}
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@ -159,6 +159,7 @@ void Load(VkDevice device, DeviceDispatch& dld) noexcept {
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X(vkCmdSetPatchControlPointsEXT);
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X(vkCmdSetPatchControlPointsEXT);
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X(vkCmdSetLineWidth);
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X(vkCmdSetLineWidth);
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X(vkCmdSetPrimitiveTopologyEXT);
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X(vkCmdSetPrimitiveTopologyEXT);
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X(vkCmdSetProvokingVertexEXT);
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X(vkCmdSetStencilOpEXT);
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X(vkCmdSetStencilOpEXT);
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X(vkCmdSetStencilTestEnableEXT);
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X(vkCmdSetStencilTestEnableEXT);
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X(vkCmdSetVertexInputEXT);
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X(vkCmdSetVertexInputEXT);
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@ -254,6 +254,7 @@ struct DeviceDispatch : InstanceDispatch {
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PFN_vkCmdSetLogicOpEXT vkCmdSetLogicOpEXT{};
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PFN_vkCmdSetLogicOpEXT vkCmdSetLogicOpEXT{};
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PFN_vkCmdSetLineWidth vkCmdSetLineWidth{};
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PFN_vkCmdSetLineWidth vkCmdSetLineWidth{};
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PFN_vkCmdSetPrimitiveTopologyEXT vkCmdSetPrimitiveTopologyEXT{};
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PFN_vkCmdSetPrimitiveTopologyEXT vkCmdSetPrimitiveTopologyEXT{};
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PFN_vkCmdSetProvokingVertexEXT vkCmdSetProvokingVertexEXT{};
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PFN_vkCmdSetScissor vkCmdSetScissor{};
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PFN_vkCmdSetScissor vkCmdSetScissor{};
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PFN_vkCmdSetStencilCompareMask vkCmdSetStencilCompareMask{};
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PFN_vkCmdSetStencilCompareMask vkCmdSetStencilCompareMask{};
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PFN_vkCmdSetStencilOpEXT vkCmdSetStencilOpEXT{};
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PFN_vkCmdSetStencilOpEXT vkCmdSetStencilOpEXT{};
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@ -1529,6 +1530,10 @@ public:
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dld->vkCmdSetPrimitiveTopologyEXT(handle, primitive_topology);
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dld->vkCmdSetPrimitiveTopologyEXT(handle, primitive_topology);
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}
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}
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void SetProvokingVertexEXT(VkProvokingVertexModeEXT provoking_vertex_mode) const noexcept {
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dld->vkCmdSetProvokingVertexEXT(handle, provoking_vertex_mode);
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}
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void SetStencilOpEXT(VkStencilFaceFlags face_mask, VkStencilOp fail_op, VkStencilOp pass_op,
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void SetStencilOpEXT(VkStencilFaceFlags face_mask, VkStencilOp fail_op, VkStencilOp pass_op,
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VkStencilOp depth_fail_op, VkCompareOp compare_op) const noexcept {
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VkStencilOp depth_fail_op, VkCompareOp compare_op) const noexcept {
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dld->vkCmdSetStencilOpEXT(handle, face_mask, fail_op, pass_op, depth_fail_op, compare_op);
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dld->vkCmdSetStencilOpEXT(handle, face_mask, fail_op, pass_op, depth_fail_op, compare_op);
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