From b4516101ad13db70c3fb5e8c655bc009465414db Mon Sep 17 00:00:00 2001 From: lizzie Date: Mon, 30 Mar 2026 02:52:11 +0000 Subject: [PATCH] fix asserts --- src/dynarmic/CMakeLists.txt | 1 - src/dynarmic/src/dynarmic/CMakeLists.txt | 3 - .../dynarmic/backend/arm64/a32_interface.cpp | 6 +- .../dynarmic/backend/arm64/a64_interface.cpp | 6 +- src/dynarmic/src/dynarmic/backend/arm64/abi.h | 4 +- .../dynarmic/backend/arm64/address_space.cpp | 8 +- .../src/dynarmic/backend/arm64/emit_arm64.cpp | 16 +- .../dynarmic/backend/arm64/emit_arm64_a32.cpp | 12 +- .../arm64/emit_arm64_data_processing.cpp | 22 +- .../arm64/emit_arm64_floating_point.cpp | 12 +- .../backend/arm64/emit_arm64_packed.cpp | 5 +- .../backend/arm64/emit_arm64_saturation.cpp | 10 +- .../backend/arm64/emit_arm64_vector.cpp | 18 +- .../emit_arm64_vector_floating_point.cpp | 12 +- .../backend/arm64/exclusive_monitor.cpp | 2 +- .../src/dynarmic/backend/arm64/reg_alloc.cpp | 80 +-- .../src/dynarmic/backend/arm64/reg_alloc.h | 2 +- .../backend/exception_handler_macos.cpp | 4 +- .../backend/exception_handler_posix.cpp | 4 +- .../backend/riscv64/a32_address_space.cpp | 4 +- .../backend/riscv64/a32_interface.cpp | 8 +- .../backend/riscv64/a64_interface.cpp | 8 +- .../src/dynarmic/backend/riscv64/code_block.h | 4 +- .../dynarmic/backend/riscv64/emit_riscv64.cpp | 20 +- .../backend/riscv64/emit_riscv64_a32.cpp | 58 +- .../riscv64/emit_riscv64_a32_coprocessor.cpp | 14 +- .../riscv64/emit_riscv64_a32_memory.cpp | 34 +- .../backend/riscv64/emit_riscv64_a64.cpp | 72 +-- .../riscv64/emit_riscv64_a64_memory.cpp | 42 +- .../riscv64/emit_riscv64_cryptography.cpp | 32 +- .../riscv64/emit_riscv64_data_processing.cpp | 172 +++--- .../riscv64/emit_riscv64_floating_point.cpp | 176 +++--- .../backend/riscv64/emit_riscv64_packed.cpp | 68 +-- .../riscv64/emit_riscv64_saturation.cpp | 44 +- .../backend/riscv64/emit_riscv64_vector.cpp | 550 +++++++++--------- .../emit_riscv64_vector_floating_point.cpp | 134 ++--- .../emit_riscv64_vector_saturation.cpp | 32 +- .../dynarmic/backend/riscv64/reg_alloc.cpp | 44 +- .../src/dynarmic/backend/riscv64/reg_alloc.h | 2 +- .../src/dynarmic/backend/x64/a32_emit_x64.cpp | 22 +- .../dynarmic/backend/x64/a32_interface.cpp | 8 +- .../src/dynarmic/backend/x64/a32_jitstate.cpp | 8 +- .../src/dynarmic/backend/x64/a64_emit_x64.cpp | 8 +- .../dynarmic/backend/x64/a64_interface.cpp | 10 +- .../dynarmic/backend/x64/block_of_code.cpp | 8 +- .../dynarmic/backend/x64/constant_pool.cpp | 4 +- .../src/dynarmic/backend/x64/emit_x64.cpp | 8 +- .../backend/x64/emit_x64_data_processing.cpp | 4 +- .../backend/x64/emit_x64_floating_point.cpp | 14 +- .../backend/x64/emit_x64_memory.cpp.inc | 12 +- .../dynarmic/backend/x64/emit_x64_memory.h | 2 +- .../backend/x64/emit_x64_saturation.cpp | 6 +- .../src/dynarmic/backend/x64/emit_x64_sha.cpp | 8 +- .../dynarmic/backend/x64/emit_x64_vector.cpp | 62 +- .../x64/emit_x64_vector_floating_point.cpp | 10 +- .../backend/x64/exception_handler_windows.cpp | 8 +- .../backend/x64/exclusive_monitor.cpp | 2 +- .../src/dynarmic/backend/x64/hostloc.h | 10 +- src/dynarmic/src/dynarmic/backend/x64/oparg.h | 2 +- .../src/dynarmic/backend/x64/reg_alloc.cpp | 104 ++-- .../src/dynarmic/backend/x64/reg_alloc.h | 22 +- src/dynarmic/src/dynarmic/common/fp/fpcr.h | 8 +- .../dynarmic/common/fp/op/FPRecipEstimate.cpp | 2 +- .../src/dynarmic/common/fp/op/FPRoundInt.cpp | 4 +- .../src/dynarmic/common/fp/op/FPToFixed.cpp | 8 +- .../dynarmic/common/fp/process_exception.cpp | 14 +- .../src/dynarmic/common/fp/process_nan.cpp | 4 +- .../src/dynarmic/common/fp/unpacked.cpp | 4 +- .../src/dynarmic/common/llvm_disassemble.cpp | 4 +- .../dynarmic/frontend/A32/a32_ir_emitter.cpp | 22 +- .../src/dynarmic/frontend/A32/a32_types.h | 10 +- .../A32/translate/conditional_state.cpp | 6 +- .../A32/translate/impl/a32_translate_impl.cpp | 4 +- .../A32/translate/impl/a32_translate_impl.h | 2 +- .../A32/translate/impl/asimd_misc.cpp | 2 +- .../impl/asimd_one_reg_modified_immediate.cpp | 2 +- .../translate/impl/asimd_two_regs_scalar.cpp | 2 +- .../translate/impl/asimd_two_regs_shift.cpp | 4 +- .../A32/translate/impl/load_store.cpp | 22 +- .../translate/impl/status_register_access.cpp | 2 +- .../frontend/A32/translate/impl/thumb16.cpp | 2 +- ...b32_data_processing_modified_immediate.cpp | 14 +- ...data_processing_plain_binary_immediate.cpp | 4 +- ...umb32_data_processing_shifted_register.cpp | 14 +- .../frontend/A32/translate/impl/vfp.cpp | 18 +- .../frontend/A32/translate/translate_arm.cpp | 4 +- .../A32/translate/translate_thumb.cpp | 4 +- .../dynarmic/frontend/A64/a64_ir_emitter.h | 2 +- .../src/dynarmic/frontend/A64/a64_types.h | 6 +- .../frontend/A64/translate/a64_translate.cpp | 2 +- .../frontend/A64/translate/impl/impl.cpp | 26 +- .../impl/load_store_multiple_structures.cpp | 5 +- .../impl/load_store_register_immediate.cpp | 7 +- .../impl/simd_scalar_shift_by_immediate.cpp | 2 +- .../impl/simd_scalar_x_indexed_element.cpp | 4 +- .../impl/simd_shift_by_immediate.cpp | 2 +- .../translate/impl/simd_three_same_extra.cpp | 4 +- .../impl/simd_vector_x_indexed_element.cpp | 4 +- .../frontend/decoder/decoder_detail.h | 6 +- .../src/dynarmic/frontend/decoder/matcher.h | 4 +- src/dynarmic/src/dynarmic/frontend/imm.cpp | 2 +- src/dynarmic/src/dynarmic/frontend/imm.h | 4 +- src/dynarmic/src/dynarmic/ir/basic_block.cpp | 6 +- src/dynarmic/src/dynarmic/ir/basic_block.h | 4 +- src/dynarmic/src/dynarmic/ir/ir_emitter.h | 136 ++--- .../src/dynarmic/ir/microinstruction.cpp | 18 +- .../src/dynarmic/ir/microinstruction.h | 8 +- src/dynarmic/src/dynarmic/ir/opt_passes.cpp | 10 +- src/dynarmic/src/dynarmic/ir/value.cpp | 34 +- src/dynarmic/src/dynarmic/ir/value.h | 6 +- src/dynarmic/src/dynarmic/mcl/bit.hpp | 16 +- .../src/dynarmic/mcl/intrusive_list.hpp | 18 +- src/dynarmic/tests/A32/fuzz_arm.cpp | 2 +- src/dynarmic/tests/A32/fuzz_thumb.cpp | 4 +- .../tests/A32/test_arm_instructions.cpp | 2 +- src/dynarmic/tests/A32/testenv.h | 10 +- src/dynarmic/tests/A64/testenv.h | 10 +- src/dynarmic/tests/decoder_tests.cpp | 4 +- src/dynarmic/tests/fuzz_util.cpp | 4 +- .../tests/unicorn_emu/a32_unicorn.cpp | 4 +- .../tests/unicorn_emu/a64_unicorn.cpp | 4 +- 121 files changed, 1329 insertions(+), 1324 deletions(-) diff --git a/src/dynarmic/CMakeLists.txt b/src/dynarmic/CMakeLists.txt index 4c4bf86d3e..0d8dcfba7c 100644 --- a/src/dynarmic/CMakeLists.txt +++ b/src/dynarmic/CMakeLists.txt @@ -32,7 +32,6 @@ else() endif() option(DYNARMIC_ENABLE_NO_EXECUTE_SUPPORT "Enables support for systems that require W^X" ${REQUIRE_WX}) -option(DYNARMIC_IGNORE_ASSERTS "Ignore asserts" ON) option(DYNARMIC_TESTS_USE_UNICORN "Enable fuzzing tests against unicorn" OFF) CMAKE_DEPENDENT_OPTION(DYNARMIC_USE_LLVM "Support disassembly of jitted x86_64 code using LLVM" OFF "NOT YUZU_DISABLE_LLVM" OFF) diff --git a/src/dynarmic/src/dynarmic/CMakeLists.txt b/src/dynarmic/src/dynarmic/CMakeLists.txt index 878e39e2c2..852b417616 100644 --- a/src/dynarmic/src/dynarmic/CMakeLists.txt +++ b/src/dynarmic/src/dynarmic/CMakeLists.txt @@ -376,9 +376,6 @@ endif() if (DYNARMIC_ENABLE_NO_EXECUTE_SUPPORT) target_compile_definitions(dynarmic PRIVATE DYNARMIC_ENABLE_NO_EXECUTE_SUPPORT=1) endif() -if (DYNARMIC_IGNORE_ASSERTS) - target_compile_definitions(dynarmic PRIVATE MCL_IGNORE_ASSERTS=1) -endif() if (CMAKE_SYSTEM_NAME STREQUAL "Windows") target_compile_definitions(dynarmic PRIVATE FMT_USE_WINDOWS_H=0) endif() diff --git a/src/dynarmic/src/dynarmic/backend/arm64/a32_interface.cpp b/src/dynarmic/src/dynarmic/backend/arm64/a32_interface.cpp index 904806c719..29b3f8459e 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/a32_interface.cpp +++ b/src/dynarmic/src/dynarmic/backend/arm64/a32_interface.cpp @@ -10,7 +10,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/backend/arm64/a32_address_space.h" @@ -31,7 +31,7 @@ struct Jit::Impl final { , core(conf) {} HaltReason Run() { - ASSERT(!jit_interface->is_executing); + assert(!jit_interface->is_executing); PerformRequestedCacheInvalidation(static_cast(Atomic::Load(&halt_reason))); jit_interface->is_executing = true; @@ -42,7 +42,7 @@ struct Jit::Impl final { } HaltReason Step() { - ASSERT(!jit_interface->is_executing); + assert(!jit_interface->is_executing); PerformRequestedCacheInvalidation(static_cast(Atomic::Load(&halt_reason))); jit_interface->is_executing = true; diff --git a/src/dynarmic/src/dynarmic/backend/arm64/a64_interface.cpp b/src/dynarmic/src/dynarmic/backend/arm64/a64_interface.cpp index c1c589162c..8143ec7280 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/a64_interface.cpp +++ b/src/dynarmic/src/dynarmic/backend/arm64/a64_interface.cpp @@ -10,7 +10,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/backend/arm64/a64_address_space.h" @@ -31,7 +31,7 @@ struct Jit::Impl final { , core(conf) {} HaltReason Run() { - ASSERT(!is_executing); + assert(!is_executing); PerformRequestedCacheInvalidation(static_cast(Atomic::Load(&halt_reason))); is_executing = true; HaltReason hr = core.Run(current_address_space, current_state, &halt_reason); @@ -41,7 +41,7 @@ struct Jit::Impl final { } HaltReason Step() { - ASSERT(!is_executing); + assert(!is_executing); PerformRequestedCacheInvalidation(static_cast(Atomic::Load(&halt_reason))); is_executing = true; HaltReason hr = core.Step(current_address_space, current_state, &halt_reason); diff --git a/src/dynarmic/src/dynarmic/backend/arm64/abi.h b/src/dynarmic/src/dynarmic/backend/arm64/abi.h index c8da6ccfa4..55331b0885 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/abi.h +++ b/src/dynarmic/src/dynarmic/backend/arm64/abi.h @@ -11,7 +11,7 @@ #include #include "common/common_types.h" -#include "common/assert.h" +#include #include @@ -57,7 +57,7 @@ constexpr RegisterList ToRegList(oaknut::Reg reg) { if (reg.is_vector()) { return RegisterList{1} << (reg.index() + 32); } - ASSERT(reg.index() != 31 && "ZR not allowed in reg list"); + assert(reg.index() != 31 && "ZR not allowed in reg list"); if (reg.index() == -1) { return RegisterList{1} << 31; } diff --git a/src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp b/src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp index 6b59871b0a..c2ea232057 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp +++ b/src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp @@ -31,7 +31,7 @@ AddressSpace::AddressSpace(size_t code_cache_size) , code(mem.ptr(), mem.ptr()) , fastmem_manager(exception_handler) { - ASSERT(code_cache_size <= 128 * 1024 * 1024 && "code_cache_size > 128 MiB not currently supported"); + assert(code_cache_size <= 128 * 1024 * 1024 && "code_cache_size > 128 MiB not currently supported"); exception_handler.Register(mem, code_cache_size); exception_handler.SetFastmemCallback([this](u64 host_pc) { @@ -115,9 +115,9 @@ EmittedBlockInfo AddressSpace::Emit(IR::Block block) { EmittedBlockInfo block_info = EmitArm64(code, std::move(block), GetEmitConfig(), fastmem_manager); - ASSERT(block_entries.insert({block.Location(), block_info.entry_point}).second); - ASSERT(reverse_block_entries.insert({block_info.entry_point, block.Location()}).second); - ASSERT(block_infos.insert({block_info.entry_point, block_info}).second); + assert(block_entries.insert({block.Location(), block_info.entry_point}).second); + assert(reverse_block_entries.insert({block_info.entry_point, block.Location()}).second); + assert(block_infos.insert({block_info.entry_point, block_info}).second); Link(block_info); RelinkForDescriptor(block.Location(), block_info.entry_point); diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp index 104d0a452c..8b2a41cbf6 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp +++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp @@ -54,7 +54,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, } auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[0].IsImmediate()); + assert(args[0].IsImmediate()); const IR::LocationDescriptor target{args[0].GetImmediateU64()}; code.LDR(Wscratch2, SP, offsetof(StackLayout, rsb_ptr)); @@ -71,19 +71,19 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, template<> void EmitIR(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) { [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(ctx.reg_alloc.WasValueDefined(inst)); + assert(ctx.reg_alloc.WasValueDefined(inst)); } template<> void EmitIR(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) { [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(ctx.reg_alloc.WasValueDefined(inst)); + assert(ctx.reg_alloc.WasValueDefined(inst)); } template<> void EmitIR(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) { [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(ctx.reg_alloc.WasValueDefined(inst)); + assert(ctx.reg_alloc.WasValueDefined(inst)); } template<> @@ -149,13 +149,13 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext& c template<> void EmitIR(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) { [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(ctx.reg_alloc.WasValueDefined(inst)); + assert(ctx.reg_alloc.WasValueDefined(inst)); } template<> void EmitIR(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) { [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(ctx.reg_alloc.WasValueDefined(inst)); + assert(ctx.reg_alloc.WasValueDefined(inst)); } template<> @@ -206,9 +206,9 @@ EmittedBlockInfo EmitArm64(oaknut::CodeGenerator& code, IR::Block block, const E ebi.entry_point = code.xptr(); if (ctx.block.GetCondition() == IR::Cond::AL) { - ASSERT(!ctx.block.HasConditionFailedLocation()); + assert(!ctx.block.HasConditionFailedLocation()); } else { - ASSERT(ctx.block.HasConditionFailedLocation()); + assert(ctx.block.HasConditionFailedLocation()); oaknut::Label pass; pass = conf.emit_cond(code, ctx, ctx.block.GetCondition()); diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32.cpp index 213403b4ba..8e2797f65e 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32.cpp +++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32.cpp @@ -211,7 +211,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef(); - ASSERT(A32::IsSingleExtReg(reg)); + assert(A32::IsSingleExtReg(reg)); const size_t index = static_cast(reg) - static_cast(A32::ExtReg::S0); auto Sresult = ctx.reg_alloc.WriteS(inst); @@ -225,7 +225,7 @@ void EmitIR(oaknut::CodeGenerator& code, E template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef(); - ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg)); + assert(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg)); if (A32::IsDoubleExtReg(reg)) { const size_t index = static_cast(reg) - static_cast(A32::ExtReg::D0); @@ -243,7 +243,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext& template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef(); - ASSERT(A32::IsDoubleExtReg(reg)); + assert(A32::IsDoubleExtReg(reg)); const size_t index = static_cast(reg) - static_cast(A32::ExtReg::D0); auto Dresult = ctx.reg_alloc.WriteD(inst); @@ -271,7 +271,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef(); - ASSERT(A32::IsSingleExtReg(reg)); + assert(A32::IsSingleExtReg(reg)); const size_t index = static_cast(reg) - static_cast(A32::ExtReg::S0); auto args = ctx.reg_alloc.GetArgumentInfo(inst); @@ -286,7 +286,7 @@ void EmitIR(oaknut::CodeGenerator& code, E template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef(); - ASSERT(A32::IsDoubleExtReg(reg)); + assert(A32::IsDoubleExtReg(reg)); const size_t index = static_cast(reg) - static_cast(A32::ExtReg::D0); auto args = ctx.reg_alloc.GetArgumentInfo(inst); @@ -301,7 +301,7 @@ void EmitIR(oaknut::CodeGenerator& code, E template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef(); - ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg)); + assert(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg)); auto args = ctx.reg_alloc.GetArgumentInfo(inst); if (A32::IsDoubleExtReg(reg)) { diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp index 0fab7598fd..eb7cadebd7 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp +++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp @@ -194,8 +194,8 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, auto Xresult = ctx.reg_alloc.WriteX(inst); auto Xoperand = ctx.reg_alloc.ReadX(args[0]); RegAlloc::Realize(Xresult, Xoperand); - ASSERT(args[1].IsImmediate()); - ASSERT(args[1].GetImmediateU8() < 64); + assert(args[1].IsImmediate()); + assert(args[1].GetImmediateU8() < 64); code.UBFX(Xresult, Xoperand, args[1].GetImmediateU8(), 1); } @@ -893,9 +893,9 @@ static void EmitAddSub(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* if (overflow_inst) { // There is a limited set of circumstances where this is required, so assert for this. - ASSERT(!sub); - ASSERT(!nzcv_inst); - ASSERT(args[2].IsImmediate() && args[2].GetImmediateU1() == false); + assert(!sub); + assert(!nzcv_inst); + assert(args[2].IsImmediate() && args[2].GetImmediateU1() == false); auto Rb = ctx.reg_alloc.ReadReg(args[1]); auto Woverflow = ctx.reg_alloc.WriteW(overflow_inst); @@ -1134,7 +1134,7 @@ static void EmitBitOp(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* i if constexpr (!std::is_same_v) { const auto nz_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZFromOp); const auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp); - ASSERT(!(nz_inst && nzcv_inst)); + assert(!(nz_inst && nzcv_inst)); const auto flag_inst = nz_inst ? nz_inst : nzcv_inst; if (flag_inst) { @@ -1171,7 +1171,7 @@ template static void EmitAndNot(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { const auto nz_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZFromOp); const auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp); - ASSERT(!(nz_inst && nzcv_inst)); + assert(!(nz_inst && nzcv_inst)); const auto flag_inst = nz_inst ? nz_inst : nzcv_inst; auto args = ctx.reg_alloc.GetArgumentInfo(inst); @@ -1402,7 +1402,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitCo template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[2].IsImmediate()); + assert(args[2].IsImmediate()); auto Wresult = ctx.reg_alloc.WriteW(inst); auto Wop1 = ctx.reg_alloc.ReadW(args[0]); @@ -1416,7 +1416,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitCont template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[2].IsImmediate()); + assert(args[2].IsImmediate()); auto Xresult = ctx.reg_alloc.WriteX(inst); auto Xop1 = ctx.reg_alloc.ReadX(args[0]); @@ -1430,7 +1430,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitCont template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); auto Wresult = ctx.reg_alloc.WriteW(inst); auto Wvalue = ctx.reg_alloc.ReadW(args[0]); @@ -1444,7 +1444,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); auto Xresult = ctx.reg_alloc.WriteX(inst); auto Xvalue = ctx.reg_alloc.ReadX(args[0]); diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp index 0efb6ce787..3497a471d6 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp +++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp @@ -1,4 +1,4 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project +// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project // SPDX-License-Identifier: GPL-3.0-or-later /* This file is part of the dynarmic project. @@ -68,7 +68,7 @@ static void EmitConvert(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst RegAlloc::Realize(Vto, Vfrom); ctx.fpsr.Load(); - ASSERT(rounding_mode == ctx.FPCR().RMode()); + assert(rounding_mode == ctx.FPCR().RMode()); emit(Vto, Vfrom); } @@ -106,8 +106,8 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* } } } else { - ASSERT(fbits == 0); - ASSERT(bitsize_to != 16); + assert(fbits == 0); + assert(bitsize_to != 16); if constexpr (is_signed) { switch (rounding_mode) { case FP::RoundingMode::ToNearest_TieEven: @@ -449,7 +449,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx.fpsr.Load(); if (exact) { - ASSERT(ctx.FPCR().RMode() == rounding_mode); + assert(ctx.FPCR().RMode() == rounding_mode); code.FRINTX(Sresult, Soperand); } else { switch (rounding_mode) { @@ -486,7 +486,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx.fpsr.Load(); if (exact) { - ASSERT(ctx.FPCR().RMode() == rounding_mode); + assert(ctx.FPCR().RMode() == rounding_mode); code.FRINTX(Dresult, Doperand); } else { switch (rounding_mode) { diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_packed.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_packed.cpp index b9f13ac6f2..c3e4d01a29 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_packed.cpp +++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_packed.cpp @@ -1,3 +1,6 @@ +// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project +// SPDX-License-Identifier: GPL-3.0-or-later + /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -244,7 +247,7 @@ static void EmitPackedAddSub(oaknut::CodeGenerator& code, EmitContext& ctx, IR:: } if (ge_inst) { - ASSERT(!is_halving); + assert(!is_halving); auto Vge = ctx.reg_alloc.WriteD(ge_inst); RegAlloc::Realize(Vge); diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp index f9d1e5d619..1097fe9114 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp +++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp @@ -1,4 +1,4 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project +// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project // SPDX-License-Identifier: GPL-3.0-or-later /* This file is part of the dynarmic project. @@ -24,7 +24,7 @@ using namespace oaknut::util; template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp); - ASSERT(overflow_inst); + assert(overflow_inst); auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto Wresult = ctx.reg_alloc.WriteW(inst); @@ -44,7 +44,7 @@ void EmitIR(oaknut::CodeGenerator& cod template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp); - ASSERT(overflow_inst); + assert(overflow_inst); auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto Wresult = ctx.reg_alloc.WriteW(inst); @@ -67,7 +67,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitConte auto args = ctx.reg_alloc.GetArgumentInfo(inst); const size_t N = args[1].GetImmediateU8(); - ASSERT(N >= 1 && N <= 32); + assert(N >= 1 && N <= 32); if (N == 32) { ctx.reg_alloc.DefineAsExisting(inst, args[0]); @@ -113,7 +113,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitCon ctx.reg_alloc.SpillFlags(); const size_t N = args[1].GetImmediateU8(); - ASSERT(N <= 31); + assert(N <= 31); const u32 saturated_value = (1u << N) - 1; code.MOV(Wscratch0, saturated_value); diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp index c773d5a339..7fc982c0eb 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp +++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp @@ -275,7 +275,7 @@ static void EmitReduce(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst, template static void EmitGetElement(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst, EmitFn emit) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); auto Rresult = ctx.reg_alloc.WriteReg(32, size)>(inst); @@ -310,7 +310,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitCon template static void EmitSetElement(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst, EmitFn emit) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); auto Qvector = ctx.reg_alloc.ReadWriteQ(args[0], inst); @@ -650,7 +650,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext& auto Qa = ctx.reg_alloc.ReadQ(args[0]); auto Qb = ctx.reg_alloc.ReadQ(args[1]); const u8 position = args[2].GetImmediateU8(); - ASSERT(position % 8 == 0); + assert(position % 8 == 0); RegAlloc::Realize(Qresult, Qa, Qb); code.EXT(Qresult->B16(), Qa->B16(), Qb->B16(), position / 8); @@ -663,7 +663,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitCon auto Da = ctx.reg_alloc.ReadD(args[0]); auto Db = ctx.reg_alloc.ReadD(args[1]); const u8 position = args[2].GetImmediateU8(); - ASSERT(position % 8 == 0); + assert(position % 8 == 0); RegAlloc::Realize(Dresult, Da, Db); code.EXT(Dresult->B8(), Da->B8(), Db->B8(), position / 8); @@ -958,7 +958,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitConte template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { - ASSERT(ctx.conf.very_verbose_debugging_output && "VectorMultiply64 is for debugging only"); + assert(ctx.conf.very_verbose_debugging_output && "VectorMultiply64 is for debugging only"); EmitThreeOp(code, ctx, inst, [&](auto& Qresult, auto& Qa, auto& Qb) { code.FMOV(Xscratch0, Qa->toD()); code.FMOV(Xscratch1, Qb->toD()); @@ -1289,7 +1289,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitCont template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { EmitImmShift<8>(code, ctx, inst, [&](auto Vresult, auto Voperand, u8 shift_amount) { - ASSERT(shift_amount % 8 == 0); + assert(shift_amount % 8 == 0); const u8 ext_imm = (shift_amount % 128) / 8; code.EXT(Vresult, Voperand, Voperand, ext_imm); }); @@ -1602,12 +1602,12 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext& c template<> void EmitIR(oaknut::CodeGenerator&, EmitContext&, IR::Inst* inst) { // Do nothing. We *want* to hold on to the refcount for our arguments, so VectorTableLookup can use our arguments. - ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times"); + assert(inst->UseCount() == 1 && "Table cannot be used multiple times"); } template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { - ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable); + assert(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable); auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst()); @@ -1674,7 +1674,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitCo template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { - ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable); + assert(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable); auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst()); diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp index 557d6284ed..8c1156424c 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp +++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp @@ -139,7 +139,7 @@ static void EmitFromFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Ins const u8 fbits = args[1].GetImmediateU8(); const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); const bool fpcr_controlled = args[3].GetImmediateU1(); - ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); + assert(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); RegAlloc::Realize(Qto, Qfrom); MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { @@ -199,7 +199,7 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) } } } else { - ASSERT(fbits == 0); + assert(fbits == 0); if constexpr (is_signed) { switch (rounding_mode) { case FP::RoundingMode::ToNearest_TieEven: @@ -346,7 +346,7 @@ template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const auto rounding_mode = static_cast(args[1].GetImmediateU8()); - ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven); + assert(rounding_mode == FP::RoundingMode::ToNearest_TieEven); const bool fpcr_controlled = args[2].GetImmediateU1(); auto Qresult = ctx.reg_alloc.WriteQ(inst); @@ -617,7 +617,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitCon MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { if (exact) { - ASSERT(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode); + assert(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode); code.FRINTX(Qresult->S4(), Qoperand->S4()); } else { switch (rounding_mode) { @@ -657,7 +657,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitCon MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { if (exact) { - ASSERT(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode); + assert(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode); code.FRINTX(Qresult->D2(), Qoperand->D2()); } else { switch (rounding_mode) { @@ -743,7 +743,7 @@ template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const auto rounding_mode = static_cast(args[1].GetImmediateU8()); - ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven); + assert(rounding_mode == FP::RoundingMode::ToNearest_TieEven); const bool fpcr_controlled = args[2].GetImmediateU1(); auto Dresult = ctx.reg_alloc.WriteD(inst); diff --git a/src/dynarmic/src/dynarmic/backend/arm64/exclusive_monitor.cpp b/src/dynarmic/src/dynarmic/backend/arm64/exclusive_monitor.cpp index 7d2eddb091..83926239e1 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/exclusive_monitor.cpp +++ b/src/dynarmic/src/dynarmic/backend/arm64/exclusive_monitor.cpp @@ -10,7 +10,7 @@ #include -#include "common/assert.h" +#include namespace Dynarmic { diff --git a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp index b766e0746a..5693dec0c9 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp +++ b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp @@ -12,7 +12,7 @@ #include #include -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include #include "common/common_types.h" @@ -53,19 +53,19 @@ bool Argument::GetImmediateU1() const { u8 Argument::GetImmediateU8() const { const u64 imm = value.GetImmediateAsU64(); - ASSERT(imm < 0x100); + assert(imm < 0x100); return u8(imm); } u16 Argument::GetImmediateU16() const { const u64 imm = value.GetImmediateAsU64(); - ASSERT(imm < 0x10000); + assert(imm < 0x10000); return u16(imm); } u32 Argument::GetImmediateU32() const { const u64 imm = value.GetImmediateAsU64(); - ASSERT(imm < 0x100000000); + assert(imm < 0x100000000); return u32(imm); } @@ -74,12 +74,12 @@ u64 Argument::GetImmediateU64() const { } IR::Cond Argument::GetImmediateCond() const { - ASSERT(IsImmediate() && GetType() == IR::Type::Cond); + assert(IsImmediate() && GetType() == IR::Type::Cond); return value.GetCond(); } IR::AccType Argument::GetImmediateAccType() const { - ASSERT(IsImmediate() && GetType() == IR::Type::AccType); + assert(IsImmediate() && GetType() == IR::Type::AccType); return value.GetAccType(); } @@ -92,12 +92,12 @@ bool HostLocInfo::Contains(const IR::Inst* value) const { } void HostLocInfo::SetupScratchLocation() { - ASSERT(IsCompletelyEmpty()); + assert(IsCompletelyEmpty()); realized = true; } void HostLocInfo::SetupLocation(const IR::Inst* value) { - ASSERT(IsCompletelyEmpty()); + assert(IsCompletelyEmpty()); values.clear(); values.push_back(value); realized = true; @@ -135,7 +135,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) { const IR::Value arg = inst->GetArg(i); ret[i].value = arg; if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) { - ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined"); + assert(ValueLocation(arg.GetInst()) && "argument must already been defined"); ValueInfo(arg.GetInst()).uses_this_inst++; } } @@ -174,11 +174,11 @@ void RegAlloc::PrepareForCall(std::optional arg0, for (int i = 0; i < 4; i++) { if (args[i]) { if (args[i]->get().GetType() == IR::Type::U128) { - ASSERT(fprs[nsrn].IsCompletelyEmpty()); + assert(fprs[nsrn].IsCompletelyEmpty()); LoadCopyInto(args[i]->get().value, oaknut::QReg{nsrn}); nsrn++; } else { - ASSERT(gprs[ngrn].IsCompletelyEmpty()); + assert(gprs[ngrn].IsCompletelyEmpty()); LoadCopyInto(args[i]->get().value, oaknut::XReg{ngrn}); ngrn++; } @@ -192,7 +192,7 @@ void RegAlloc::PrepareForCall(std::optional arg0, void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) { defined_insts.insert(inst); - ASSERT(!ValueLocation(inst)); + assert(!ValueLocation(inst)); if (arg.value.IsImmediate()) { inst->ReplaceUsesWith(arg.value); @@ -206,9 +206,9 @@ void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) { void RegAlloc::DefineAsRegister(IR::Inst* inst, oaknut::Reg reg) { defined_insts.insert(inst); - ASSERT(!ValueLocation(inst)); + assert(!ValueLocation(inst)); auto& info = reg.is_vector() ? fprs[reg.index()] : gprs[reg.index()]; - ASSERT(info.IsCompletelyEmpty()); + assert(info.IsCompletelyEmpty()); info.values.push_back(inst); info.expected_uses += inst->UseCount(); } @@ -228,18 +228,18 @@ void RegAlloc::UpdateAllUses() { void RegAlloc::AssertAllUnlocked() const { const auto is_unlocked = [](const auto& i) { return !i.locked && !i.realized; }; - ASSERT(std::all_of(gprs.begin(), gprs.end(), is_unlocked)); - ASSERT(std::all_of(fprs.begin(), fprs.end(), is_unlocked)); - ASSERT(is_unlocked(flags)); - ASSERT(std::all_of(spills.begin(), spills.end(), is_unlocked)); + assert(std::all_of(gprs.begin(), gprs.end(), is_unlocked)); + assert(std::all_of(fprs.begin(), fprs.end(), is_unlocked)); + assert(is_unlocked(flags)); + assert(std::all_of(spills.begin(), spills.end(), is_unlocked)); } void RegAlloc::AssertNoMoreUses() const { const auto is_empty = [](const auto& i) { return i.IsCompletelyEmpty(); }; - ASSERT(std::all_of(gprs.begin(), gprs.end(), is_empty)); - ASSERT(std::all_of(fprs.begin(), fprs.end(), is_empty)); - ASSERT(is_empty(flags)); - ASSERT(std::all_of(spills.begin(), spills.end(), is_empty)); + assert(std::all_of(gprs.begin(), gprs.end(), is_empty)); + assert(std::all_of(fprs.begin(), fprs.end(), is_empty)); + assert(is_empty(flags)); + assert(std::all_of(spills.begin(), spills.end(), is_empty)); } void RegAlloc::EmitVerboseDebuggingOutput() { @@ -271,7 +271,7 @@ void RegAlloc::EmitVerboseDebuggingOutput() { template int RegAlloc::GenerateImmediate(const IR::Value& value) { - ASSERT(value.GetType() != IR::Type::U1); + assert(value.GetType() != IR::Type::U1); if constexpr (kind == HostLoc::Kind::Gpr) { const int new_location_index = AllocateRegister(gprs, gpr_order); SpillGpr(new_location_index); @@ -309,15 +309,15 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) { } const auto current_location = ValueLocation(value.GetInst()); - ASSERT(current_location); + assert(current_location); if (current_location->kind == required_kind) { ValueInfo(*current_location).realized = true; return current_location->index; } - ASSERT(!ValueInfo(*current_location).realized); - ASSERT(ValueInfo(*current_location).locked); + assert(!ValueInfo(*current_location).realized); + assert(ValueInfo(*current_location).locked); if constexpr (required_kind == HostLoc::Kind::Gpr) { const int new_location_index = AllocateRegister(gprs, gpr_order); @@ -328,7 +328,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) { UNREACHABLE(); //logic error case HostLoc::Kind::Fpr: code.FMOV(oaknut::XReg{new_location_index}, oaknut::DReg{current_location->index}); - // ASSERT size fits + // assert size fits break; case HostLoc::Kind::Spill: code.LDR(oaknut::XReg{new_location_index}, SP, spill_offset + current_location->index * spill_slot_size); @@ -355,7 +355,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) { code.LDR(oaknut::QReg{new_location_index}, SP, spill_offset + current_location->index * spill_slot_size); break; case HostLoc::Kind::Flags: - ASSERT(false && "Moving from flags into fprs is not currently supported"); + assert(false && "Moving from flags into fprs is not currently supported"); break; } @@ -372,7 +372,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) { template int RegAlloc::RealizeWriteImpl(const IR::Inst* value) { defined_insts.insert(value); - ASSERT(!ValueLocation(value)); + assert(!ValueLocation(value)); if constexpr (kind == HostLoc::Kind::Gpr) { const int new_location_index = AllocateRegister(gprs, gpr_order); @@ -407,7 +407,7 @@ int RegAlloc::RealizeReadWriteImpl(const IR::Value& read_value, const IR::Inst* LoadCopyInto(read_value, oaknut::QReg{write_loc}); return write_loc; } else if constexpr (kind == HostLoc::Kind::Flags) { - ASSERT(false && "Incorrect function for ReadWrite of flags"); + assert(false && "Incorrect function for ReadWrite of flags"); } else { UNREACHABLE(); } @@ -439,7 +439,7 @@ int RegAlloc::AllocateRegister(const std::array& regs, const st } void RegAlloc::SpillGpr(int index) { - ASSERT(!gprs[index].locked && !gprs[index].realized); + assert(!gprs[index].locked && !gprs[index].realized); if (gprs[index].values.empty()) { return; } @@ -449,7 +449,7 @@ void RegAlloc::SpillGpr(int index) { } void RegAlloc::SpillFpr(int index) { - ASSERT(!fprs[index].locked && !fprs[index].realized); + assert(!fprs[index].locked && !fprs[index].realized); if (fprs[index].values.empty()) { return; } @@ -461,7 +461,7 @@ void RegAlloc::SpillFpr(int index) { void RegAlloc::ReadWriteFlags(Argument& read, IR::Inst* write) { defined_insts.insert(write); const auto current_location = ValueLocation(read.value.GetInst()); - ASSERT(current_location); + assert(current_location); if (current_location->kind == HostLoc::Kind::Flags) { if (!flags.IsOneRemainingUse()) { @@ -479,7 +479,7 @@ void RegAlloc::ReadWriteFlags(Argument& read, IR::Inst* write) { code.LDR(Wscratch0, SP, spill_offset + current_location->index * spill_slot_size); code.MSR(oaknut::SystemReg::NZCV, Xscratch0); } else { - UNREACHABLE(); //ASSERT(false && "Invalid current location for flags"); + UNREACHABLE(); //assert(false && "Invalid current location for flags"); } if (write) { @@ -489,7 +489,7 @@ void RegAlloc::ReadWriteFlags(Argument& read, IR::Inst* write) { } void RegAlloc::SpillFlags() { - ASSERT(!flags.locked && !flags.realized); + assert(!flags.locked && !flags.realized); if (flags.values.empty()) { return; } @@ -501,7 +501,7 @@ void RegAlloc::SpillFlags() { int RegAlloc::FindFreeSpill() const { const auto iter = std::find_if(spills.begin(), spills.end(), [](const HostLocInfo& info) { return info.values.empty(); }); - ASSERT(iter != spills.end() && "All spill locations are full"); + assert(iter != spills.end() && "All spill locations are full"); return static_cast(iter - spills.begin()); } @@ -512,14 +512,14 @@ void RegAlloc::LoadCopyInto(const IR::Value& value, oaknut::XReg reg) { } const auto current_location = ValueLocation(value.GetInst()); - ASSERT(current_location); + assert(current_location); switch (current_location->kind) { case HostLoc::Kind::Gpr: code.MOV(reg, oaknut::XReg{current_location->index}); break; case HostLoc::Kind::Fpr: code.FMOV(reg, oaknut::DReg{current_location->index}); - // ASSERT size fits + // assert size fits break; case HostLoc::Kind::Spill: code.LDR(reg, SP, spill_offset + current_location->index * spill_slot_size); @@ -538,7 +538,7 @@ void RegAlloc::LoadCopyInto(const IR::Value& value, oaknut::QReg reg) { } const auto current_location = ValueLocation(value.GetInst()); - ASSERT(current_location); + assert(current_location); switch (current_location->kind) { case HostLoc::Kind::Gpr: code.FMOV(reg.toD(), oaknut::XReg{current_location->index}); @@ -551,7 +551,7 @@ void RegAlloc::LoadCopyInto(const IR::Value& value, oaknut::QReg reg) { code.LDR(reg, SP, spill_offset + current_location->index * spill_slot_size); break; case HostLoc::Kind::Flags: - UNREACHABLE(); //ASSERT(false && "Moving from flags into fprs is not currently supported"); + UNREACHABLE(); //assert(false && "Moving from flags into fprs is not currently supported"); } } diff --git a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h index e23c8670fb..bd63687f40 100644 --- a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h +++ b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h @@ -14,7 +14,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/mcl/is_instance_of_template.hpp" #include diff --git a/src/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp b/src/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp index fc627f60b2..edd7075846 100644 --- a/src/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp +++ b/src/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp @@ -19,7 +19,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/backend/exception_handler.h" @@ -87,7 +87,7 @@ private: }; MachHandler::MachHandler() { -#define KCHECK(x) ASSERT((x) == KERN_SUCCESS && "init failure at " #x) +#define KCHECK(x) assert((x) == KERN_SUCCESS && "init failure at " #x) KCHECK(mach_port_allocate(mach_task_self(), MACH_PORT_RIGHT_RECEIVE, &server_port)); KCHECK(mach_port_insert_right(mach_task_self(), server_port, server_port, MACH_MSG_TYPE_MAKE_SEND)); KCHECK(task_set_exception_ports(mach_task_self(), EXC_MASK_BAD_ACCESS, server_port, EXCEPTION_STATE | MACH_EXCEPTION_CODES, THREAD_STATE)); diff --git a/src/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp b/src/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp index 50d552aa0e..b563f33b86 100644 --- a/src/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp +++ b/src/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp @@ -17,7 +17,7 @@ #include #include #include "dynarmic/backend/exception_handler.h" -#include "common/assert.h" +#include #include "dynarmic/common/context.h" #include "common/common_types.h" #if defined(ARCHITECTURE_x86_64) @@ -116,7 +116,7 @@ void RegisterHandler() { } void SigHandler::SigAction(int sig, siginfo_t* info, void* raw_context) { - DEBUG_ASSERT(sig == SIGSEGV || sig == SIGBUS); + assert(sig == SIGSEGV || sig == SIGBUS); CTX_DECLARE(raw_context); #if defined(ARCHITECTURE_x86_64) { diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp index 490398931c..cf270d2f74 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp @@ -8,7 +8,7 @@ #include "dynarmic/backend/riscv64/a32_address_space.h" -#include "common/assert.h" +#include #include "dynarmic/backend/riscv64/abi.h" #include "dynarmic/backend/riscv64/emit_riscv64.h" @@ -94,7 +94,7 @@ void A32AddressSpace::EmitPrelude() { void A32AddressSpace::SetCursorPtr(CodePtr ptr) { ptrdiff_t offset = ptr - GetMemPtr(); - ASSERT(offset >= 0); + assert(offset >= 0); as.RewindBuffer(offset); } diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp index 6e30e0dbec..43cf5e2e84 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp @@ -10,7 +10,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/backend/riscv64/a32_address_space.h" @@ -31,7 +31,7 @@ struct Jit::Impl final { , core(conf) {} HaltReason Run() { - ASSERT(!jit_interface->is_executing); + assert(!jit_interface->is_executing); jit_interface->is_executing = true; HaltReason hr = core.Run(current_address_space, current_state, &halt_reason); RequestCacheInvalidation(); @@ -40,9 +40,9 @@ struct Jit::Impl final { } HaltReason Step() { - ASSERT(!jit_interface->is_executing); + assert(!jit_interface->is_executing); jit_interface->is_executing = true; - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented RequestCacheInvalidation(); jit_interface->is_executing = false; return HaltReason{}; diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/a64_interface.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/a64_interface.cpp index 67c4986109..464b052d15 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/a64_interface.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/a64_interface.cpp @@ -5,7 +5,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/frontend/A64/a64_location_descriptor.h" @@ -28,12 +28,12 @@ struct Jit::Impl final { , jit_interface(jit_interface) {} HaltReason Run() { - ASSERT(false); + assert(false); return HaltReason{}; } HaltReason Step() { - ASSERT(false); + assert(false); return HaltReason{}; } @@ -51,7 +51,7 @@ struct Jit::Impl final { } void Reset() { - ASSERT(!is_executing); + assert(!is_executing); //jit_state = {}; } diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/code_block.h b/src/dynarmic/src/dynarmic/backend/riscv64/code_block.h index 4917399f10..163063f187 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/code_block.h +++ b/src/dynarmic/src/dynarmic/backend/riscv64/code_block.h @@ -13,7 +13,7 @@ #include -#include "common/assert.h" +#include #include "common/common_types.h" namespace Dynarmic::Backend::RV64 { @@ -22,7 +22,7 @@ class CodeBlock { public: explicit CodeBlock(std::size_t size) noexcept : memsize(size) { mem = (u8*)mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, -1, 0); - ASSERT(mem != nullptr); + assert(mem != nullptr); } ~CodeBlock() noexcept { diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp index 795ec4ca21..c08e783d23 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp @@ -35,39 +35,39 @@ void EmitIR(biscuit::Assembler&, EmitContext& ctx, IR::Ins template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext& ctx, IR::Inst* inst) { [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(ctx.reg_alloc.IsValueLive(inst)); + assert(ctx.reg_alloc.IsValueLive(inst)); } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext& ctx, IR::Inst* inst) { [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(ctx.reg_alloc.IsValueLive(inst)); + assert(ctx.reg_alloc.IsValueLive(inst)); } template<> @@ -87,12 +87,12 @@ void EmitIR(biscuit::Assembler& as, EmitContext& ctx, I template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> @@ -109,7 +109,7 @@ void EmitIR(biscuit::Assembler& as, EmitContext& c template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } EmittedBlockInfo EmitRV64(biscuit::Assembler& as, IR::Block block, const EmitConfig& emit_conf) { diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp index 8218ca3489..418b97a335 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp @@ -205,7 +205,7 @@ void EmitA32Terminal(biscuit::Assembler& as, EmitContext& ctx) { template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> @@ -220,17 +220,17 @@ void EmitIR(biscuit::Assembler& as, EmitContext& ctx template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> @@ -249,27 +249,27 @@ void EmitIR(biscuit::Assembler& as, EmitContext& ctx template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> @@ -284,17 +284,17 @@ void EmitIR(biscuit::Assembler& as, EmitContext& ctx template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> @@ -302,7 +302,7 @@ void EmitIR(biscuit::Assembler& as, EmitContext& ctx, auto args = ctx.reg_alloc.GetArgumentInfo(inst); // TODO: Add full implementation - ASSERT(!args[0].IsImmediate() && !args[1].IsImmediate()); + assert(!args[0].IsImmediate() && !args[1].IsImmediate()); auto Xnz = ctx.reg_alloc.ReadX(args[0]); auto Xc = ctx.reg_alloc.ReadX(args[1]); @@ -318,82 +318,82 @@ void EmitIR(biscuit::Assembler& as, EmitContext& ctx, template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } // namespace Dynarmic::Backend::RV64 diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_coprocessor.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_coprocessor.cpp index b6a41f71b2..bd5ff215e6 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_coprocessor.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_coprocessor.cpp @@ -22,37 +22,37 @@ namespace Dynarmic::Backend::RV64 { template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } // namespace Dynarmic::Backend::RV64 diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_memory.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_memory.cpp index fa96d52e6e..cdcd46231c 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_memory.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_memory.cpp @@ -22,87 +22,87 @@ namespace Dynarmic::Backend::RV64 { template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } // namespace Dynarmic::Backend::RV64 diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64.cpp index eed51547c6..18f60833a2 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64.cpp @@ -22,182 +22,182 @@ namespace Dynarmic::Backend::RV64 { template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } // namespace Dynarmic::Backend::RV64 diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64_memory.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64_memory.cpp index 84802837c5..3d09e8ab62 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64_memory.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64_memory.cpp @@ -22,107 +22,107 @@ namespace Dynarmic::Backend::RV64 { template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } // namespace Dynarmic::Backend::RV64 diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_cryptography.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_cryptography.cpp index 44ebc2e3fc..e7aa5fe8e4 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_cryptography.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_cryptography.cpp @@ -22,82 +22,82 @@ namespace Dynarmic::Backend::RV64 { template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } // namespace Dynarmic::Backend::RV64 diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_data_processing.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_data_processing.cpp index d41433b12b..e92d5e78d8 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_data_processing.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_data_processing.cpp @@ -22,67 +22,67 @@ namespace Dynarmic::Backend::RV64 { template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> @@ -95,8 +95,8 @@ void EmitIR(biscuit::Assembler& as, EmitContext& auto& carry_arg = args[2]; // TODO: Add full implementation - ASSERT(carry_inst != nullptr); - ASSERT(shift_arg.IsImmediate()); + assert(carry_inst != nullptr); + assert(shift_arg.IsImmediate()); auto Xresult = ctx.reg_alloc.WriteX(inst); auto Xcarry_out = ctx.reg_alloc.WriteX(carry_inst); @@ -124,7 +124,7 @@ void EmitIR(biscuit::Assembler& as, EmitContext& template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> @@ -136,8 +136,8 @@ void EmitIR(biscuit::Assembler& as, EmitContext auto& shift_arg = args[1]; // TODO: Add full implementation - ASSERT(carry_inst == nullptr); - ASSERT(shift_arg.IsImmediate()); + assert(carry_inst == nullptr); + assert(shift_arg.IsImmediate()); const u8 shift = shift_arg.GetImmediateU8(); auto Xresult = ctx.reg_alloc.WriteX(inst); @@ -153,72 +153,72 @@ void EmitIR(biscuit::Assembler& as, EmitContext template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template @@ -264,7 +264,7 @@ static void AddImmWithFlags(biscuit::Assembler& as, biscuit::GPR rd, biscuit::GP as.SLLI(Xscratch1, Xscratch1, 28); as.OR(flags, flags, Xscratch1); } else { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } @@ -279,7 +279,7 @@ static void EmitAddSub(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst) auto Xa = ctx.reg_alloc.ReadX(args[0]); if (overflow_inst) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } else if (nzcv_inst) { if (args[1].IsImmediate()) { const u64 imm = args[1].GetImmediateU64(); @@ -294,17 +294,17 @@ static void EmitAddSub(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst) AddImmWithFlags(as, *Xresult, *Xa, sub ? -imm : imm, *Xflags); } } else { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } else { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } else { if (args[1].IsImmediate()) { const u64 imm = args[1].GetImmediateU64(); if (args[2].IsImmediate()) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } else { auto Xnzcv = ctx.reg_alloc.ReadX(args[2]); RegAlloc::Realize(Xresult, Xa, Xnzcv); @@ -317,7 +317,7 @@ static void EmitAddSub(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst) as.ADDW(Xresult, Xa, Xscratch0); } } else { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } } @@ -329,7 +329,7 @@ void EmitIR(biscuit::Assembler& as, EmitContext& ctx, IR::Ins template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> @@ -339,237 +339,237 @@ void EmitIR(biscuit::Assembler& as, EmitContext& ctx, IR::Ins template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } // namespace Dynarmic::Backend::RV64 diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_floating_point.cpp index 0c5d5984bc..2c16b7052c 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_floating_point.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_floating_point.cpp @@ -22,442 +22,442 @@ namespace Dynarmic::Backend::RV64 { template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } // namespace Dynarmic::Backend::RV64 diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_packed.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_packed.cpp index acd73e86a3..6c7a575907 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_packed.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_packed.cpp @@ -22,172 +22,172 @@ namespace Dynarmic::Backend::RV64 { template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } // namespace Dynarmic::Backend::RV64 diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_saturation.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_saturation.cpp index 9fae6cda77..fc8fd5103c 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_saturation.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_saturation.cpp @@ -22,112 +22,112 @@ namespace Dynarmic::Backend::RV64 { template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } // namespace Dynarmic::Backend::RV64 diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector.cpp index 5e56a34f19..5c8d79b5a4 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector.cpp @@ -22,1377 +22,1377 @@ namespace Dynarmic::Backend::RV64 { template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } // namespace Dynarmic::Backend::RV64 diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_floating_point.cpp index 661cfc5403..ff2731050a 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_floating_point.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_floating_point.cpp @@ -22,337 +22,337 @@ namespace Dynarmic::Backend::RV64 { template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } // namespace Dynarmic::Backend::RV64 diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_saturation.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_saturation.cpp index 6662afcd69..28330ddca5 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_saturation.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_saturation.cpp @@ -22,82 +22,82 @@ namespace Dynarmic::Backend::RV64 { template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } template<> void EmitIR(biscuit::Assembler&, EmitContext&, IR::Inst*) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } } // namespace Dynarmic::Backend::RV64 diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp b/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp index fdb8ff898f..247241d047 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp +++ b/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp @@ -11,7 +11,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/common/always_false.h" @@ -44,19 +44,19 @@ bool Argument::GetImmediateU1() const { u8 Argument::GetImmediateU8() const { const u64 imm = value.GetImmediateAsU64(); - ASSERT(imm < 0x100); + assert(imm < 0x100); return u8(imm); } u16 Argument::GetImmediateU16() const { const u64 imm = value.GetImmediateAsU64(); - ASSERT(imm < 0x10000); + assert(imm < 0x10000); return u16(imm); } u32 Argument::GetImmediateU32() const { const u64 imm = value.GetImmediateAsU64(); - ASSERT(imm < 0x100000000); + assert(imm < 0x100000000); return u32(imm); } @@ -65,12 +65,12 @@ u64 Argument::GetImmediateU64() const { } IR::Cond Argument::GetImmediateCond() const { - ASSERT(IsImmediate() && GetType() == IR::Type::Cond); + assert(IsImmediate() && GetType() == IR::Type::Cond); return value.GetCond(); } IR::AccType Argument::GetImmediateAccType() const { - ASSERT(IsImmediate() && GetType() == IR::Type::AccType); + assert(IsImmediate() && GetType() == IR::Type::AccType); return value.GetAccType(); } @@ -79,7 +79,7 @@ bool HostLocInfo::Contains(const IR::Inst* value) const { } void HostLocInfo::SetupScratchLocation() { - ASSERT(IsCompletelyEmpty()); + assert(IsCompletelyEmpty()); realized = true; } @@ -104,7 +104,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) { const IR::Value arg = inst->GetArg(i); ret[i].value = arg; if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) { - ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined"); + assert(ValueLocation(arg.GetInst()) && "argument must already been defined"); ValueInfo(arg.GetInst()).uses_this_inst++; } } @@ -128,7 +128,7 @@ void RegAlloc::UpdateAllUses() { } void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) { - ASSERT(!ValueLocation(inst)); + assert(!ValueLocation(inst)); if (arg.value.IsImmediate()) { inst->ReplaceUsesWith(arg.value); @@ -142,15 +142,15 @@ void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) { void RegAlloc::AssertNoMoreUses() const { const auto is_empty = [](const auto& i) { return i.IsCompletelyEmpty(); }; - ASSERT(std::all_of(gprs.begin(), gprs.end(), is_empty)); - ASSERT(std::all_of(fprs.begin(), fprs.end(), is_empty)); - ASSERT(std::all_of(spills.begin(), spills.end(), is_empty)); + assert(std::all_of(gprs.begin(), gprs.end(), is_empty)); + assert(std::all_of(fprs.begin(), fprs.end(), is_empty)); + assert(std::all_of(spills.begin(), spills.end(), is_empty)); } template u32 RegAlloc::GenerateImmediate(const IR::Value& value) { // TODO - // ASSERT(value.GetType() != IR::Type::U1); + // assert(value.GetType() != IR::Type::U1); if constexpr (kind == HostLoc::Kind::Gpr) { const u32 new_location_index = AllocateRegister(gprs, gpr_order); @@ -161,7 +161,7 @@ u32 RegAlloc::GenerateImmediate(const IR::Value& value) { return new_location_index; } else if constexpr (kind == HostLoc::Kind::Fpr) { - ASSERT(false && "Unimplemented instruction"); + std::terminate(); //unimplemented } else { UNREACHABLE(); } @@ -175,15 +175,15 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) { } const auto current_location = ValueLocation(value.GetInst()); - ASSERT(current_location); + assert(current_location); if (current_location->kind == required_kind) { ValueInfo(*current_location).realized = true; return current_location->index; } - ASSERT(!ValueInfo(*current_location).realized); - ASSERT(!ValueInfo(*current_location).locked); + assert(!ValueInfo(*current_location).realized); + assert(!ValueInfo(*current_location).locked); if constexpr (required_kind == HostLoc::Kind::Gpr) { const u32 new_location_index = AllocateRegister(gprs, gpr_order); @@ -194,7 +194,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) { UNREACHABLE(); //logic error case HostLoc::Kind::Fpr: as.FMV_X_D(biscuit::GPR(new_location_index), biscuit::FPR{current_location->index}); - // ASSERT size fits + // assert size fits break; case HostLoc::Kind::Spill: as.LD(biscuit::GPR{new_location_index}, spill_offset + current_location->index * spill_slot_size, biscuit::sp); @@ -229,7 +229,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) { template u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value) { - ASSERT(!ValueLocation(value)); + assert(!ValueLocation(value)); const auto setup_location = [&](HostLocInfo& info) { info = {}; @@ -274,7 +274,7 @@ u32 RegAlloc::AllocateRegister(const std::array& regs, const st } void RegAlloc::SpillGpr(u32 index) { - ASSERT(!gprs[index].locked && !gprs[index].realized); + assert(!gprs[index].locked && !gprs[index].realized); if (gprs[index].values.empty()) { return; } @@ -284,7 +284,7 @@ void RegAlloc::SpillGpr(u32 index) { } void RegAlloc::SpillFpr(u32 index) { - ASSERT(!fprs[index].locked && !fprs[index].realized); + assert(!fprs[index].locked && !fprs[index].realized); if (fprs[index].values.empty()) { return; } @@ -295,7 +295,7 @@ void RegAlloc::SpillFpr(u32 index) { u32 RegAlloc::FindFreeSpill() const { const auto iter = std::find_if(spills.begin(), spills.end(), [](const HostLocInfo& info) { return info.values.empty(); }); - ASSERT(iter != spills.end() && "All spill locations are full"); + assert(iter != spills.end() && "All spill locations are full"); return static_cast(iter - spills.begin()); } diff --git a/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.h b/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.h index 5a0bd660de..7a5feef5ca 100644 --- a/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.h +++ b/src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.h @@ -16,7 +16,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/mcl/is_instance_of_template.hpp" #include diff --git a/src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp b/src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp index f7a4e426c8..6ba74d0c92 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp @@ -14,7 +14,7 @@ #include #include -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "common/common_types.h" #include @@ -183,11 +183,11 @@ void A32EmitX64::InvalidateCacheRanges(const boost::icl::interval_set& rang void A32EmitX64::EmitCondPrelude(const A32EmitContext& ctx) { if (ctx.block.GetCondition() == IR::Cond::AL) { - ASSERT(!ctx.block.HasConditionFailedLocation()); + assert(!ctx.block.HasConditionFailedLocation()); return; } - ASSERT(ctx.block.HasConditionFailedLocation()); + assert(ctx.block.HasConditionFailedLocation()); Xbyak::Label pass = EmitCond(ctx.block.GetCondition()); if (conf.enable_cycle_counting) { @@ -285,7 +285,7 @@ void A32EmitX64::EmitA32GetRegister(A32EmitContext& ctx, IR::Inst* inst) { void A32EmitX64::EmitA32GetExtendedRegister32(A32EmitContext& ctx, IR::Inst* inst) { const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef(); - ASSERT(A32::IsSingleExtReg(reg)); + assert(A32::IsSingleExtReg(reg)); const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code); code.movss(result, MJitStateExtReg(reg)); @@ -294,7 +294,7 @@ void A32EmitX64::EmitA32GetExtendedRegister32(A32EmitContext& ctx, IR::Inst* ins void A32EmitX64::EmitA32GetExtendedRegister64(A32EmitContext& ctx, IR::Inst* inst) { const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef(); - ASSERT(A32::IsDoubleExtReg(reg)); + assert(A32::IsDoubleExtReg(reg)); const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code); code.movsd(result, MJitStateExtReg(reg)); @@ -303,7 +303,7 @@ void A32EmitX64::EmitA32GetExtendedRegister64(A32EmitContext& ctx, IR::Inst* ins void A32EmitX64::EmitA32GetVector(A32EmitContext& ctx, IR::Inst* inst) { const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef(); - ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg)); + assert(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg)); const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code); if (A32::IsDoubleExtReg(reg)) { @@ -332,7 +332,7 @@ void A32EmitX64::EmitA32SetRegister(A32EmitContext& ctx, IR::Inst* inst) { void A32EmitX64::EmitA32SetExtendedRegister32(A32EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef(); - ASSERT(A32::IsSingleExtReg(reg)); + assert(A32::IsSingleExtReg(reg)); if (args[1].IsInXmm(ctx.reg_alloc)) { Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[1]); @@ -346,7 +346,7 @@ void A32EmitX64::EmitA32SetExtendedRegister32(A32EmitContext& ctx, IR::Inst* ins void A32EmitX64::EmitA32SetExtendedRegister64(A32EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef(); - ASSERT(A32::IsDoubleExtReg(reg)); + assert(A32::IsDoubleExtReg(reg)); if (args[1].IsInXmm(ctx.reg_alloc)) { const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[1]); @@ -360,7 +360,7 @@ void A32EmitX64::EmitA32SetExtendedRegister64(A32EmitContext& ctx, IR::Inst* ins void A32EmitX64::EmitA32SetVector(A32EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef(); - ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg)); + assert(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg)); const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[1]); if (A32::IsDoubleExtReg(reg)) { @@ -621,7 +621,7 @@ void A32EmitX64::EmitA32GetGEFlags(A32EmitContext& ctx, IR::Inst* inst) { void A32EmitX64::EmitA32SetGEFlags(A32EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(!args[0].IsImmediate()); + assert(!args[0].IsImmediate()); if (args[0].IsInXmm(ctx.reg_alloc)) { const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[0]); @@ -762,7 +762,7 @@ void A32EmitX64::EmitA32ExceptionRaised(A32EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.EndOfAllocScope(); auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[0].IsImmediate() && args[1].IsImmediate()); + assert(args[0].IsImmediate() && args[1].IsImmediate()); const u32 pc = args[0].GetImmediateU32(); const u64 exception = args[1].GetImmediateU64(); Devirtualize<&A32::UserCallbacks::ExceptionRaised>(conf.callbacks).EmitCall(code, [&](RegList param) { diff --git a/src/dynarmic/src/dynarmic/backend/x64/a32_interface.cpp b/src/dynarmic/src/dynarmic/backend/x64/a32_interface.cpp index 097e0f426f..549eabac99 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/a32_interface.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/a32_interface.cpp @@ -12,7 +12,7 @@ #include #include -#include "common/assert.h" +#include #include #include "common/common_types.h" #include "dynarmic/common/llvm_disassemble.h" @@ -74,7 +74,7 @@ struct Jit::Impl { ~Impl() = default; HaltReason Run() { - ASSERT(!jit_interface->is_executing); + assert(!jit_interface->is_executing); PerformRequestedCacheInvalidation(static_cast(Atomic::Load(&jit_state.halt_reason))); jit_interface->is_executing = true; const CodePtr current_codeptr = [this] { @@ -94,7 +94,7 @@ struct Jit::Impl { } HaltReason Step() { - ASSERT(!jit_interface->is_executing); + assert(!jit_interface->is_executing); PerformRequestedCacheInvalidation(static_cast(Atomic::Load(&jit_state.halt_reason))); jit_interface->is_executing = true; const HaltReason hr = block_of_code.StepCode(&jit_state, GetCurrentSingleStep()); @@ -116,7 +116,7 @@ struct Jit::Impl { } void Reset() { - ASSERT(!jit_interface->is_executing); + assert(!jit_interface->is_executing); jit_state = {}; } diff --git a/src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp b/src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp index df1d789895..028509e7c0 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp @@ -8,7 +8,7 @@ #include "dynarmic/backend/x64/a32_jitstate.h" -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "common/common_types.h" @@ -51,8 +51,8 @@ namespace Dynarmic::Backend::X64 { */ u32 A32JitState::Cpsr() const { - DEBUG_ASSERT((cpsr_q & ~1) == 0); - DEBUG_ASSERT((cpsr_jaifm & ~0x010001DF) == 0); + assert((cpsr_q & ~1) == 0); + assert((cpsr_jaifm & ~0x010001DF) == 0); u32 cpsr = 0; @@ -167,7 +167,7 @@ constexpr u32 FPSCR_MODE_MASK = A32::LocationDescriptor::FPSCR_MODE_MASK; constexpr u32 FPSCR_NZCV_MASK = 0xF0000000; u32 A32JitState::Fpscr() const { - DEBUG_ASSERT((fpsr_nzcv & ~FPSCR_NZCV_MASK) == 0); + assert((fpsr_nzcv & ~FPSCR_NZCV_MASK) == 0); const u32 fpcr_mode = static_cast(upper_location_descriptor) & FPSCR_MODE_MASK; const u32 mxcsr = guest_MXCSR | asimd_MXCSR; diff --git a/src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp b/src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp index 1c58cc64d5..2d52a0a881 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp @@ -10,7 +10,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/mcl/integer_of_size.hpp" #include @@ -89,7 +89,7 @@ A64EmitX64::BlockDescriptor A64EmitX64::Emit(IR::Block& block) noexcept { code.align(); const auto* const entrypoint = code.getCurr(); - DEBUG_ASSERT(block.GetCondition() == IR::Cond::AL); + assert(block.GetCondition() == IR::Cond::AL); typedef void (EmitX64::*EmitHandlerFn)(EmitContext& context, IR::Inst* inst); constexpr EmitHandlerFn opcode_handlers[] = { #define OPCODE(name, type, ...) &EmitX64::Emit##name, @@ -497,7 +497,7 @@ void A64EmitX64::EmitA64SetPC(A64EmitContext& ctx, IR::Inst* inst) { void A64EmitX64::EmitA64CallSupervisor(A64EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.HostCall(code, nullptr); auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[0].IsImmediate()); + assert(args[0].IsImmediate()); const u32 imm = args[0].GetImmediateU32(); Devirtualize<&A64::UserCallbacks::CallSVC>(conf.callbacks).EmitCall(code, [&](RegList param) { code.mov(param[0], imm); @@ -509,7 +509,7 @@ void A64EmitX64::EmitA64CallSupervisor(A64EmitContext& ctx, IR::Inst* inst) { void A64EmitX64::EmitA64ExceptionRaised(A64EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.HostCall(code, nullptr); auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[0].IsImmediate() && args[1].IsImmediate()); + assert(args[0].IsImmediate() && args[1].IsImmediate()); const u64 pc = args[0].GetImmediateU64(); const u64 exception = args[1].GetImmediateU64(); Devirtualize<&A64::UserCallbacks::ExceptionRaised>(conf.callbacks).EmitCall(code, [&](RegList param) { diff --git a/src/dynarmic/src/dynarmic/backend/x64/a64_interface.cpp b/src/dynarmic/src/dynarmic/backend/x64/a64_interface.cpp index 9acaf3f9f6..df997b74fc 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/a64_interface.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/a64_interface.cpp @@ -11,7 +11,7 @@ #include #include -#include "common/assert.h" +#include #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/llvm_disassemble.h" #include @@ -66,13 +66,13 @@ public: , emitter(block_of_code, conf, jit) , polyfill_options(GenPolyfillOptions(block_of_code)) { - ASSERT(conf.page_table_address_space_bits >= 12 && conf.page_table_address_space_bits <= 64); + assert(conf.page_table_address_space_bits >= 12 && conf.page_table_address_space_bits <= 64); } ~Impl() = default; HaltReason Run() { - ASSERT(!is_executing); + assert(!is_executing); PerformRequestedCacheInvalidation(static_cast(Atomic::Load(&jit_state.halt_reason))); is_executing = true; // TODO: Check code alignment @@ -92,7 +92,7 @@ public: } HaltReason Step() { - ASSERT(!is_executing); + assert(!is_executing); PerformRequestedCacheInvalidation(static_cast(Atomic::Load(&jit_state.halt_reason))); is_executing = true; const HaltReason hr = block_of_code.StepCode(&jit_state, GetCurrentSingleStep()); @@ -116,7 +116,7 @@ public: } void Reset() { - ASSERT(!is_executing); + assert(!is_executing); jit_state = {}; } diff --git a/src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp b/src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp index f41bea6c83..bdd1dd57dd 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp @@ -24,7 +24,7 @@ #include #include -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "dynarmic/backend/x64/xbyak.h" @@ -278,12 +278,12 @@ void BlockOfCode::DisableWriting() { } void BlockOfCode::ClearCache() { - ASSERT(prelude_complete); + assert(prelude_complete); SetCodePtr(code_begin); } size_t BlockOfCode::SpaceRemaining() const { - ASSERT(prelude_complete); + assert(prelude_complete); const u8* current_ptr = getCurr(); if (current_ptr >= &top_[maxSize_]) return 0; @@ -553,7 +553,7 @@ void BlockOfCode::SetCodePtr(CodePtr code_ptr) { void BlockOfCode::EnsurePatchLocationSize(CodePtr begin, size_t size) { size_t current_size = getCurr() - reinterpret_cast(begin); - ASSERT(current_size <= size); + assert(current_size <= size); nop(size - current_size); } diff --git a/src/dynarmic/src/dynarmic/backend/x64/constant_pool.cpp b/src/dynarmic/src/dynarmic/backend/x64/constant_pool.cpp index 127149a29e..c20d61a2eb 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/constant_pool.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/constant_pool.cpp @@ -10,7 +10,7 @@ #include -#include "common/assert.h" +#include #include "dynarmic/backend/x64/block_of_code.h" @@ -29,7 +29,7 @@ Xbyak::Address ConstantPool::GetConstant(const Xbyak::AddressFrame& frame, u64 l const auto constant = ConstantT(lower, upper); auto iter = constant_info.find(constant); if (iter == constant_info.end()) { - ASSERT(insertion_point < pool.size()); + assert(insertion_point < pool.size()); ConstantT& target_constant = pool[insertion_point]; target_constant = constant; iter = constant_info.insert({constant, &target_constant}).first; diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp index 85c0517a19..168a05e67e 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp @@ -10,7 +10,7 @@ #include -#include "common/assert.h" +#include #include #include "dynarmic/mcl/bit.hpp" #include "common/common_types.h" @@ -103,7 +103,7 @@ void EmitX64::PushRSBHelper(Xbyak::Reg64 loc_desc_reg, Xbyak::Reg64 index_reg, I code.mov(qword[code.ABI_JIT_PTR + index_reg * 8 + code.GetJitStateInfo().offsetof_rsb_location_descriptors], loc_desc_reg); code.mov(qword[code.ABI_JIT_PTR + index_reg * 8 + code.GetJitStateInfo().offsetof_rsb_codeptrs], rcx); // Byte size hack - DEBUG_ASSERT(code.GetJitStateInfo().rsb_ptr_mask <= 0xFF); + assert(code.GetJitStateInfo().rsb_ptr_mask <= 0xFF); code.add(index_reg.cvt32(), 1); //flags trashed, 1 single byte, haswell doesn't care code.and_(index_reg.cvt32(), u32(code.GetJitStateInfo().rsb_ptr_mask)); //trashes flags // Results ready and sort by least needed: give OOO some break @@ -144,7 +144,7 @@ void EmitX64::EmitVerboseDebuggingOutput(RegAlloc& reg_alloc) { void EmitX64::EmitPushRSB(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[0].IsImmediate()); + assert(args[0].IsImmediate()); const u64 unique_hash_of_target = args[0].GetImmediateU64(); ctx.reg_alloc.ScratchGpr(code, HostLoc::RCX); @@ -284,7 +284,7 @@ void EmitX64::EmitNZCVFromPackedFlags(EmitContext& ctx, IR::Inst* inst) { } void EmitX64::EmitAddCycles(size_t cycles) { - ASSERT(cycles < (std::numeric_limits::max)()); + assert(cycles < (std::numeric_limits::max)()); code.sub(qword[rsp + ABI_SHADOW_SPACE + offsetof(StackLayout, cycles_remaining)], static_cast(cycles)); } diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp index d05d4aa036..161355bc3f 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp @@ -9,7 +9,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/backend/x64/block_of_code.h" @@ -129,7 +129,7 @@ void EmitX64::EmitIsZero64(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitTestBit(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const Xbyak::Reg64 result = ctx.reg_alloc.UseScratchGpr(code, args[0]); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); // TODO: Flag optimization code.bt(result, args[1].GetImmediateU8()); code.setc(result.cvt8()); diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp index 2b1b9c532b..73fe5c1795 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp @@ -10,7 +10,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/mcl/integer_of_size.hpp" #include "dynarmic/backend/x64/xbyak.h" @@ -1842,7 +1842,7 @@ void EmitX64::EmitFPFixedS32ToSingle(EmitContext& ctx, IR::Inst* inst) { if (rounding_mode == ctx.FPCR().RMode() || ctx.HasOptimization(OptimizationFlag::Unsafe_IgnoreStandardFPCRValue)) { code.cvtsi2ss(result, from); } else { - ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven); + assert(rounding_mode == FP::RoundingMode::ToNearest_TieEven); code.EnterStandardASIMD(); code.cvtsi2ss(result, from); code.LeaveStandardASIMD(); @@ -1878,7 +1878,7 @@ void EmitX64::EmitFPFixedU32ToSingle(EmitContext& ctx, IR::Inst* inst) { if (rounding_mode == ctx.FPCR().RMode() || ctx.HasOptimization(OptimizationFlag::Unsafe_IgnoreStandardFPCRValue)) { op(); } else { - ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven); + assert(rounding_mode == FP::RoundingMode::ToNearest_TieEven); code.EnterStandardASIMD(); op(); code.LeaveStandardASIMD(); @@ -1984,7 +1984,7 @@ void EmitX64::EmitFPFixedS64ToDouble(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code); const size_t fbits = args[1].GetImmediateU8(); const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); - ASSERT(rounding_mode == ctx.FPCR().RMode()); + assert(rounding_mode == ctx.FPCR().RMode()); code.cvtsi2sd(result, from); @@ -2003,7 +2003,7 @@ void EmitX64::EmitFPFixedS64ToSingle(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code); const size_t fbits = args[1].GetImmediateU8(); const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); - ASSERT(rounding_mode == ctx.FPCR().RMode()); + assert(rounding_mode == ctx.FPCR().RMode()); code.cvtsi2ss(result, from); @@ -2022,7 +2022,7 @@ void EmitX64::EmitFPFixedU64ToDouble(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code); const size_t fbits = args[1].GetImmediateU8(); const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); - ASSERT(rounding_mode == ctx.FPCR().RMode()); + assert(rounding_mode == ctx.FPCR().RMode()); if (code.HasHostFeature(HostFeature::AVX512F)) { code.vcvtusi2sd(result, result, from); @@ -2053,7 +2053,7 @@ void EmitX64::EmitFPFixedU64ToSingle(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code); const size_t fbits = args[1].GetImmediateU8(); const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); - ASSERT(rounding_mode == ctx.FPCR().RMode()); + assert(rounding_mode == ctx.FPCR().RMode()); if (code.HasHostFeature(HostFeature::AVX512F)) { const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(code, args[0]); diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc index 54fc595214..df7c5d0d93 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc +++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc @@ -113,7 +113,7 @@ void AxxEmitX64::EmitMemoryRead(AxxEmitContext& ctx, IR::Inst* inst) { }); } else { // Use page table - ASSERT(conf.page_table); + assert(conf.page_table); const auto src_ptr = EmitVAddrLookup(code, ctx, bitsize, *abort, vaddr); EmitReadMemoryMov(code, value_idx, src_ptr, ordered); @@ -200,7 +200,7 @@ void AxxEmitX64::EmitMemoryWrite(AxxEmitContext& ctx, IR::Inst* inst) { }); } else { // Use page table - ASSERT(conf.page_table); + assert(conf.page_table); const auto dest_ptr = EmitVAddrLookup(code, ctx, bitsize, *abort, vaddr); EmitWriteMemoryMov(code, dest_ptr, value_idx, ordered); @@ -216,7 +216,7 @@ void AxxEmitX64::EmitMemoryWrite(AxxEmitContext& ctx, IR::Inst* inst) { template void AxxEmitX64::EmitExclusiveReadMemory(AxxEmitContext& ctx, IR::Inst* inst) { - ASSERT(conf.global_monitor != nullptr); + assert(conf.global_monitor != nullptr); auto args = ctx.reg_alloc.GetArgumentInfo(inst); const bool ordered = IsOrdered(args[2].GetImmediateAccType()); @@ -267,7 +267,7 @@ void AxxEmitX64::EmitExclusiveReadMemory(AxxEmitContext& ctx, IR::Inst* inst) { template void AxxEmitX64::EmitExclusiveWriteMemory(AxxEmitContext& ctx, IR::Inst* inst) { - ASSERT(conf.global_monitor != nullptr); + assert(conf.global_monitor != nullptr); auto args = ctx.reg_alloc.GetArgumentInfo(inst); const bool ordered = IsOrdered(args[3].GetImmediateAccType()); @@ -320,7 +320,7 @@ void AxxEmitX64::EmitExclusiveWriteMemory(AxxEmitContext& ctx, IR::Inst* inst) { template void AxxEmitX64::EmitExclusiveReadMemoryInline(AxxEmitContext& ctx, IR::Inst* inst) { - ASSERT(conf.global_monitor && conf.fastmem_pointer); + assert(conf.global_monitor && conf.fastmem_pointer); if (!exception_handler.SupportsFastmem()) { EmitExclusiveReadMemory(ctx, inst); return; @@ -397,7 +397,7 @@ void AxxEmitX64::EmitExclusiveReadMemoryInline(AxxEmitContext& ctx, IR::Inst* in template void AxxEmitX64::EmitExclusiveWriteMemoryInline(AxxEmitContext& ctx, IR::Inst* inst) { - ASSERT(conf.global_monitor && conf.fastmem_pointer); + assert(conf.global_monitor && conf.fastmem_pointer); if (!exception_handler.SupportsFastmem()) { EmitExclusiveWriteMemory(ctx, inst); return; diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h index b354efcb51..853c202740 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h +++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h @@ -134,7 +134,7 @@ template<> code.and_(tmp, u32((1 << valid_page_index_bits) - 1)); } } else { - ASSERT(valid_page_index_bits < 32); + assert(valid_page_index_bits < 32); code.mov(tmp, vaddr); code.shr(tmp, int(page_table_const_bits)); code.test(tmp, u32(-(1 << valid_page_index_bits))); diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_saturation.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_saturation.cpp index 74e8c76275..48da79f6dd 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_saturation.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_saturation.cpp @@ -8,7 +8,7 @@ #include -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "common/common_types.h" #include "dynarmic/mcl/integer_of_size.hpp" @@ -118,7 +118,7 @@ void EmitX64::EmitSignedSaturation(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const size_t N = args[1].GetImmediateU8(); - ASSERT(N >= 1 && N <= 32); + assert(N >= 1 && N <= 32); if (N == 32) { if (overflow_inst) { @@ -167,7 +167,7 @@ void EmitX64::EmitUnsignedSaturation(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const size_t N = args[1].GetImmediateU8(); - ASSERT(N <= 31); + assert(N <= 31); const u32 saturated_value = (1u << N) - 1; diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_sha.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_sha.cpp index cd166f0cb8..8be898b84f 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_sha.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_sha.cpp @@ -1,4 +1,4 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project +// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project // SPDX-License-Identifier: GPL-3.0-or-later /* This file is part of the dynarmic project. @@ -18,7 +18,7 @@ void EmitX64::EmitSHA256Hash(EmitContext& ctx, IR::Inst* inst) { const bool part1 = args[3].GetImmediateU1(); - ASSERT(code.HasHostFeature(HostFeature::SHA)); + assert(code.HasHostFeature(HostFeature::SHA)); // 3 2 1 0 // x = d c b a @@ -54,7 +54,7 @@ void EmitX64::EmitSHA256Hash(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitSHA256MessageSchedule0(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(code.HasHostFeature(HostFeature::SHA)); + assert(code.HasHostFeature(HostFeature::SHA)); const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(code, args[0]); const Xbyak::Xmm y = ctx.reg_alloc.UseXmm(code, args[1]); @@ -67,7 +67,7 @@ void EmitX64::EmitSHA256MessageSchedule0(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitSHA256MessageSchedule1(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(code.HasHostFeature(HostFeature::SHA)); + assert(code.HasHostFeature(HostFeature::SHA)); const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(code, args[0]); const Xbyak::Xmm y = ctx.reg_alloc.UseXmm(code, args[1]); diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp index 490b310c8c..7aeeb66aa8 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp @@ -12,7 +12,7 @@ #include #include -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "common/common_types.h" #include "dynarmic/mcl/function_info.hpp" @@ -189,7 +189,7 @@ static void EmitTwoArgumentFallback(BlockOfCode& code, EmitContext& ctx, IR::Ins void EmitX64::EmitVectorGetElement8(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); // TODO: DefineValue directly on Argument for index == 0 @@ -213,7 +213,7 @@ void EmitX64::EmitVectorGetElement8(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitVectorGetElement16(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); // TODO: DefineValue directly on Argument for index == 0 @@ -226,7 +226,7 @@ void EmitX64::EmitVectorGetElement16(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitVectorGetElement32(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); // TODO: DefineValue directly on Argument for index == 0 @@ -247,7 +247,7 @@ void EmitX64::EmitVectorGetElement32(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitVectorGetElement64(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); if (index == 0) { @@ -275,7 +275,7 @@ void EmitX64::EmitVectorGetElement64(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitVectorSetElement8(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); const Xbyak::Xmm source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]); @@ -307,7 +307,7 @@ void EmitX64::EmitVectorSetElement8(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitVectorSetElement16(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); const Xbyak::Xmm source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]); @@ -320,7 +320,7 @@ void EmitX64::EmitVectorSetElement16(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitVectorSetElement32(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); const Xbyak::Xmm source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]); @@ -343,7 +343,7 @@ void EmitX64::EmitVectorSetElement32(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitVectorSetElement64(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); const Xbyak::Xmm source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]); @@ -748,9 +748,9 @@ void EmitX64::EmitVectorBroadcast64(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitVectorBroadcastElementLower8(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); - ASSERT(index < 16); + assert(index < 16); if (index > 0) { code.psrldq(a, index); } @@ -772,9 +772,9 @@ void EmitX64::EmitVectorBroadcastElementLower8(EmitContext& ctx, IR::Inst* inst) void EmitX64::EmitVectorBroadcastElementLower16(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); - ASSERT(index < 8); + assert(index < 8); if (index > 0) { code.psrldq(a, u8(index * 2)); } @@ -785,9 +785,9 @@ void EmitX64::EmitVectorBroadcastElementLower16(EmitContext& ctx, IR::Inst* inst void EmitX64::EmitVectorBroadcastElementLower32(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); - ASSERT(index < 4); + assert(index < 4); if (index > 0) { code.psrldq(a, u8(index * 4)); @@ -801,9 +801,9 @@ void EmitX64::EmitVectorBroadcastElementLower32(EmitContext& ctx, IR::Inst* inst void EmitX64::EmitVectorBroadcastElement8(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); - ASSERT(index < 16); + assert(index < 16); if (index > 0) { code.psrldq(a, index); } @@ -825,9 +825,9 @@ void EmitX64::EmitVectorBroadcastElement8(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitVectorBroadcastElement16(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); - ASSERT(index < 8); + assert(index < 8); if (index == 0 && code.HasHostFeature(HostFeature::AVX2)) { code.vpbroadcastw(a, a); } else { @@ -845,9 +845,9 @@ void EmitX64::EmitVectorBroadcastElement16(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitVectorBroadcastElement32(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); - ASSERT(index < 4); + assert(index < 4); code.pshufd(a, a, mcl::bit::replicate_element<2, u8>(index)); @@ -857,9 +857,9 @@ void EmitX64::EmitVectorBroadcastElement32(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitVectorBroadcastElement64(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(code, args[0]); - ASSERT(args[1].IsImmediate()); + assert(args[1].IsImmediate()); const u8 index = args[1].GetImmediateU8(); - ASSERT(index < 2); + assert(index < 2); if (code.HasHostFeature(HostFeature::AVX)) { code.vpermilpd(a, a, mcl::bit::replicate_element<1, u8>(index)); @@ -1345,7 +1345,7 @@ void EmitX64::EmitVectorExtract(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const u8 position = args[2].GetImmediateU8(); - ASSERT(position % 8 == 0); + assert(position % 8 == 0); if (position == 0) { ctx.reg_alloc.DefineValue(code, inst, args[0]); @@ -1377,7 +1377,7 @@ void EmitX64::EmitVectorExtractLower(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm xmm_a = ctx.reg_alloc.UseScratchXmm(code, args[0]); const u8 position = args[2].GetImmediateU8(); - ASSERT(position % 8 == 0); + assert(position % 8 == 0); if (position != 0) { const Xbyak::Xmm xmm_b = ctx.reg_alloc.UseXmm(code, args[1]); @@ -3527,7 +3527,7 @@ void EmitX64::EmitVectorRotateWholeVectorRight(EmitContext& ctx, IR::Inst* inst) const Xbyak::Xmm operand = ctx.reg_alloc.UseXmm(code, args[0]); const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code); const u8 shift_amount = args[1].GetImmediateU8(); - ASSERT(shift_amount % 32 == 0); + assert(shift_amount % 32 == 0); const u8 shuffle_imm = std::rotr(0b11100100, shift_amount / 32 * 2); code.pshufd(result, operand, shuffle_imm); @@ -4591,7 +4591,7 @@ static void EmitVectorSignedSaturatedNarrowToUnsigned(size_t original_esize, Blo code.punpcklbw(reconstructed, xmm0); break; case 32: - ASSERT(code.HasHostFeature(HostFeature::SSE41)); + assert(code.HasHostFeature(HostFeature::SSE41)); code.packusdw(dest, xmm0); // SSE4.1 code.movdqa(reconstructed, dest); code.punpcklwd(reconstructed, xmm0); @@ -4874,11 +4874,11 @@ void EmitX64::EmitVectorSub64(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitVectorTable(EmitContext&, IR::Inst* inst) { // Do nothing. We *want* to hold on to the refcount for our arguments, so VectorTableLookup can use our arguments. - ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times"); + assert(inst->UseCount() == 1 && "Table cannot be used multiple times"); } void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) { - ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable); + assert(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable); auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst()); @@ -5036,7 +5036,7 @@ void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) { code.pxor(xmm0, xmm0); code.punpcklqdq(xmm_table1, xmm0); } else { - ASSERT(table_size == 4); + assert(table_size == 4); const Xbyak::Xmm xmm_table1_upper = ctx.reg_alloc.UseXmm(code, table[3]); code.punpcklqdq(xmm_table1, xmm_table1_upper); ctx.reg_alloc.Release(xmm_table1_upper); @@ -5133,7 +5133,7 @@ void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) { } void EmitX64::EmitVectorTableLookup128(EmitContext& ctx, IR::Inst* inst) { - ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable); + assert(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable); auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst()); diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp index 3c0ce4d6f6..f046ef211a 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp @@ -12,7 +12,7 @@ #include #include -#include "common/assert.h" +#include #include "dynarmic/mcl/function_info.hpp" #include "dynarmic/mcl/integer_of_size.hpp" #include "dynarmic/backend/x64/xbyak.h" @@ -692,7 +692,7 @@ void EmitX64::EmitFPVectorFromSignedFixed32(EmitContext& ctx, IR::Inst* inst) { const int fbits = args[1].GetImmediateU8(); const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); const bool fpcr_controlled = args[3].GetImmediateU1(); - ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); + assert(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { code.cvtdq2ps(xmm, xmm); @@ -710,7 +710,7 @@ void EmitX64::EmitFPVectorFromSignedFixed64(EmitContext& ctx, IR::Inst* inst) { const int fbits = args[1].GetImmediateU8(); const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); const bool fpcr_controlled = args[3].GetImmediateU1(); - ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); + assert(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { if (code.HasHostFeature(HostFeature::AVX512_OrthoFloat)) { @@ -761,7 +761,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed32(EmitContext& ctx, IR::Inst* inst) const int fbits = args[1].GetImmediateU8(); const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); const bool fpcr_controlled = args[3].GetImmediateU1(); - ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); + assert(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { if (code.HasHostFeature(HostFeature::AVX512_Ortho)) { @@ -811,7 +811,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed64(EmitContext& ctx, IR::Inst* inst) const int fbits = args[1].GetImmediateU8(); const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); const bool fpcr_controlled = args[3].GetImmediateU1(); - ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); + assert(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { if (code.HasHostFeature(HostFeature::AVX512_OrthoFloat)) { diff --git a/src/dynarmic/src/dynarmic/backend/x64/exception_handler_windows.cpp b/src/dynarmic/src/dynarmic/backend/x64/exception_handler_windows.cpp index c7249741f9..9b091687dd 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/exception_handler_windows.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/exception_handler_windows.cpp @@ -12,7 +12,7 @@ #include #include -#include "common/assert.h" +#include #include #include "common/common_types.h" @@ -104,7 +104,7 @@ static PrologueInformation GetPrologueInformation() { entry.code.OpInfo = reg; }; const auto alloc_large = [&](u8 offset, size_t size) { - ASSERT(size % 8 == 0); + assert(size % 8 == 0); size /= 8; auto& entry = next_entry(); @@ -123,7 +123,7 @@ static PrologueInformation GetPrologueInformation() { } }; const auto save_xmm128 = [&](u8 offset, u8 reg, size_t frame_offset) { - ASSERT(frame_offset % 16 == 0); + assert(frame_offset % 16 == 0); auto& entry = next_entry(); entry.code.CodeOffset = offset; @@ -165,7 +165,7 @@ static PrologueInformation GetPrologueInformation() { auto& last_entry = next_entry(); last_entry.FrameOffset = 0; } - ASSERT(ret.unwind_code.size() % 2 == 0); + assert(ret.unwind_code.size() % 2 == 0); return ret; } diff --git a/src/dynarmic/src/dynarmic/backend/x64/exclusive_monitor.cpp b/src/dynarmic/src/dynarmic/backend/x64/exclusive_monitor.cpp index c7fee69214..71054c31f3 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/exclusive_monitor.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/exclusive_monitor.cpp @@ -10,7 +10,7 @@ #include -#include "common/assert.h" +#include namespace Dynarmic { diff --git a/src/dynarmic/src/dynarmic/backend/x64/hostloc.h b/src/dynarmic/src/dynarmic/backend/x64/hostloc.h index 7191a0ceba..225392e431 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/hostloc.h +++ b/src/dynarmic/src/dynarmic/backend/x64/hostloc.h @@ -10,7 +10,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/backend/x64/xbyak.h" @@ -80,12 +80,12 @@ constexpr bool HostLocIsFlag(HostLoc reg) { } constexpr HostLoc HostLocRegIdx(int idx) { - ASSERT(idx >= 0 && idx <= 15); + assert(idx >= 0 && idx <= 15); return HostLoc(idx); } constexpr HostLoc HostLocXmmIdx(int idx) { - ASSERT(idx >= 0 && idx <= 15); + assert(idx >= 0 && idx <= 15); return HostLoc(size_t(HostLoc::XMM0) + idx); } @@ -161,12 +161,12 @@ const std::bitset<32> any_xmm = BuildRegSet({ }); inline Xbyak::Reg64 HostLocToReg64(HostLoc loc) noexcept { - ASSERT(HostLocIsGPR(loc)); + assert(HostLocIsGPR(loc)); return Xbyak::Reg64(int(loc)); } inline Xbyak::Xmm HostLocToXmm(HostLoc loc) noexcept { - ASSERT(HostLocIsXMM(loc)); + assert(HostLocIsXMM(loc)); return Xbyak::Xmm(int(loc) - int(HostLoc::XMM0)); } diff --git a/src/dynarmic/src/dynarmic/backend/x64/oparg.h b/src/dynarmic/src/dynarmic/backend/x64/oparg.h index 7366c0c7a3..73cce40ff3 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/oparg.h +++ b/src/dynarmic/src/dynarmic/backend/x64/oparg.h @@ -8,7 +8,7 @@ #pragma once -#include "common/assert.h" +#include #include "dynarmic/backend/x64/xbyak.h" namespace Dynarmic::Backend::X64 { diff --git a/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp b/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp index 4b4890cfab..dfd8d159c3 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp @@ -13,7 +13,7 @@ #include #include "dynarmic/backend/x64/hostloc.h" -#include "common/assert.h" +#include #include #include "dynarmic/backend/x64/xbyak.h" @@ -56,11 +56,11 @@ static inline bool IsValuelessType(const IR::Type type) noexcept { } void HostLocInfo::ReleaseOne() noexcept { - ASSERT(is_being_used_count > 0); + assert(is_being_used_count > 0); --is_being_used_count; is_scratch = false; if (current_references > 0) { - ASSERT(size_t(accumulated_uses) + 1 < (std::numeric_limits::max)()); + assert(size_t(accumulated_uses) + 1 < (std::numeric_limits::max)()); ++accumulated_uses; --current_references; if (current_references == 0) @@ -69,7 +69,7 @@ void HostLocInfo::ReleaseOne() noexcept { } void HostLocInfo::ReleaseAll() noexcept { - ASSERT(size_t(accumulated_uses) + current_references < (std::numeric_limits::max)()); + assert(size_t(accumulated_uses) + current_references < (std::numeric_limits::max)()); accumulated_uses += current_references; current_references = 0; is_set_last_use = false; @@ -91,7 +91,7 @@ void HostLocInfo::AddValue(HostLoc loc, IR::Inst* inst) noexcept { } values.push_back(inst); - ASSERT(size_t(total_uses) + inst->UseCount() < (std::numeric_limits::max)()); + assert(size_t(total_uses) + inst->UseCount() < (std::numeric_limits::max)()); total_uses += inst->UseCount(); max_bit_width = std::max(max_bit_width, std::countr_zero(GetBitWidth(inst->GetType()))); } @@ -129,24 +129,24 @@ bool Argument::GetImmediateU1() const noexcept { u8 Argument::GetImmediateU8() const noexcept { const u64 imm = value.GetImmediateAsU64(); - ASSERT(imm <= u64(std::numeric_limits::max())); + assert(imm <= u64(std::numeric_limits::max())); return u8(imm); } u16 Argument::GetImmediateU16() const noexcept { const u64 imm = value.GetImmediateAsU64(); - ASSERT(imm <= u64(std::numeric_limits::max())); + assert(imm <= u64(std::numeric_limits::max())); return u16(imm); } u32 Argument::GetImmediateU32() const noexcept { const u64 imm = value.GetImmediateAsU64(); - ASSERT(imm <= u64(std::numeric_limits::max())); + assert(imm <= u64(std::numeric_limits::max())); return u32(imm); } u64 Argument::GetImmediateS32() const noexcept { - ASSERT(FitsInImmediateS32()); + assert(FitsInImmediateS32()); return value.GetImmediateAsU64(); } @@ -155,12 +155,12 @@ u64 Argument::GetImmediateU64() const noexcept { } IR::Cond Argument::GetImmediateCond() const noexcept { - ASSERT(IsImmediate() && GetType() == IR::Type::Cond); + assert(IsImmediate() && GetType() == IR::Type::Cond); return value.GetCond(); } IR::AccType Argument::GetImmediateAccType() const noexcept { - ASSERT(IsImmediate() && GetType() == IR::Type::AccType); + assert(IsImmediate() && GetType() == IR::Type::AccType); return value.GetAccType(); } @@ -201,7 +201,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(const IR::Inst* inst) noexcept ret[i].value = arg; if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) { auto const loc = ValueLocation(arg.GetInst()); - ASSERT(loc && "argument must already been defined"); + assert(loc && "argument must already been defined"); LocInfo(*loc).AddArgReference(); } } @@ -209,7 +209,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(const IR::Inst* inst) noexcept } void RegAlloc::RegisterPseudoOperation(const IR::Inst* inst) noexcept { - ASSERT(IsValueLive(inst) || !inst->HasUses()); + assert(IsValueLive(inst) || !inst->HasUses()); for (size_t i = 0; i < inst->NumArgs(); i++) { auto const arg = inst->GetArg(i); if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) { @@ -222,37 +222,37 @@ void RegAlloc::RegisterPseudoOperation(const IR::Inst* inst) noexcept { } Xbyak::Reg64 RegAlloc::UseScratchGpr(BlockOfCode& code, Argument& arg) noexcept { - ASSERT(!arg.allocated); + assert(!arg.allocated); arg.allocated = true; return HostLocToReg64(UseScratchImpl(code, arg.value, gpr_order)); } Xbyak::Xmm RegAlloc::UseScratchXmm(BlockOfCode& code, Argument& arg) noexcept { - ASSERT(!arg.allocated); + assert(!arg.allocated); arg.allocated = true; return HostLocToXmm(UseScratchImpl(code, arg.value, xmm_order)); } void RegAlloc::UseScratch(BlockOfCode& code, Argument& arg, HostLoc host_loc) noexcept { - ASSERT(!arg.allocated); + assert(!arg.allocated); arg.allocated = true; UseScratchImpl(code, arg.value, BuildRegSet({host_loc})); } void RegAlloc::DefineValue(BlockOfCode& code, IR::Inst* inst, const Xbyak::Reg& reg) noexcept { - ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG); + assert(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG); const auto hostloc = static_cast(reg.getIdx() + static_cast(reg.getKind() == Xbyak::Operand::XMM ? HostLoc::XMM0 : HostLoc::RAX)); DefineValueImpl(code, inst, hostloc); } void RegAlloc::DefineValue(BlockOfCode& code, IR::Inst* inst, Argument& arg) noexcept { - ASSERT(!arg.allocated); + assert(!arg.allocated); arg.allocated = true; DefineValueImpl(code, inst, arg.value); } void RegAlloc::Release(const Xbyak::Reg& reg) noexcept { - ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG); + assert(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG); const auto hostloc = static_cast(reg.getIdx() + static_cast(reg.getKind() == Xbyak::Operand::XMM ? HostLoc::XMM0 : HostLoc::RAX)); LocInfo(hostloc).ReleaseOne(); } @@ -382,15 +382,15 @@ void RegAlloc::HostCall( } void RegAlloc::AllocStackSpace(BlockOfCode& code, const size_t stack_space) noexcept { - ASSERT(stack_space < size_t((std::numeric_limits::max)())); - ASSERT(reserved_stack_space == 0); + assert(stack_space < size_t((std::numeric_limits::max)())); + assert(reserved_stack_space == 0); reserved_stack_space = stack_space; code.sub(code.rsp, u32(stack_space)); } void RegAlloc::ReleaseStackSpace(BlockOfCode& code, const size_t stack_space) noexcept { - ASSERT(stack_space < size_t((std::numeric_limits::max)())); - ASSERT(reserved_stack_space == stack_space); + assert(stack_space < size_t((std::numeric_limits::max)())); + assert(reserved_stack_space == stack_space); reserved_stack_space = 0; code.add(code.rsp, u32(stack_space)); } @@ -410,7 +410,7 @@ HostLoc RegAlloc::SelectARegister(std::bitset<32> desired_locations) const noexc for (HostLoc i = HostLoc(0); i < HostLoc(desired_locations.size()); i = HostLoc(size_t(i) + 1)) { if (desired_locations.test(size_t(i))) { auto const& loc_info = LocInfo(i); - DEBUG_ASSERT(i != ABI_JIT_PTR); + assert(i != ABI_JIT_PTR); // Abstain from using upper registers unless absolutely nescesary if (loc_info.IsLocked()) { // skip, not suitable for allocation @@ -448,7 +448,7 @@ HostLoc RegAlloc::SelectARegister(std::bitset<32> desired_locations) const noexc auto const it_final = it_empty_candidate != HostLoc::FirstSpill ? it_empty_candidate : it_candidate != HostLoc::FirstSpill ? it_candidate : it_rex_candidate; - ASSERT(it_final != HostLoc::FirstSpill && "All candidate registers have already been allocated"); + assert(it_final != HostLoc::FirstSpill && "All candidate registers have already been allocated"); // Evil magic - increment LRU counter (will wrap at 256) const_cast(this)->LocInfo(HostLoc(it_final)).lru_counter++; return HostLoc(it_final); @@ -458,26 +458,26 @@ std::optional RegAlloc::ValueLocation(const IR::Inst* value) const noex for (size_t i = 0; i < hostloc_info.size(); i++) if (hostloc_info[i].ContainsValue(value)) { //for (size_t j = 0; j < hostloc_info.size(); ++j) - // ASSERT((i == j || !hostloc_info[j].ContainsValue(value)) && "duplicate defs"); + // assert((i == j || !hostloc_info[j].ContainsValue(value)) && "duplicate defs"); return HostLoc(i); } return std::nullopt; } void RegAlloc::DefineValueImpl(BlockOfCode& code, IR::Inst* def_inst, HostLoc host_loc) noexcept { - ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined"); + assert(!ValueLocation(def_inst) && "def_inst has already been defined"); LocInfo(host_loc).AddValue(host_loc, def_inst); - ASSERT(*ValueLocation(def_inst) == host_loc); + assert(*ValueLocation(def_inst) == host_loc); } void RegAlloc::DefineValueImpl(BlockOfCode& code, IR::Inst* def_inst, const IR::Value& use_inst) noexcept { - ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined"); + assert(!ValueLocation(def_inst) && "def_inst has already been defined"); if (use_inst.IsImmediate()) { const HostLoc location = ScratchImpl(code, gpr_order); DefineValueImpl(code, def_inst, location); LoadImmediate(code, use_inst, location); } else { - ASSERT(ValueLocation(use_inst.GetInst()) && "use_inst must already be defined"); + assert(ValueLocation(use_inst.GetInst()) && "use_inst must already be defined"); const HostLoc location = *ValueLocation(use_inst.GetInst()); DefineValueImpl(code, def_inst, location); } @@ -485,22 +485,22 @@ void RegAlloc::DefineValueImpl(BlockOfCode& code, IR::Inst* def_inst, const IR:: void RegAlloc::Move(BlockOfCode& code, HostLoc to, HostLoc from) noexcept { const size_t bit_width = LocInfo(from).GetMaxBitWidth(); - ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsLocked()); - ASSERT(bit_width <= HostLocBitWidth(to)); - ASSERT(!LocInfo(from).IsEmpty() && "Mov eliminated"); + assert(LocInfo(to).IsEmpty() && !LocInfo(from).IsLocked()); + assert(bit_width <= HostLocBitWidth(to)); + assert(!LocInfo(from).IsEmpty() && "Mov eliminated"); EmitMove(code, bit_width, to, from); LocInfo(to) = std::exchange(LocInfo(from), {}); } void RegAlloc::CopyToScratch(BlockOfCode& code, size_t bit_width, HostLoc to, HostLoc from) noexcept { - ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsEmpty()); + assert(LocInfo(to).IsEmpty() && !LocInfo(from).IsEmpty()); EmitMove(code, bit_width, to, from); } void RegAlloc::Exchange(BlockOfCode& code, HostLoc a, HostLoc b) noexcept { - ASSERT(!LocInfo(a).IsLocked() && !LocInfo(b).IsLocked()); - ASSERT(LocInfo(a).GetMaxBitWidth() <= HostLocBitWidth(b)); - ASSERT(LocInfo(b).GetMaxBitWidth() <= HostLocBitWidth(a)); + assert(!LocInfo(a).IsLocked() && !LocInfo(b).IsLocked()); + assert(LocInfo(a).GetMaxBitWidth() <= HostLocBitWidth(b)); + assert(LocInfo(b).GetMaxBitWidth() <= HostLocBitWidth(a)); if (LocInfo(a).IsEmpty()) { Move(code, a, b); @@ -513,16 +513,16 @@ void RegAlloc::Exchange(BlockOfCode& code, HostLoc a, HostLoc b) noexcept { } void RegAlloc::MoveOutOfTheWay(BlockOfCode& code, HostLoc reg) noexcept { - ASSERT(!LocInfo(reg).IsLocked()); + assert(!LocInfo(reg).IsLocked()); if (!LocInfo(reg).IsEmpty()) { SpillRegister(code, reg); } } void RegAlloc::SpillRegister(BlockOfCode& code, HostLoc loc) noexcept { - ASSERT(HostLocIsRegister(loc) && "Only registers can be spilled"); - ASSERT(!LocInfo(loc).IsEmpty() && "There is no need to spill unoccupied registers"); - ASSERT(!LocInfo(loc).IsLocked() && "Registers that have been allocated must not be spilt"); + assert(HostLocIsRegister(loc) && "Only registers can be spilled"); + assert(!LocInfo(loc).IsEmpty() && "There is no need to spill unoccupied registers"); + assert(!LocInfo(loc).IsLocked() && "Registers that have been allocated must not be spilt"); auto const new_loc = FindFreeSpill(HostLocIsXMM(loc)); Move(code, new_loc, loc); } @@ -558,7 +558,7 @@ HostLoc RegAlloc::FindFreeSpill(bool is_xmm) const noexcept { }() HostLoc RegAlloc::LoadImmediate(BlockOfCode& code, IR::Value imm, HostLoc host_loc) noexcept { - ASSERT(imm.IsImmediate() && "imm is not an immediate"); + assert(imm.IsImmediate() && "imm is not an immediate"); if (HostLocIsGPR(host_loc)) { const Xbyak::Reg64 reg = HostLocToReg64(host_loc); const u64 imm_value = imm.GetImmediateAsU64(); @@ -583,9 +583,9 @@ HostLoc RegAlloc::LoadImmediate(BlockOfCode& code, IR::Value imm, HostLoc host_l void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc to, const HostLoc from) noexcept { auto const spill_to_op_arg_helper = [&](HostLoc loc, size_t reserved_stack_space) { - ASSERT(HostLocIsSpill(loc)); + assert(HostLocIsSpill(loc)); size_t i = size_t(loc) - size_t(HostLoc::FirstSpill); - ASSERT(i < SpillCount && "Spill index greater than number of available spill locations"); + assert(i < SpillCount && "Spill index greater than number of available spill locations"); return Xbyak::util::rsp + reserved_stack_space + ABI_SHADOW_SPACE + offsetof(StackLayout, spill) + i * sizeof(StackLayout::spill[0]); }; auto const spill_xmm_to_op = [&](const HostLoc loc) { @@ -594,21 +594,21 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc if (HostLocIsXMM(to) && HostLocIsXMM(from)) { MAYBE_AVX(movaps, HostLocToXmm(to), HostLocToXmm(from)); } else if (HostLocIsGPR(to) && HostLocIsGPR(from)) { - ASSERT(bit_width != 128); + assert(bit_width != 128); if (bit_width == 64) { code.mov(HostLocToReg64(to), HostLocToReg64(from)); } else { code.mov(HostLocToReg64(to).cvt32(), HostLocToReg64(from).cvt32()); } } else if (HostLocIsXMM(to) && HostLocIsGPR(from)) { - ASSERT(bit_width != 128); + assert(bit_width != 128); if (bit_width == 64) { MAYBE_AVX(movq, HostLocToXmm(to), HostLocToReg64(from)); } else { MAYBE_AVX(movd, HostLocToXmm(to), HostLocToReg64(from).cvt32()); } } else if (HostLocIsGPR(to) && HostLocIsXMM(from)) { - ASSERT(bit_width != 128); + assert(bit_width != 128); if (bit_width == 64) { MAYBE_AVX(movq, HostLocToReg64(to), HostLocToXmm(from)); } else { @@ -616,7 +616,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc } } else if (HostLocIsXMM(to) && HostLocIsSpill(from)) { const Xbyak::Address spill_addr = spill_xmm_to_op(from); - ASSERT(spill_addr.getBit() >= bit_width); + assert(spill_addr.getBit() >= bit_width); switch (bit_width) { case 128: MAYBE_AVX(movaps, HostLocToXmm(to), spill_addr); @@ -634,7 +634,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc } } else if (HostLocIsSpill(to) && HostLocIsXMM(from)) { const Xbyak::Address spill_addr = spill_xmm_to_op(to); - ASSERT(spill_addr.getBit() >= bit_width); + assert(spill_addr.getBit() >= bit_width); switch (bit_width) { case 128: MAYBE_AVX(movaps, spill_addr, HostLocToXmm(from)); @@ -651,14 +651,14 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc UNREACHABLE(); } } else if (HostLocIsGPR(to) && HostLocIsSpill(from)) { - ASSERT(bit_width != 128); + assert(bit_width != 128); if (bit_width == 64) { code.mov(HostLocToReg64(to), Xbyak::util::qword[spill_to_op_arg_helper(from, reserved_stack_space)]); } else { code.mov(HostLocToReg64(to).cvt32(), Xbyak::util::dword[spill_to_op_arg_helper(from, reserved_stack_space)]); } } else if (HostLocIsSpill(to) && HostLocIsGPR(from)) { - ASSERT(bit_width != 128); + assert(bit_width != 128); if (bit_width == 64) { code.mov(Xbyak::util::qword[spill_to_op_arg_helper(to, reserved_stack_space)], HostLocToReg64(from)); } else { @@ -671,7 +671,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc #undef MAYBE_AVX void RegAlloc::EmitExchange(BlockOfCode& code, const HostLoc a, const HostLoc b) noexcept { - ASSERT(HostLocIsGPR(a) && HostLocIsGPR(b) && "Exchanging XMM registers is uneeded OR invalid emit"); + assert(HostLocIsGPR(a) && HostLocIsGPR(b) && "Exchanging XMM registers is uneeded OR invalid emit"); code.xchg(HostLocToReg64(a), HostLocToReg64(b)); } diff --git a/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.h b/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.h index 93c5e05af7..3ca92216cd 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.h +++ b/src/dynarmic/src/dynarmic/backend/x64/reg_alloc.h @@ -49,19 +49,19 @@ public: return is_being_used_count == 0 && current_references == 1 && size_t(accumulated_uses) + 1 == size_t(total_uses); } inline void ReadLock() noexcept { - ASSERT(size_t(is_being_used_count) + 1 < (std::numeric_limits::max)()); - ASSERT(!is_scratch); + assert(size_t(is_being_used_count) + 1 < (std::numeric_limits::max)()); + assert(!is_scratch); is_being_used_count++; } inline void WriteLock() noexcept { - ASSERT(is_being_used_count == 0); + assert(is_being_used_count == 0); is_being_used_count++; is_scratch = true; } inline void AddArgReference() noexcept { - ASSERT(size_t(current_references) + 1 < (std::numeric_limits::max)()); + assert(size_t(current_references) + 1 < (std::numeric_limits::max)()); ++current_references; - ASSERT(size_t(accumulated_uses) + current_references <= size_t(total_uses)); + assert(size_t(accumulated_uses) + current_references <= size_t(total_uses)); } void ReleaseOne() noexcept; void ReleaseAll() noexcept; @@ -147,12 +147,12 @@ public: return !!ValueLocation(inst); } inline Xbyak::Reg64 UseGpr(BlockOfCode& code, Argument& arg) noexcept { - ASSERT(!arg.allocated); + assert(!arg.allocated); arg.allocated = true; return HostLocToReg64(UseImpl(code, arg.value, gpr_order)); } inline Xbyak::Xmm UseXmm(BlockOfCode& code, Argument& arg) noexcept { - ASSERT(!arg.allocated); + assert(!arg.allocated); arg.allocated = true; return HostLocToXmm(UseImpl(code, arg.value, xmm_order)); } @@ -160,7 +160,7 @@ public: return UseGpr(code, arg); } inline void Use(BlockOfCode& code, Argument& arg, const HostLoc host_loc) noexcept { - ASSERT(!arg.allocated); + assert(!arg.allocated); arg.allocated = true; UseImpl(code, arg.value, BuildRegSet({host_loc})); } @@ -205,7 +205,7 @@ public: iter.ReleaseAll(); } inline void AssertNoMoreUses() noexcept { - ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), [](const auto& i) noexcept { return i.IsEmpty(); })); + assert(std::all_of(hostloc_info.begin(), hostloc_info.end(), [](const auto& i) noexcept { return i.IsEmpty(); })); } #ifndef NDEBUG inline void EmitVerboseDebuggingOutput(BlockOfCode& code) noexcept { @@ -234,11 +234,11 @@ private: HostLoc FindFreeSpill(bool is_xmm) const noexcept; inline HostLocInfo& LocInfo(const HostLoc loc) noexcept { - DEBUG_ASSERT(loc != HostLoc::RSP && loc != ABI_JIT_PTR); + assert(loc != HostLoc::RSP && loc != ABI_JIT_PTR); return hostloc_info[size_t(loc)]; } inline const HostLocInfo& LocInfo(const HostLoc loc) const noexcept { - DEBUG_ASSERT(loc != HostLoc::RSP && loc != ABI_JIT_PTR); + assert(loc != HostLoc::RSP && loc != ABI_JIT_PTR); return hostloc_info[size_t(loc)]; } diff --git a/src/dynarmic/src/dynarmic/common/fp/fpcr.h b/src/dynarmic/src/dynarmic/common/fp/fpcr.h index 038800c7c2..4af365e24c 100644 --- a/src/dynarmic/src/dynarmic/common/fp/fpcr.h +++ b/src/dynarmic/src/dynarmic/common/fp/fpcr.h @@ -10,7 +10,7 @@ #include -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "common/common_types.h" @@ -73,7 +73,7 @@ public: /// Set rounding mode control field. void RMode(FP::RoundingMode rounding_mode) { - ASSERT(static_cast(rounding_mode) <= 0b11 && "FPCR: Invalid rounding mode"); + assert(static_cast(rounding_mode) <= 0b11 && "FPCR: Invalid rounding mode"); value = mcl::bit::set_bits<22, 23>(value, static_cast(rounding_mode)); } @@ -93,7 +93,7 @@ public: /// Set the stride of a vector when executing AArch32 VFP instructions. /// This field has no function in AArch64 state. void Stride(size_t stride) { - ASSERT(stride >= 1 && stride <= 2 && "FPCR: Invalid stride"); + assert(stride >= 1 && stride <= 2 && "FPCR: Invalid stride"); value = mcl::bit::set_bits<20, 21>(value, stride == 1 ? 0b00u : 0b11u); } @@ -116,7 +116,7 @@ public: /// Sets the length of a vector when executing AArch32 VFP instructions. /// This field has no function in AArch64 state. void Len(size_t len) { - ASSERT(len >= 1 && len <= 8 && "FPCR: Invalid len"); + assert(len >= 1 && len <= 8 && "FPCR: Invalid len"); value = mcl::bit::set_bits<16, 18>(value, static_cast(len - 1)); } diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp b/src/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp index 42de9a0ed1..77a187ba19 100644 --- a/src/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp +++ b/src/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp @@ -10,7 +10,7 @@ #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/common/fp/fpcr.h" diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp b/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp index 426c66efec..79c216a609 100644 --- a/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp +++ b/src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp @@ -8,7 +8,7 @@ #include "dynarmic/common/fp/op/FPRoundInt.h" -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "common/common_types.h" @@ -26,7 +26,7 @@ namespace Dynarmic::FP { template u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr) { - ASSERT(rounding != RoundingMode::ToOdd); + assert(rounding != RoundingMode::ToOdd); auto [type, sign, value] = FPUnpack(op, fpcr, fpsr); diff --git a/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp b/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp index d920f2d900..8725d2a927 100644 --- a/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp +++ b/src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp @@ -9,7 +9,7 @@ #include "dynarmic/common/fp/op/FPToFixed.h" #include -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "common/common_types.h" @@ -25,9 +25,9 @@ namespace Dynarmic::FP { template u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, RoundingMode rounding, FPSR& fpsr) { - ASSERT(rounding != RoundingMode::ToOdd); - ASSERT(ibits <= 64); - ASSERT(fbits <= ibits); + assert(rounding != RoundingMode::ToOdd); + assert(ibits <= 64); + assert(fbits <= ibits); auto [type, sign, value] = FPUnpack(op, fpcr, fpsr); diff --git a/src/dynarmic/src/dynarmic/common/fp/process_exception.cpp b/src/dynarmic/src/dynarmic/common/fp/process_exception.cpp index 2fee438246..013d1a7bb4 100644 --- a/src/dynarmic/src/dynarmic/common/fp/process_exception.cpp +++ b/src/dynarmic/src/dynarmic/common/fp/process_exception.cpp @@ -8,7 +8,7 @@ #include "dynarmic/common/fp/process_exception.h" -#include "common/assert.h" +#include #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" @@ -18,27 +18,27 @@ namespace Dynarmic::FP { void FPProcessException(FPExc exception, FPCR fpcr, FPSR& fpsr) { switch (exception) { case FPExc::InvalidOp: - ASSERT(!fpcr.IOE() && "Raising floating point exceptions unimplemented"); + assert(!fpcr.IOE() && "Raising floating point exceptions unimplemented"); fpsr.IOC(true); break; case FPExc::DivideByZero: - ASSERT(!fpcr.DZE() && "Raising floating point exceptions unimplemented"); + assert(!fpcr.DZE() && "Raising floating point exceptions unimplemented"); fpsr.DZC(true); break; case FPExc::Overflow: - ASSERT(!fpcr.OFE() && "Raising floating point exceptions unimplemented"); + assert(!fpcr.OFE() && "Raising floating point exceptions unimplemented"); fpsr.OFC(true); break; case FPExc::Underflow: - ASSERT(!fpcr.UFE() && "Raising floating point exceptions unimplemented"); + assert(!fpcr.UFE() && "Raising floating point exceptions unimplemented"); fpsr.UFC(true); break; case FPExc::Inexact: - ASSERT(!fpcr.IXE() && "Raising floating point exceptions unimplemented"); + assert(!fpcr.IXE() && "Raising floating point exceptions unimplemented"); fpsr.IXC(true); break; case FPExc::InputDenorm: - ASSERT(!fpcr.IDE() && "Raising floating point exceptions unimplemented"); + assert(!fpcr.IDE() && "Raising floating point exceptions unimplemented"); fpsr.IDC(true); break; default: diff --git a/src/dynarmic/src/dynarmic/common/fp/process_nan.cpp b/src/dynarmic/src/dynarmic/common/fp/process_nan.cpp index acc9c329e8..6ac0de5fe7 100644 --- a/src/dynarmic/src/dynarmic/common/fp/process_nan.cpp +++ b/src/dynarmic/src/dynarmic/common/fp/process_nan.cpp @@ -10,7 +10,7 @@ #include -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "dynarmic/common/fp/fpcr.h" @@ -23,7 +23,7 @@ namespace Dynarmic::FP { template FPT FPProcessNaN(FPType type, FPT op, FPCR fpcr, FPSR& fpsr) { - ASSERT(type == FPType::QNaN || type == FPType::SNaN); + assert(type == FPType::QNaN || type == FPType::SNaN); constexpr size_t topfrac = FPInfo::explicit_mantissa_width - 1; diff --git a/src/dynarmic/src/dynarmic/common/fp/unpacked.cpp b/src/dynarmic/src/dynarmic/common/fp/unpacked.cpp index d6bb615cb4..b27eb9b48b 100644 --- a/src/dynarmic/src/dynarmic/common/fp/unpacked.cpp +++ b/src/dynarmic/src/dynarmic/common/fp/unpacked.cpp @@ -85,8 +85,8 @@ std::tuple Normalize(FPUnpacked op, int extra_rig template FPT FPRoundBase(FPUnpacked op, FPCR fpcr, RoundingMode rounding, FPSR& fpsr) { - ASSERT(op.mantissa != 0); - ASSERT(rounding != RoundingMode::ToNearest_TieAwayFromZero); + assert(op.mantissa != 0); + assert(rounding != RoundingMode::ToNearest_TieAwayFromZero); constexpr int minimum_exp = FPInfo::exponent_min; constexpr size_t E = FPInfo::exponent_width; diff --git a/src/dynarmic/src/dynarmic/common/llvm_disassemble.cpp b/src/dynarmic/src/dynarmic/common/llvm_disassemble.cpp index 6aff6d6cc7..f22d460327 100644 --- a/src/dynarmic/src/dynarmic/common/llvm_disassemble.cpp +++ b/src/dynarmic/src/dynarmic/common/llvm_disassemble.cpp @@ -15,7 +15,7 @@ # include #endif -#include "common/assert.h" +#include #include #include "common/common_types.h" @@ -37,7 +37,7 @@ std::string DisassembleX64(const void* begin, const void* end) { while (pos < end) { char buffer[80]; size_t inst_size = LLVMDisasmInstruction(llvm_ctx, const_cast(pos), remaining, reinterpret_cast(pos), buffer, sizeof(buffer)); - ASSERT(inst_size); + assert(inst_size); for (const u8* i = pos; i < pos + inst_size; i++) result += fmt::format("{:02x} ", *i); for (size_t i = inst_size; i < 10; i++) diff --git a/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp b/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp index 7848539186..3ec743db07 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp @@ -8,7 +8,7 @@ #include "dynarmic/frontend/A32/a32_ir_emitter.h" -#include "common/assert.h" +#include #include "dynarmic/frontend/A32/a32_types.h" #include "dynarmic/interface/A32/arch_version.h" @@ -64,12 +64,12 @@ IR::U32U64 IREmitter::GetExtendedRegister(ExtReg reg) { } IR::U128 IREmitter::GetVector(ExtReg reg) { - ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg)); + assert(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg)); return Inst(Opcode::A32GetVector, IR::Value(reg)); } void IREmitter::SetRegister(const Reg reg, const IR::U32& value) { - ASSERT(reg != A32::Reg::PC); + assert(reg != A32::Reg::PC); Inst(Opcode::A32SetRegister, IR::Value(reg), value); } @@ -84,7 +84,7 @@ void IREmitter::SetExtendedRegister(const ExtReg reg, const IR::U32U64& value) { } void IREmitter::SetVector(ExtReg reg, const IR::U128& value) { - ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg)); + assert(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg)); Inst(Opcode::A32SetVector, IR::Value(reg), value); } @@ -361,7 +361,7 @@ IR::U32 IREmitter::ExclusiveWriteMemory64(const IR::U32& vaddr, const IR::U32& v } void IREmitter::CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1, CoprocReg CRd, CoprocReg CRn, CoprocReg CRm, size_t opc2) { - ASSERT(coproc_no <= 15); + assert(coproc_no <= 15); const IR::Value::CoprocessorInfo coproc_info{static_cast(coproc_no), static_cast(two ? 1 : 0), static_cast(opc1), @@ -373,7 +373,7 @@ void IREmitter::CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1, } void IREmitter::CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, CoprocReg CRn, CoprocReg CRm, size_t opc2, const IR::U32& word) { - ASSERT(coproc_no <= 15); + assert(coproc_no <= 15); const IR::Value::CoprocessorInfo coproc_info{static_cast(coproc_no), static_cast(two ? 1 : 0), static_cast(opc1), @@ -384,7 +384,7 @@ void IREmitter::CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, Copro } void IREmitter::CoprocSendTwoWords(size_t coproc_no, bool two, size_t opc, CoprocReg CRm, const IR::U32& word1, const IR::U32& word2) { - ASSERT(coproc_no <= 15); + assert(coproc_no <= 15); const IR::Value::CoprocessorInfo coproc_info{static_cast(coproc_no), static_cast(two ? 1 : 0), static_cast(opc), @@ -393,7 +393,7 @@ void IREmitter::CoprocSendTwoWords(size_t coproc_no, bool two, size_t opc, Copro } IR::U32 IREmitter::CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, CoprocReg CRn, CoprocReg CRm, size_t opc2) { - ASSERT(coproc_no <= 15); + assert(coproc_no <= 15); const IR::Value::CoprocessorInfo coproc_info{static_cast(coproc_no), static_cast(two ? 1 : 0), static_cast(opc1), @@ -404,7 +404,7 @@ IR::U32 IREmitter::CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, Cop } IR::U64 IREmitter::CoprocGetTwoWords(size_t coproc_no, bool two, size_t opc, CoprocReg CRm) { - ASSERT(coproc_no <= 15); + assert(coproc_no <= 15); const IR::Value::CoprocessorInfo coproc_info{static_cast(coproc_no), static_cast(two ? 1 : 0), static_cast(opc), @@ -413,7 +413,7 @@ IR::U64 IREmitter::CoprocGetTwoWords(size_t coproc_no, bool two, size_t opc, Cop } void IREmitter::CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option) { - ASSERT(coproc_no <= 15); + assert(coproc_no <= 15); const IR::Value::CoprocessorInfo coproc_info{static_cast(coproc_no), static_cast(two ? 1 : 0), static_cast(long_transfer ? 1 : 0), @@ -424,7 +424,7 @@ void IREmitter::CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer, } void IREmitter::CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option) { - ASSERT(coproc_no <= 15); + assert(coproc_no <= 15); const IR::Value::CoprocessorInfo coproc_info{static_cast(coproc_no), static_cast(two ? 1 : 0), static_cast(long_transfer ? 1 : 0), diff --git a/src/dynarmic/src/dynarmic/frontend/A32/a32_types.h b/src/dynarmic/src/dynarmic/frontend/A32/a32_types.h index 957c643f56..30c683eb7b 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/a32_types.h +++ b/src/dynarmic/src/dynarmic/frontend/A32/a32_types.h @@ -10,7 +10,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/interface/A32/coprocessor_util.h" #include "dynarmic/ir/cond.h" @@ -85,7 +85,7 @@ constexpr bool IsQuadExtReg(ExtReg reg) { } inline size_t RegNumber(Reg reg) { - ASSERT(reg != Reg::INVALID_REG); + assert(reg != Reg::INVALID_REG); return size_t(reg); } @@ -95,13 +95,13 @@ inline size_t RegNumber(ExtReg reg) { } else if (IsDoubleExtReg(reg)) { return size_t(reg) - size_t(ExtReg::D0); } - ASSERT(IsQuadExtReg(reg)); + assert(IsQuadExtReg(reg)); return size_t(reg) - size_t(ExtReg::Q0); } inline Reg operator+(Reg reg, size_t number) { const size_t new_reg = RegNumber(reg) + number; - ASSERT(new_reg <= 15); + assert(new_reg <= 15); return static_cast(new_reg); } @@ -109,7 +109,7 @@ inline Reg operator+(Reg reg, size_t number) { inline ExtReg operator+(ExtReg reg, size_t number) { const auto new_reg = static_cast(static_cast(reg) + number); - ASSERT((IsSingleExtReg(reg) && IsSingleExtReg(new_reg)) + assert((IsSingleExtReg(reg) && IsSingleExtReg(new_reg)) || (IsDoubleExtReg(reg) && IsDoubleExtReg(new_reg)) || (IsQuadExtReg(reg) && IsQuadExtReg(new_reg))); diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.cpp index 64e6bf2c7c..aa510a9be3 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.cpp @@ -10,7 +10,7 @@ #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/frontend/A32/a32_ir_emitter.h" @@ -21,7 +21,7 @@ namespace Dynarmic::A32 { bool CondCanContinue(const ConditionalState cond_state, const A32::IREmitter& ir) { - ASSERT(cond_state != ConditionalState::Break && "Should never happen."); + assert(cond_state != ConditionalState::Break && "Should never happen."); if (cond_state == ConditionalState::None) return true; @@ -32,7 +32,7 @@ bool CondCanContinue(const ConditionalState cond_state, const A32::IREmitter& ir } bool IsConditionPassed(TranslatorVisitor& v, IR::Cond cond) { - ASSERT(v.cond_state != ConditionalState::Break && "This should never happen. We requested a break but that wasn't honored."); + assert(v.cond_state != ConditionalState::Break && "This should never happen. We requested a break but that wasn't honored."); if (cond == IR::Cond::NV) { // NV conditional is obsolete diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp index f5d1830769..44d9e915a0 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp @@ -8,7 +8,7 @@ #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "common/assert.h" +#include #include "dynarmic/interface/A32/config.h" @@ -29,7 +29,7 @@ bool TranslatorVisitor::ThumbConditionPassed() { bool TranslatorVisitor::VFPConditionPassed(Cond cond) { if (ir.current_location.TFlag()) { - ASSERT(cond == Cond::AL); + assert(cond == Cond::AL); return true; } return ArmConditionPassed(cond); diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h index 82e919720e..9fa7716b44 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h @@ -8,7 +8,7 @@ #pragma once -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "dynarmic/frontend/A32/a32_ir_emitter.h" diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp index 6ccfe1e3bc..e2eda87fd4 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp @@ -8,7 +8,7 @@ #include -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp index 99b0cf2eb1..a0627473fd 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp @@ -6,7 +6,7 @@ * SPDX-License-Identifier: 0BSD */ -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp index 35f9888ce5..28d2ad804d 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp @@ -8,7 +8,7 @@ #include -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp index 4b653c0455..045e81735c 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp @@ -6,7 +6,7 @@ * SPDX-License-Identifier: 0BSD */ -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" @@ -130,7 +130,7 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, bool D, size_t imm6, size_t Vd, b } return v.ir.VectorUnsignedSaturatedNarrow(source_esize, wide_result); case Narrowing::SaturateToSigned: - ASSERT(signedness == Signedness::Signed); + assert(signedness == Signedness::Signed); return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result); } UNREACHABLE(); diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp index d7c667aecf..061b95cba6 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp @@ -95,7 +95,7 @@ bool TranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Re return UnpredictableInstruction(); } - ASSERT(!(!P && W) && "T form of instruction unimplemented"); + assert(!(!P && W) && "T form of instruction unimplemented"); if ((!P || W) && n == t) { return UnpredictableInstruction(); } @@ -126,7 +126,7 @@ bool TranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Re // LDR , [, #+/-]{!} // LDR , [], #+/- bool TranslatorVisitor::arm_LDR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<5> imm5, ShiftType shift, Reg m) { - ASSERT(!(!P && W) && "T form of instruction unimplemented"); + assert(!(!P && W) && "T form of instruction unimplemented"); if (m == Reg::PC) { return UnpredictableInstruction(); } @@ -184,7 +184,7 @@ bool TranslatorVisitor::arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, R return UnpredictableInstruction(); } - ASSERT(!(!P && W) && "T form of instruction unimplemented"); + assert(!(!P && W) && "T form of instruction unimplemented"); if ((!P || W) && n == t) { return UnpredictableInstruction(); } @@ -209,7 +209,7 @@ bool TranslatorVisitor::arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, R // LDRB , [, #+/-]{!} // LDRB , [], #+/- bool TranslatorVisitor::arm_LDRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<5> imm5, ShiftType shift, Reg m) { - ASSERT(!(!P && W) && "T form of instruction unimplemented"); + assert(!(!P && W) && "T form of instruction unimplemented"); if (t == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); } @@ -352,7 +352,7 @@ bool TranslatorVisitor::arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n, R // LDRH , [PC, #-/+] bool TranslatorVisitor::arm_LDRH_lit(Cond cond, bool P, bool U, bool W, Reg t, Imm<4> imm8a, Imm<4> imm8b) { - ASSERT(!(!P && W) && "T form of instruction unimplemented"); + assert(!(!P && W) && "T form of instruction unimplemented"); if (P == W) { return UnpredictableInstruction(); } @@ -382,7 +382,7 @@ bool TranslatorVisitor::arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, R return UnpredictableInstruction(); } - ASSERT(!(!P && W) && "T form of instruction unimplemented"); + assert(!(!P && W) && "T form of instruction unimplemented"); if ((!P || W) && n == t) { return UnpredictableInstruction(); } @@ -407,7 +407,7 @@ bool TranslatorVisitor::arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, R // LDRH , [, #+/-]{!} // LDRH , [], #+/- bool TranslatorVisitor::arm_LDRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) { - ASSERT(!(!P && W) && "T form of instruction unimplemented"); + assert(!(!P && W) && "T form of instruction unimplemented"); if (t == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); } @@ -456,7 +456,7 @@ bool TranslatorVisitor::arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n, return UnpredictableInstruction(); } - ASSERT(!(!P && W) && "T form of instruction unimplemented"); + assert(!(!P && W) && "T form of instruction unimplemented"); if ((!P || W) && n == t) { return UnpredictableInstruction(); } @@ -481,7 +481,7 @@ bool TranslatorVisitor::arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n, // LDRSB , [, #+/-]{!} // LDRSB , [], #+/- bool TranslatorVisitor::arm_LDRSB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) { - ASSERT(!(!P && W) && "T form of instruction unimplemented"); + assert(!(!P && W) && "T form of instruction unimplemented"); if (t == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); } @@ -529,7 +529,7 @@ bool TranslatorVisitor::arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n, return UnpredictableInstruction(); } - ASSERT(!(!P && W) && "T form of instruction unimplemented"); + assert(!(!P && W) && "T form of instruction unimplemented"); if ((!P || W) && n == t) { return UnpredictableInstruction(); } @@ -554,7 +554,7 @@ bool TranslatorVisitor::arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n, // LDRSH , [, #+/-]{!} // LDRSH , [], #+/- bool TranslatorVisitor::arm_LDRSH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) { - ASSERT(!(!P && W) && "T form of instruction unimplemented"); + assert(!(!P && W) && "T form of instruction unimplemented"); if (t == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); } diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp index 7a0640598c..711b4970bb 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp @@ -34,7 +34,7 @@ bool TranslatorVisitor::arm_MRS(Cond cond, Reg d) { // MSR , # bool TranslatorVisitor::arm_MSR_imm(Cond cond, unsigned mask, int rotate, Imm<8> imm8) { - ASSERT(mask != 0 && "Decode error"); + assert(mask != 0 && "Decode error"); if (!ArmConditionPassed(cond)) { return true; diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp index a8c75e22b9..fb63f4590a 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp @@ -687,7 +687,7 @@ bool TranslatorVisitor::thumb16_NOP() { // IT{{{}}} bool TranslatorVisitor::thumb16_IT(Imm<8> imm8) { - ASSERT((imm8.Bits<0, 3>() != 0b0000) && "Decode Error"); + assert((imm8.Bits<0, 3>() != 0b0000) && "Decode Error"); if (imm8.Bits<4, 7>() == 0b1111 || (imm8.Bits<4, 7>() == 0b1110 && mcl::bit::count_ones(imm8.Bits<0, 3>()) != 1)) { return UnpredictableInstruction(); } diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp index 2f4f2f7298..7d8a4046e2 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp @@ -1,4 +1,4 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project +// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project // SPDX-License-Identifier: GPL-3.0-or-later /* This file is part of the dynarmic project. @@ -23,7 +23,7 @@ bool TranslatorVisitor::thumb32_TST_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm } bool TranslatorVisitor::thumb32_AND_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) { - ASSERT(!(d == Reg::PC && S) && "Decode error"); + assert(!(d == Reg::PC && S) && "Decode error"); if ((d == Reg::PC && !S) || n == Reg::PC) { return UnpredictableInstruction(); } @@ -69,7 +69,7 @@ bool TranslatorVisitor::thumb32_MOV_imm(Imm<1> i, bool S, Imm<3> imm3, Reg d, Im } bool TranslatorVisitor::thumb32_ORR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) { - ASSERT(n != Reg::PC && "Decode error"); + assert(n != Reg::PC && "Decode error"); if (d == Reg::PC) { return UnpredictableInstruction(); } @@ -100,7 +100,7 @@ bool TranslatorVisitor::thumb32_MVN_imm(Imm<1> i, bool S, Imm<3> imm3, Reg d, Im } bool TranslatorVisitor::thumb32_ORN_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) { - ASSERT(n != Reg::PC && "Decode error"); + assert(n != Reg::PC && "Decode error"); if (d == Reg::PC) { return UnpredictableInstruction(); } @@ -128,7 +128,7 @@ bool TranslatorVisitor::thumb32_TEQ_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm } bool TranslatorVisitor::thumb32_EOR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) { - ASSERT(!(d == Reg::PC && S) && "Decode error"); + assert(!(d == Reg::PC && S) && "Decode error"); if ((d == Reg::PC && !S) || n == Reg::PC) { return UnpredictableInstruction(); } @@ -156,7 +156,7 @@ bool TranslatorVisitor::thumb32_CMN_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm } bool TranslatorVisitor::thumb32_ADD_imm_1(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) { - ASSERT(!(d == Reg::PC && S) && "Decode error"); + assert(!(d == Reg::PC && S) && "Decode error"); if ((d == Reg::PC && !S) || n == Reg::PC) { return UnpredictableInstruction(); } @@ -214,7 +214,7 @@ bool TranslatorVisitor::thumb32_CMP_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm } bool TranslatorVisitor::thumb32_SUB_imm_1(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) { - ASSERT(!(d == Reg::PC && S) && "Decode error"); + assert(!(d == Reg::PC && S) && "Decode error"); if ((d == Reg::PC && !S) || n == Reg::PC) { return UnpredictableInstruction(); } diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp index c0bb75962f..661dafa830 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp @@ -6,7 +6,7 @@ * SPDX-License-Identifier: 0BSD */ -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" @@ -17,7 +17,7 @@ namespace Dynarmic::A32 { using SaturationFunction = IR::ResultAndOverflow (IREmitter::*)(const IR::U32&, size_t); static bool Saturation(TranslatorVisitor& v, bool sh, Reg n, Reg d, Imm<5> shift_amount, size_t saturate_to, SaturationFunction sat_fn) { - ASSERT(!(sh && shift_amount == 0) && "Invalid decode"); + assert(!(sh && shift_amount == 0) && "Invalid decode"); if (d == Reg::PC || n == Reg::PC) { return v.UnpredictableInstruction(); diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp index f6b7cb5c87..cf5c39a3d7 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp @@ -1,4 +1,4 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project +// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project // SPDX-License-Identifier: GPL-3.0-or-later /* This file is part of the dynarmic project. @@ -23,7 +23,7 @@ bool TranslatorVisitor::thumb32_TST_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy } bool TranslatorVisitor::thumb32_AND_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) { - ASSERT(!(d == Reg::PC && S) && "Decode error"); + assert(!(d == Reg::PC && S) && "Decode error"); if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); @@ -67,7 +67,7 @@ bool TranslatorVisitor::thumb32_MOV_reg(bool S, Imm<3> imm3, Reg d, Imm<2> imm2, } bool TranslatorVisitor::thumb32_ORR_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) { - ASSERT(n != Reg::PC && "Decode error"); + assert(n != Reg::PC && "Decode error"); if (d == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); @@ -97,7 +97,7 @@ bool TranslatorVisitor::thumb32_MVN_reg(bool S, Imm<3> imm3, Reg d, Imm<2> imm2, } bool TranslatorVisitor::thumb32_ORN_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) { - ASSERT(n != Reg::PC && "Decode error"); + assert(n != Reg::PC && "Decode error"); if (d == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); @@ -125,7 +125,7 @@ bool TranslatorVisitor::thumb32_TEQ_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy } bool TranslatorVisitor::thumb32_EOR_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) { - ASSERT(!(d == Reg::PC && S) && "Decode error"); + assert(!(d == Reg::PC && S) && "Decode error"); if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); @@ -168,7 +168,7 @@ bool TranslatorVisitor::thumb32_CMN_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy } bool TranslatorVisitor::thumb32_ADD_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) { - ASSERT(!(d == Reg::PC && S) && "Decode error"); + assert(!(d == Reg::PC && S) && "Decode error"); if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); @@ -224,7 +224,7 @@ bool TranslatorVisitor::thumb32_CMP_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy } bool TranslatorVisitor::thumb32_SUB_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) { - ASSERT(!(d == Reg::PC && S) && "Decode error"); + assert(!(d == Reg::PC && S) && "Decode error"); if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/vfp.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/vfp.cpp index 794d247929..67e29c1237 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/vfp.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/impl/vfp.cpp @@ -1,4 +1,4 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project +// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project // SPDX-License-Identifier: GPL-3.0-or-later /* This file is part of the dynarmic project. @@ -1304,11 +1304,11 @@ bool TranslatorVisitor::vfp_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bo // VSTM{mode} {!}, bool TranslatorVisitor::vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) { if (!p && !u && !w) { - ASSERT(false && "Decode error"); + assert(false && "Decode error"); } if (p && !w) { - ASSERT(false && "Decode error"); + assert(false && "Decode error"); } if (p == u && w) { @@ -1356,11 +1356,11 @@ bool TranslatorVisitor::vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, R // VSTM{mode} {!}, bool TranslatorVisitor::vfp_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) { if (!p && !u && !w) { - ASSERT(false && "Decode error"); + assert(false && "Decode error"); } if (p && !w) { - ASSERT(false && "Decode error"); + assert(false && "Decode error"); } if (p == u && w) { @@ -1399,11 +1399,11 @@ bool TranslatorVisitor::vfp_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, R // VLDM{mode} {!}, bool TranslatorVisitor::vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) { if (!p && !u && !w) { - ASSERT(false && "Decode error"); + assert(false && "Decode error"); } if (p && !w) { - ASSERT(false && "Decode error"); + assert(false && "Decode error"); } if (p == u && w) { @@ -1449,11 +1449,11 @@ bool TranslatorVisitor::vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, R // VLDM{mode} {!}, bool TranslatorVisitor::vfp_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) { if (!p && !u && !w) { - ASSERT(false && "Decode error"); + assert(false && "Decode error"); } if (p && !w) { - ASSERT(false && "Decode error"); + assert(false && "Decode error"); } if (p == u && w) { diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_arm.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_arm.cpp index 3fd475d074..128a5d83bd 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_arm.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_arm.cpp @@ -6,7 +6,7 @@ * SPDX-License-Identifier: 0BSD */ -#include "common/assert.h" +#include #include "dynarmic/frontend/A32/a32_location_descriptor.h" #include "dynarmic/frontend/A32/a32_types.h" @@ -73,7 +73,7 @@ void TranslateArm(IR::Block& block, LocationDescriptor descriptor, TranslateCall } } } - ASSERT(block.HasTerminal() && "Terminal has not been set"); + assert(block.HasTerminal() && "Terminal has not been set"); block.SetEndLocation(visitor.ir.current_location); } diff --git a/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_thumb.cpp b/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_thumb.cpp index 332860a95c..9477aa7db9 100644 --- a/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_thumb.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A32/translate/translate_thumb.cpp @@ -8,7 +8,7 @@ #include -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "dynarmic/frontend/A32/a32_ir_emitter.h" @@ -172,7 +172,7 @@ void TranslateThumb(IR::Block& block, LocationDescriptor descriptor, TranslateCa } } } - ASSERT(block.HasTerminal() && "Terminal has not been set"); + assert(block.HasTerminal() && "Terminal has not been set"); block.SetEndLocation(visitor.ir.current_location); } diff --git a/src/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.h b/src/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.h index 21bd9250dd..74b4babcb4 100644 --- a/src/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.h +++ b/src/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.h @@ -11,7 +11,7 @@ #include #include "common/common_types.h" -#include "common/assert.h" +#include #include "dynarmic/frontend/A64/a64_location_descriptor.h" #include "dynarmic/frontend/A64/a64_types.h" diff --git a/src/dynarmic/src/dynarmic/frontend/A64/a64_types.h b/src/dynarmic/src/dynarmic/frontend/A64/a64_types.h index 55d82a740a..8819fd44d6 100644 --- a/src/dynarmic/src/dynarmic/frontend/A64/a64_types.h +++ b/src/dynarmic/src/dynarmic/frontend/A64/a64_types.h @@ -11,7 +11,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/ir/cond.h" @@ -114,14 +114,14 @@ constexpr size_t VecNumber(Vec vec) { inline Reg operator+(Reg reg, size_t number) { const size_t new_reg = RegNumber(reg) + number; - ASSERT(new_reg <= 31); + assert(new_reg <= 31); return static_cast(new_reg); } inline Vec operator+(Vec vec, size_t number) { const size_t new_vec = VecNumber(vec) + number; - ASSERT(new_vec <= 31); + assert(new_vec <= 31); return static_cast(new_vec); } diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.cpp index 4afce6bd29..fe1ee90b88 100644 --- a/src/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.cpp @@ -40,7 +40,7 @@ void Translate(IR::Block& block, LocationDescriptor descriptor, MemoryReadCodeFu if (single_step && should_continue) { visitor.ir.SetTerm(IR::Term::LinkBlock{*visitor.ir.current_location}); } - ASSERT(block.HasTerminal() && "Terminal has not been set"); + assert(block.HasTerminal() && "Terminal has not been set"); block.SetEndLocation(*visitor.ir.current_location); } diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp index f3ecd7c604..60c8a8e2ed 100644 --- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp @@ -170,8 +170,8 @@ void TranslatorVisitor::V_scalar(size_t bitsize, Vec vec, IR::UAnyU128 value) { } IR::U128 TranslatorVisitor::Vpart(size_t bitsize, Vec vec, size_t part) { - ASSERT(part == 0 || part == 1); - ASSERT(bitsize == 64); + assert(part == 0 || part == 1); + assert(bitsize == 64); if (part == 0) { return V(64, vec); } @@ -179,33 +179,33 @@ IR::U128 TranslatorVisitor::Vpart(size_t bitsize, Vec vec, size_t part) { } void TranslatorVisitor::Vpart(size_t bitsize, Vec vec, size_t part, IR::U128 value) { - ASSERT(part == 0 || part == 1); + assert(part == 0 || part == 1); if (part == 0) { - ASSERT(bitsize == 64); + assert(bitsize == 64); V(128, vec, ir.VectorZeroExtend(bitsize, value)); } else { - ASSERT(bitsize == 64); + assert(bitsize == 64); V(128, vec, ir.VectorInterleaveLower(64, V(128, vec), value)); } } IR::UAny TranslatorVisitor::Vpart_scalar(size_t bitsize, Vec vec, size_t part) { - ASSERT(part == 0 || part == 1); + assert(part == 0 || part == 1); if (part == 0) { - ASSERT(bitsize == 8 || bitsize == 16 || bitsize == 32 || bitsize == 64); + assert(bitsize == 8 || bitsize == 16 || bitsize == 32 || bitsize == 64); } else { - ASSERT(bitsize == 64); + assert(bitsize == 64); } return ir.VectorGetElement(bitsize, V(128, vec), part); } void TranslatorVisitor::Vpart_scalar(size_t bitsize, Vec vec, size_t part, IR::UAny value) { - ASSERT(part == 0 || part == 1); + assert(part == 0 || part == 1); if (part == 0) { - ASSERT(bitsize == 8 || bitsize == 16 || bitsize == 32 || bitsize == 64); + assert(bitsize == 8 || bitsize == 16 || bitsize == 32 || bitsize == 64); V(128, vec, ir.ZeroExtendToQuad(value)); } else { - ASSERT(bitsize == 64); + assert(bitsize == 64); V(128, vec, ir.VectorSetElement(64, V(128, vec), 1, value)); } } @@ -315,8 +315,8 @@ IR::U32U64 TranslatorVisitor::ShiftReg(size_t bitsize, Reg reg, Imm<2> shift, IR } IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, u8 shift) { - ASSERT(shift <= 4); - ASSERT(bitsize == 32 || bitsize == 64); + assert(shift <= 4); + assert(bitsize == 32 || bitsize == 64); IR::UAny val = X(bitsize, reg); size_t len; IR::U32U64 extended; diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_multiple_structures.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_multiple_structures.cpp index 77c57a9659..61ad6422e6 100644 --- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_multiple_structures.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_multiple_structures.cpp @@ -1,3 +1,6 @@ +// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project +// SPDX-License-Identifier: GPL-3.0-or-later + /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -48,7 +51,7 @@ static bool SharedDecodeAndOperation(TranslatorVisitor& v, bool wback, IR::MemOp default: return v.UnallocatedEncoding(); } - ASSERT(rpt == 1 || selem == 1); + assert(rpt == 1 || selem == 1); if ((size == 0b11 && !Q) && selem != 1) { return v.ReservedValue(); diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp index d939c45f2c..b803649e3d 100644 --- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp @@ -1,3 +1,6 @@ +// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project +// SPDX-License-Identifier: GPL-3.0-or-later + /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -18,10 +21,10 @@ static bool LoadStoreRegisterImmediate(TranslatorVisitor& v, bool wback, bool po signed_ = false; } else if (size == 0b11) { memop = IR::MemOp::PREFETCH; - ASSERT(!opc.Bit<0>()); + assert(!opc.Bit<0>()); } else { memop = IR::MemOp::LOAD; - ASSERT(!(size == 0b10 && opc.Bit<0>() == 1)); + assert(!(size == 0b10 && opc.Bit<0>() == 1)); regsize = opc.Bit<0>() ? 32 : 64; signed_ = true; } diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp index 332eb35ebe..1d8121f87d 100644 --- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp @@ -198,7 +198,7 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, } return v.ir.VectorUnsignedSaturatedNarrow(source_esize, wide_result); case Narrowing::SaturateToSigned: - ASSERT(SignednessSSSBI == SignednessSSSBI::Signed); + assert(SignednessSSSBI == SignednessSSSBI::Signed); return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result); } UNREACHABLE(); diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp index bb0c6fc175..89bf3fdba2 100644 --- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp @@ -1,4 +1,4 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project +// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project // SPDX-License-Identifier: GPL-3.0-or-later /* This file is part of the dynarmic project. @@ -73,7 +73,7 @@ bool MultiplyByElementHalfPrecision(TranslatorVisitor& v, Imm<1> L, Imm<1> M, Im // TODO: Currently we don't implement half-precision paths // for regular multiplication and extended multiplication. - ASSERT(extra_behavior != ExtraBehavior::None + assert(extra_behavior != ExtraBehavior::None && extra_behavior != ExtraBehavior::MultiplyExtended); if (extra_behavior == ExtraBehavior::Subtract) { operand1 = v.ir.FPNeg(operand1); diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp index 33debd1062..2abb2c04c3 100644 --- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp @@ -127,7 +127,7 @@ bool ShiftRightNarrowingSSBI(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> i } return v.ir.VectorUnsignedSaturatedNarrow(source_esize, wide_result); case NarrowingSSBI::SaturateToSigned: - ASSERT(SignednessSSBI == SignednessSSBI::Signed); + assert(SignednessSSBI == SignednessSSBI::Signed); return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result); } UNREACHABLE(); diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same_extra.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same_extra.cpp index 91ade93f4b..4a3353125f 100644 --- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same_extra.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same_extra.cpp @@ -66,7 +66,7 @@ bool TranslatorVisitor::FCMLA_vec(bool Q, Imm<2> size, Vec Vm, Imm<2> rot, Vec V const size_t esize = 8U << size.ZeroExtend(); // TODO: Currently we don't support half-precision floating point - ASSERT(esize != 16); + assert(esize != 16); const size_t datasize = Q ? 128 : 64; const size_t num_elements = datasize / esize; @@ -135,7 +135,7 @@ bool TranslatorVisitor::FCADD_vec(bool Q, Imm<2> size, Vec Vm, Imm<1> rot, Vec V const size_t esize = 8U << size.ZeroExtend(); // TODO: Currently we don't support half-precision floating point - ASSERT(esize != 16); + assert(esize != 16); const size_t datasize = Q ? 128 : 64; const size_t num_elements = datasize / esize; diff --git a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp index da11b51d84..d0d721bc21 100644 --- a/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp +++ b/src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp @@ -8,7 +8,7 @@ #include -#include "common/assert.h" +#include #include "dynarmic/frontend/A64/translate/impl/impl.h" @@ -223,7 +223,7 @@ bool TranslatorVisitor::FCMLA_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4 const size_t esize = 8U << size.ZeroExtend(); // TODO: We don't support the half-precision floating point variant yet. - ASSERT(esize != 16); + assert(esize != 16); const size_t index = [=] { if (size == 0b01) { diff --git a/src/dynarmic/src/dynarmic/frontend/decoder/decoder_detail.h b/src/dynarmic/src/dynarmic/frontend/decoder/decoder_detail.h index c22e585c26..6e9aa27e9b 100644 --- a/src/dynarmic/src/dynarmic/frontend/decoder/decoder_detail.h +++ b/src/dynarmic/src/dynarmic/frontend/decoder/decoder_detail.h @@ -12,7 +12,7 @@ #include #include -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "dynarmic/mcl/function_info.hpp" @@ -99,9 +99,9 @@ struct detail { shifts[arg_index] = bit_position; } } -#if !defined(DYNARMIC_IGNORE_ASSERTS) && !defined(__ANDROID__) +#if !defined(DYNARMIC_IGNORE_assertS) && !defined(__ANDROID__) // Avoids a MSVC ICE, and avoids Android NDK issue. - ASSERT(std::all_of(masks.begin(), masks.end(), [](auto m) { return m != 0; })); + assert(std::all_of(masks.begin(), masks.end(), [](auto m) { return m != 0; })); #endif return std::make_tuple(masks, shifts); } diff --git a/src/dynarmic/src/dynarmic/frontend/decoder/matcher.h b/src/dynarmic/src/dynarmic/frontend/decoder/matcher.h index 194f646ed2..2eb7dae759 100644 --- a/src/dynarmic/src/dynarmic/frontend/decoder/matcher.h +++ b/src/dynarmic/src/dynarmic/frontend/decoder/matcher.h @@ -10,7 +10,7 @@ #include -#include "common/assert.h" +#include namespace Dynarmic::Decoder { @@ -51,7 +51,7 @@ public: /// @param v The visitor to use /// @param instruction The instruction to decode. inline handler_return_type call(Visitor& v, opcode_type instruction) const noexcept { - ASSERT(Matches(instruction)); + assert(Matches(instruction)); return fn(v, instruction); } diff --git a/src/dynarmic/src/dynarmic/frontend/imm.cpp b/src/dynarmic/src/dynarmic/frontend/imm.cpp index 7afc3ae403..c3c531a619 100644 --- a/src/dynarmic/src/dynarmic/frontend/imm.cpp +++ b/src/dynarmic/src/dynarmic/frontend/imm.cpp @@ -8,7 +8,7 @@ #include "dynarmic/frontend/imm.h" -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "common/common_types.h" diff --git a/src/dynarmic/src/dynarmic/frontend/imm.h b/src/dynarmic/src/dynarmic/frontend/imm.h index 56fbcbda0e..5eb4ca6922 100644 --- a/src/dynarmic/src/dynarmic/frontend/imm.h +++ b/src/dynarmic/src/dynarmic/frontend/imm.h @@ -10,7 +10,7 @@ #include -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "common/common_types.h" @@ -29,7 +29,7 @@ public: explicit Imm(u32 value) : value(value) { - ASSERT((mcl::bit::get_bits<0, bit_size - 1>(value) == value) && "More bits in value than expected"); + assert((mcl::bit::get_bits<0, bit_size - 1>(value) == value) && "More bits in value than expected"); } template diff --git a/src/dynarmic/src/dynarmic/ir/basic_block.cpp b/src/dynarmic/src/dynarmic/ir/basic_block.cpp index 284f115328..70f3cfeb4f 100644 --- a/src/dynarmic/src/dynarmic/ir/basic_block.cpp +++ b/src/dynarmic/src/dynarmic/ir/basic_block.cpp @@ -14,7 +14,7 @@ #include #include -#include "common/assert.h" +#include #include "dynarmic/frontend/A32/a32_types.h" #include "dynarmic/frontend/A64/a64_types.h" #include "dynarmic/ir/cond.h" @@ -49,7 +49,7 @@ Block::iterator Block::PrependNewInst(iterator insertion_point, Opcode opcode, s pooled_inst.back().emplace_back(opcode); inst = &pooled_inst.back()[pooled_inst.back().size() - 1]; } - DEBUG_ASSERT(args.size() == inst->NumArgs()); + assert(args.size() == inst->NumArgs()); std::for_each(args.begin(), args.end(), [&inst, index = size_t(0)](const auto& arg) mutable { inst->SetArg(index, arg); index++; @@ -69,7 +69,7 @@ void Block::Reset(LocationDescriptor location_) noexcept { terminal = Term::Invalid{}; cond_failed_cycle_count = 0; cycle_count = 0; - ASSERT(instructions.size() == 0); + assert(instructions.size() == 0); } static std::string TerminalToString(const Terminal& terminal_variant) noexcept { diff --git a/src/dynarmic/src/dynarmic/ir/basic_block.h b/src/dynarmic/src/dynarmic/ir/basic_block.h index 1518903d2a..90599ef8a3 100644 --- a/src/dynarmic/src/dynarmic/ir/basic_block.h +++ b/src/dynarmic/src/dynarmic/ir/basic_block.h @@ -119,12 +119,12 @@ public: } /// Sets the terminal instruction for this basic block. inline void SetTerminal(Terminal term) noexcept { - ASSERT(!HasTerminal() && "Terminal has already been set."); + assert(!HasTerminal() && "Terminal has already been set."); terminal = std::move(term); } /// Replaces the terminal instruction for this basic block. inline void ReplaceTerminal(Terminal term) noexcept { - ASSERT(HasTerminal() && "Terminal has not been set."); + assert(HasTerminal() && "Terminal has not been set."); terminal = std::move(term); } /// Determines whether or not this basic block has a terminal instruction. diff --git a/src/dynarmic/src/dynarmic/ir/ir_emitter.h b/src/dynarmic/src/dynarmic/ir/ir_emitter.h index c035af2708..05eb5c4ce3 100644 --- a/src/dynarmic/src/dynarmic/ir/ir_emitter.h +++ b/src/dynarmic/src/dynarmic/ir/ir_emitter.h @@ -11,7 +11,7 @@ #include #include "common/common_types.h" -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "dynarmic/ir/opcodes.h" @@ -118,7 +118,7 @@ public: } return LeastSignificantWord(value); case 64: - ASSERT(value.GetType() == Type::U64); + assert(value.GetType() == Type::U64); return value; } UNREACHABLE(); @@ -189,7 +189,7 @@ public: } U32U64 ConditionalSelect(Cond cond, const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); if (a.GetType() == Type::U32) { return Inst(Opcode::ConditionalSelect32, Value{cond}, a, b); } else { @@ -272,7 +272,7 @@ public: } U32U64 LogicalShiftLeftMasked(const U32U64& value_in, const U32U64& shift_amount) { - ASSERT(value_in.GetType() == shift_amount.GetType()); + assert(value_in.GetType() == shift_amount.GetType()); if (value_in.GetType() == Type::U32) { return Inst(Opcode::LogicalShiftLeftMasked32, value_in, shift_amount); } else { @@ -281,7 +281,7 @@ public: } U32U64 LogicalShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount) { - ASSERT(value_in.GetType() == shift_amount.GetType()); + assert(value_in.GetType() == shift_amount.GetType()); if (value_in.GetType() == Type::U32) { return Inst(Opcode::LogicalShiftRightMasked32, value_in, shift_amount); } else { @@ -290,7 +290,7 @@ public: } U32U64 ArithmeticShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount) { - ASSERT(value_in.GetType() == shift_amount.GetType()); + assert(value_in.GetType() == shift_amount.GetType()); if (value_in.GetType() == Type::U32) { return Inst(Opcode::ArithmeticShiftRightMasked32, value_in, shift_amount); } else { @@ -299,7 +299,7 @@ public: } U32U64 RotateRightMasked(const U32U64& value_in, const U32U64& shift_amount) { - ASSERT(value_in.GetType() == shift_amount.GetType()); + assert(value_in.GetType() == shift_amount.GetType()); if (value_in.GetType() == Type::U32) { return Inst(Opcode::RotateRightMasked32, value_in, shift_amount); } else { @@ -308,7 +308,7 @@ public: } U32U64 AddWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); if (a.GetType() == Type::U32) { return Inst(Opcode::Add32, a, b, carry_in); } else { @@ -317,7 +317,7 @@ public: } U32U64 Add(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); if (a.GetType() == Type::U32) { return Inst(Opcode::Add32, a, b, Imm1(0)); } else { @@ -326,7 +326,7 @@ public: } U32U64 SubWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); if (a.GetType() == Type::U32) { return Inst(Opcode::Sub32, a, b, carry_in); } else { @@ -335,7 +335,7 @@ public: } U32U64 Sub(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); if (a.GetType() == Type::U32) { return Inst(Opcode::Sub32, a, b, Imm1(1)); } else { @@ -376,7 +376,7 @@ public: } U32U64 And(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); if (a.GetType() == Type::U32) { return Inst(Opcode::And32, a, b); } else { @@ -385,7 +385,7 @@ public: } U32U64 AndNot(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); if (a.GetType() == Type::U32) { return Inst(Opcode::AndNot32, a, b); } else { @@ -394,7 +394,7 @@ public: } U32U64 Eor(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); if (a.GetType() == Type::U32) { return Inst(Opcode::Eor32, a, b); } else { @@ -403,7 +403,7 @@ public: } U32U64 Or(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); if (a.GetType() == Type::U32) { return Inst(Opcode::Or32, a, b); } else { @@ -547,11 +547,11 @@ public: U32U64 ReplicateBit(const U32U64& a, u8 bit) { if (a.GetType() == IR::Type::U32) { - ASSERT(bit < 32); + assert(bit < 32); return Inst(Opcode::ReplicateBit32, a, Imm8(bit)); } - ASSERT(bit < 64); + assert(bit < 64); return Inst(Opcode::ReplicateBit64, a, Imm8(bit)); } @@ -600,21 +600,21 @@ public: } ResultAndOverflow SignedSaturation(const U32& a, size_t bit_size_to_saturate_to) { - ASSERT(bit_size_to_saturate_to >= 1 && bit_size_to_saturate_to <= 32); + assert(bit_size_to_saturate_to >= 1 && bit_size_to_saturate_to <= 32); const auto result = Inst(Opcode::SignedSaturation, a, Imm8(static_cast(bit_size_to_saturate_to))); const auto overflow = Inst(Opcode::GetOverflowFromOp, result); return {result, overflow}; } ResultAndOverflow UnsignedSaturation(const U32& a, size_t bit_size_to_saturate_to) { - ASSERT(bit_size_to_saturate_to <= 31); + assert(bit_size_to_saturate_to <= 31); const auto result = Inst(Opcode::UnsignedSaturation, a, Imm8(static_cast(bit_size_to_saturate_to))); const auto overflow = Inst(Opcode::GetOverflowFromOp, result); return {result, overflow}; } UAny SignedSaturatedAdd(const UAny& a, const UAny& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); const auto result = [&]() -> IR::UAny { switch (a.GetType()) { case IR::Type::U8: @@ -633,7 +633,7 @@ public: } UAny SignedSaturatedDoublingMultiplyReturnHigh(const UAny& a, const UAny& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); const auto result = [&]() -> IR::UAny { switch (a.GetType()) { case IR::Type::U16: @@ -648,7 +648,7 @@ public: } UAny SignedSaturatedSub(const UAny& a, const UAny& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); const auto result = [&]() -> IR::UAny { switch (a.GetType()) { case IR::Type::U8: @@ -667,7 +667,7 @@ public: } UAny UnsignedSaturatedAdd(const UAny& a, const UAny& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); const auto result = [&]() -> IR::UAny { switch (a.GetType()) { case IR::Type::U8: @@ -686,7 +686,7 @@ public: } UAny UnsignedSaturatedSub(const UAny& a, const UAny& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); const auto result = [&]() -> IR::UAny { switch (a.GetType()) { case IR::Type::U8: @@ -989,7 +989,7 @@ public: } UAny VectorGetElement(size_t esize, const U128& a, size_t index) { - ASSERT(esize * index < 128 && "Invalid index"); + assert(esize * index < 128 && "Invalid index"); switch (esize) { case 8: return Inst(Opcode::VectorGetElement8, a, Imm8(static_cast(index))); @@ -1005,7 +1005,7 @@ public: } U128 VectorSetElement(size_t esize, const U128& a, size_t index, const IR::UAny& elem) { - ASSERT(esize * index < 128 && "Invalid index"); + assert(esize * index < 128 && "Invalid index"); switch (esize) { case 8: return Inst(Opcode::VectorSetElement8, a, Imm8(static_cast(index)), elem); @@ -1111,7 +1111,7 @@ public: } U128 VectorBroadcastElementLower(size_t esize, const U128& a, size_t index) { - ASSERT(esize * index < 128 && "Invalid index"); + assert(esize * index < 128 && "Invalid index"); switch (esize) { case 8: return Inst(Opcode::VectorBroadcastElementLower8, a, u8(index)); @@ -1124,7 +1124,7 @@ public: } U128 VectorBroadcastElement(size_t esize, const U128& a, size_t index) { - ASSERT(esize * index < 128 && "Invalid index"); + assert(esize * index < 128 && "Invalid index"); switch (esize) { case 8: return Inst(Opcode::VectorBroadcastElement8, a, u8(index)); @@ -1223,12 +1223,12 @@ public: } U128 VectorExtract(const U128& a, const U128& b, size_t position) { - ASSERT(position <= 128); + assert(position <= 128); return Inst(Opcode::VectorExtract, a, b, Imm8(static_cast(position))); } U128 VectorExtractLower(const U128& a, const U128& b, size_t position) { - ASSERT(position <= 64); + assert(position <= 64); return Inst(Opcode::VectorExtractLower, a, b, Imm8(static_cast(position))); } @@ -1732,7 +1732,7 @@ public: } U128 VectorRotateLeft(size_t esize, const U128& a, u8 amount) { - ASSERT(amount < esize); + assert(amount < esize); if (amount == 0) { return a; @@ -1743,7 +1743,7 @@ public: } U128 VectorRotateRight(size_t esize, const U128& a, u8 amount) { - ASSERT(amount < esize); + assert(amount < esize); if (amount == 0) { return a; @@ -1754,7 +1754,7 @@ public: } U128 VectorRotateWholeVectorRight(const U128& a, u8 amount) { - ASSERT(amount % 32 == 0); + assert(amount % 32 == 0); return Inst(Opcode::VectorRotateWholeVectorRight, a, Imm8(amount)); } @@ -1970,7 +1970,7 @@ public: } U128 VectorSignedSaturatedShiftLeftUnsigned(size_t esize, const U128& a, u8 shift_amount) { - ASSERT(shift_amount < esize); + assert(shift_amount < esize); switch (esize) { case 8: return Inst(Opcode::VectorSignedSaturatedShiftLeftUnsigned8, a, Imm8(shift_amount)); @@ -1999,24 +1999,24 @@ public: } Table VectorTable(std::vector values) { - ASSERT(values.size() >= 1 && values.size() <= 4); + assert(values.size() >= 1 && values.size() <= 4); values.resize(4); return Inst(Opcode::VectorTable, values[0], values[1], values[2], values[3]); } Table VectorTable(std::vector values) { - ASSERT(values.size() >= 1 && values.size() <= 4); + assert(values.size() >= 1 && values.size() <= 4); values.resize(4); return Inst
(Opcode::VectorTable, values[0], values[1], values[2], values[3]); } U64 VectorTableLookup(const U64& defaults, const Table& table, const U64& indices) { - ASSERT(table.GetInst()->GetArg(0).GetType() == Type::U64); + assert(table.GetInst()->GetArg(0).GetType() == Type::U64); return Inst(Opcode::VectorTableLookup64, defaults, table, indices); } U128 VectorTableLookup(const U128& defaults, const Table& table, const U128& indices) { - ASSERT(table.GetInst()->GetArg(0).GetType() == Type::U128); + assert(table.GetInst()->GetArg(0).GetType() == Type::U128); return Inst(Opcode::VectorTableLookup128, defaults, table, indices); } @@ -2130,7 +2130,7 @@ public: } U32U64 FPAdd(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); switch (a.GetType()) { case Type::U32: @@ -2143,7 +2143,7 @@ public: } NZCV FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); const IR::U1 exc_on_qnan_imm = Imm1(exc_on_qnan); @@ -2158,7 +2158,7 @@ public: } U32U64 FPDiv(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); switch (a.GetType()) { case Type::U32: @@ -2171,7 +2171,7 @@ public: } U32U64 FPMax(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); switch (a.GetType()) { case Type::U32: @@ -2184,7 +2184,7 @@ public: } U32U64 FPMaxNumeric(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); switch (a.GetType()) { case Type::U32: @@ -2197,7 +2197,7 @@ public: } U32U64 FPMin(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); switch (a.GetType()) { case Type::U32: @@ -2210,7 +2210,7 @@ public: } U32U64 FPMinNumeric(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); switch (a.GetType()) { case Type::U32: @@ -2223,7 +2223,7 @@ public: } U32U64 FPMul(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); switch (a.GetType()) { case Type::U32: @@ -2236,7 +2236,7 @@ public: } U16U32U64 FPMulAdd(const U16U32U64& a, const U16U32U64& b, const U16U32U64& c) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); switch (a.GetType()) { case Type::U16: @@ -2251,7 +2251,7 @@ public: } U16U32U64 FPMulSub(const U16U32U64& a, const U16U32U64& b, const U16U32U64& c) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); switch (a.GetType()) { case Type::U16: @@ -2266,7 +2266,7 @@ public: } U32U64 FPMulX(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); switch (a.GetType()) { case Type::U32: @@ -2318,7 +2318,7 @@ public: } U16U32U64 FPRecipStepFused(const U16U32U64& a, const U16U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); switch (a.GetType()) { case Type::U16: @@ -2362,7 +2362,7 @@ public: } U16U32U64 FPRSqrtStepFused(const U16U32U64& a, const U16U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); switch (a.GetType()) { case Type::U16: @@ -2388,7 +2388,7 @@ public: } U32U64 FPSub(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); + assert(a.GetType() == b.GetType()); switch (a.GetType()) { case Type::U32: @@ -2425,7 +2425,7 @@ public: } U16 FPToFixedS16(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= 16); + assert(fbits <= 16); const U8 fbits_imm = Imm8(static_cast(fbits)); const U8 rounding_imm = Imm8(static_cast(rounding)); @@ -2443,7 +2443,7 @@ public: } U32 FPToFixedS32(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= 32); + assert(fbits <= 32); const U8 fbits_imm = Imm8(static_cast(fbits)); const U8 rounding_imm = Imm8(static_cast(rounding)); @@ -2461,7 +2461,7 @@ public: } U64 FPToFixedS64(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= 64); + assert(fbits <= 64); const U8 fbits_imm = Imm8(static_cast(fbits)); const U8 rounding_imm = Imm8(static_cast(rounding)); @@ -2479,7 +2479,7 @@ public: } U16 FPToFixedU16(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= 16); + assert(fbits <= 16); const U8 fbits_imm = Imm8(static_cast(fbits)); const U8 rounding_imm = Imm8(static_cast(rounding)); @@ -2497,7 +2497,7 @@ public: } U32 FPToFixedU32(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= 32); + assert(fbits <= 32); const U8 fbits_imm = Imm8(static_cast(fbits)); const U8 rounding_imm = Imm8(static_cast(rounding)); @@ -2515,7 +2515,7 @@ public: } U64 FPToFixedU64(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= 64); + assert(fbits <= 64); const U8 fbits_imm = Imm8(static_cast(fbits)); const U8 rounding_imm = Imm8(static_cast(rounding)); @@ -2533,7 +2533,7 @@ public: } U32 FPSignedFixedToSingle(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); + assert(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); const IR::U8 fbits_imm = Imm8(static_cast(fbits)); const IR::U8 rounding_imm = Imm8(static_cast(rounding)); @@ -2551,7 +2551,7 @@ public: } U32 FPUnsignedFixedToSingle(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); + assert(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); const IR::U8 fbits_imm = Imm8(static_cast(fbits)); const IR::U8 rounding_imm = Imm8(static_cast(rounding)); @@ -2569,7 +2569,7 @@ public: } U64 FPSignedFixedToDouble(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); + assert(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); const IR::U8 fbits_imm = Imm8(static_cast(fbits)); const IR::U8 rounding_imm = Imm8(static_cast(rounding)); @@ -2587,7 +2587,7 @@ public: } U64 FPUnsignedFixedToDouble(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); + assert(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); const IR::U8 fbits_imm = Imm8(static_cast(fbits)); const IR::U8 rounding_imm = Imm8(static_cast(rounding)); @@ -2649,12 +2649,12 @@ public: } U128 FPVectorFromHalf(size_t esize, const U128& a, FP::RoundingMode rounding, bool fpcr_controlled = true) { - ASSERT(esize == 32); + assert(esize == 32); return Inst(Opcode::FPVectorFromHalf32, a, Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); } U128 FPVectorFromSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) { - ASSERT(fbits <= esize); + assert(fbits <= esize); switch (esize) { case 32: return Inst(Opcode::FPVectorFromSignedFixed32, a, Imm8(static_cast(fbits)), Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); @@ -2665,7 +2665,7 @@ public: } U128 FPVectorFromUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) { - ASSERT(fbits <= esize); + assert(fbits <= esize); switch (esize) { case 32: return Inst(Opcode::FPVectorFromUnsignedFixed32, a, Imm8(static_cast(fbits)), Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); @@ -2883,12 +2883,12 @@ public: } U128 FPVectorToHalf(size_t esize, const U128& a, FP::RoundingMode rounding, bool fpcr_controlled = true) { - ASSERT(esize == 32); + assert(esize == 32); return Inst(Opcode::FPVectorToHalf32, a, Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); } U128 FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) { - ASSERT(fbits <= esize); + assert(fbits <= esize); const U8 fbits_imm = Imm8(static_cast(fbits)); const U8 rounding_imm = Imm8(static_cast(rounding)); @@ -2906,7 +2906,7 @@ public: } U128 FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) { - ASSERT(fbits <= esize); + assert(fbits <= esize); const U8 fbits_imm = Imm8(static_cast(fbits)); const U8 rounding_imm = Imm8(static_cast(rounding)); diff --git a/src/dynarmic/src/dynarmic/ir/microinstruction.cpp b/src/dynarmic/src/dynarmic/ir/microinstruction.cpp index b5541470cd..890fe3cffa 100644 --- a/src/dynarmic/src/dynarmic/ir/microinstruction.cpp +++ b/src/dynarmic/src/dynarmic/ir/microinstruction.cpp @@ -10,7 +10,7 @@ #include -#include "common/assert.h" +#include #include "dynarmic/ir/opcodes.h" #include "dynarmic/ir/type.h" @@ -27,7 +27,7 @@ Inst* Inst::GetAssociatedPseudoOperation(Opcode opcode) { Inst* pseudoop = next_pseudoop; while (pseudoop) { if (pseudoop->GetOpcode() == opcode) { - ASSERT(pseudoop->GetArg(0).GetInst() == this); + assert(pseudoop->GetArg(0).GetInst() == this); return pseudoop; } pseudoop = pseudoop->next_pseudoop; @@ -42,10 +42,10 @@ Type Inst::GetType() const { } void Inst::SetArg(size_t index, Value value) noexcept { - DEBUG_ASSERT(index < GetNumArgsOf(op)); - DEBUG_ASSERT(AreTypesCompatible(value.GetType(), GetArgTypeOf(op, index))); - //DEBUG_ASSERT(index < GetNumArgsOf(op) && "Inst::SetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op)); - //DEBUG_ASSERT(AreTypesCompatible(value.GetType(), GetArgTypeOf(op, index)) && "Inst::SetArg: type {} of argument {} not compatible with operation {} ({})", value.GetType(), index, op, GetArgTypeOf(op, index)); + assert(index < GetNumArgsOf(op)); + assert(AreTypesCompatible(value.GetType(), GetArgTypeOf(op, index))); + //assert(index < GetNumArgsOf(op) && "Inst::SetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op)); + //assert(AreTypesCompatible(value.GetType(), GetArgTypeOf(op, index)) && "Inst::SetArg: type {} of argument {} not compatible with operation {} ({})", value.GetType(), index, op, GetArgTypeOf(op, index)); if (!args[index].IsImmediate()) { UndoUse(args[index]); } @@ -81,13 +81,13 @@ void Inst::Use(const Value& value) { if (IsAPseudoOperation(op)) { if (op == Opcode::GetNZCVFromOp) { - ASSERT(MayGetNZCVFromOp(value.GetInst()->GetOpcode()) && "This value doesn't support the GetNZCVFromOp pseduo-op"); + assert(MayGetNZCVFromOp(value.GetInst()->GetOpcode()) && "This value doesn't support the GetNZCVFromOp pseduo-op"); } Inst* insert_point = value.GetInst(); while (insert_point->next_pseudoop) { insert_point = insert_point->next_pseudoop; - DEBUG_ASSERT(insert_point->GetArg(0).GetInst() == value.GetInst()); + assert(insert_point->GetArg(0).GetInst() == value.GetInst()); } insert_point->next_pseudoop = this; } @@ -100,7 +100,7 @@ void Inst::UndoUse(const Value& value) { Inst* insert_point = value.GetInst(); while (insert_point->next_pseudoop != this) { insert_point = insert_point->next_pseudoop; - DEBUG_ASSERT(insert_point->GetArg(0).GetInst() == value.GetInst()); + assert(insert_point->GetArg(0).GetInst() == value.GetInst()); } insert_point->next_pseudoop = next_pseudoop; next_pseudoop = nullptr; diff --git a/src/dynarmic/src/dynarmic/ir/microinstruction.h b/src/dynarmic/src/dynarmic/ir/microinstruction.h index 76ca3b389d..b85e58b4e3 100644 --- a/src/dynarmic/src/dynarmic/ir/microinstruction.h +++ b/src/dynarmic/src/dynarmic/ir/microinstruction.h @@ -53,10 +53,10 @@ public: } inline Value GetArg(size_t index) const noexcept { - DEBUG_ASSERT(index < GetNumArgsOf(op)); - DEBUG_ASSERT(!args[index].IsEmpty() || GetArgTypeOf(op, index) == IR::Type::Opaque); - //DEBUG_ASSERT(index < GetNumArgsOf(op) && "Inst::GetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op)); - //DEBUG_ASSERT(!args[index].IsEmpty() || GetArgTypeOf(op, index) == IR::Type::Opaque && "Inst::GetArg: index {} is empty", index, args[index].GetType()); + assert(index < GetNumArgsOf(op)); + assert(!args[index].IsEmpty() || GetArgTypeOf(op, index) == IR::Type::Opaque); + //assert(index < GetNumArgsOf(op) && "Inst::GetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op)); + //assert(!args[index].IsEmpty() || GetArgTypeOf(op, index) == IR::Type::Opaque && "Inst::GetArg: index {} is empty", index, args[index].GetType()); return args[index]; } void SetArg(size_t index, Value value) noexcept; diff --git a/src/dynarmic/src/dynarmic/ir/opt_passes.cpp b/src/dynarmic/src/dynarmic/ir/opt_passes.cpp index 999d4c49bc..ff7bd71c95 100644 --- a/src/dynarmic/src/dynarmic/ir/opt_passes.cpp +++ b/src/dynarmic/src/dynarmic/ir/opt_passes.cpp @@ -323,7 +323,7 @@ static void RegisterPass(IR::Block& block) { switch (opcode) { case IR::Opcode::A32GetRegister: { const A32::Reg reg = inst->GetArg(0).GetA32RegRef(); - ASSERT(reg != A32::Reg::PC); + assert(reg != A32::Reg::PC); const size_t reg_index = size_t(reg); do_get(reg_info[reg_index], inst); break; @@ -383,7 +383,7 @@ static void RegisterPass(IR::Block& block) { }, inst); } else { - DEBUG_ASSERT(A32::IsQuadExtReg(reg)); + assert(A32::IsQuadExtReg(reg)); do_ext_get(ExtValueType::VectorQuad, { ext_reg_info[reg_index * 4 + 0], @@ -409,7 +409,7 @@ static void RegisterPass(IR::Block& block) { stored_value, inst); } else { - DEBUG_ASSERT(A32::IsQuadExtReg(reg)); + assert(A32::IsQuadExtReg(reg)); do_ext_set(ExtValueType::VectorQuad, { ext_reg_info[reg_index * 4 + 0], @@ -1430,7 +1430,7 @@ static void VerificationPass(const IR::Block& block) { for (size_t i = 0; i < inst.NumArgs(); i++) { const IR::Type t1 = inst.GetArg(i).GetType(); const IR::Type t2 = IR::GetArgTypeOf(inst.GetOpcode(), i); - ASSERT(IR::AreTypesCompatible(t1, t2)); + assert(IR::AreTypesCompatible(t1, t2)); } } ankerl::unordered_dense::map actual_uses; @@ -1440,7 +1440,7 @@ static void VerificationPass(const IR::Block& block) { actual_uses[arg.GetInst()]++; } for (auto const& pair : actual_uses) - ASSERT(pair.first->UseCount() == pair.second); + assert(pair.first->UseCount() == pair.second); } void Optimize(IR::Block& block, const A32::UserConfig& conf, const Optimization::PolyfillOptions& polyfill_options) { diff --git a/src/dynarmic/src/dynarmic/ir/value.cpp b/src/dynarmic/src/dynarmic/ir/value.cpp index 7f0249b1ec..6e7c2bbed3 100644 --- a/src/dynarmic/src/dynarmic/ir/value.cpp +++ b/src/dynarmic/src/dynarmic/ir/value.cpp @@ -8,7 +8,7 @@ #include "dynarmic/ir/value.h" -#include "common/assert.h" +#include #include "dynarmic/mcl/bit.hpp" #include "dynarmic/ir/microinstruction.h" @@ -119,32 +119,32 @@ Type Value::GetType() const noexcept { } A32::Reg Value::GetA32RegRef() const { - ASSERT(type == Type::A32Reg); + assert(type == Type::A32Reg); return inner.imm_a32regref; } A32::ExtReg Value::GetA32ExtRegRef() const { - ASSERT(type == Type::A32ExtReg); + assert(type == Type::A32ExtReg); return inner.imm_a32extregref; } A64::Reg Value::GetA64RegRef() const { - ASSERT(type == Type::A64Reg); + assert(type == Type::A64Reg); return inner.imm_a64regref; } A64::Vec Value::GetA64VecRef() const { - ASSERT(type == Type::A64Vec); + assert(type == Type::A64Vec); return inner.imm_a64vecref; } Inst* Value::GetInst() const { - ASSERT(type == Type::Opaque); + assert(type == Type::Opaque); return inner.inst; } Inst* Value::GetInstRecursive() const { - ASSERT(type == Type::Opaque); + assert(type == Type::Opaque); if (IsIdentity()) return inner.inst->GetArg(0).GetInstRecursive(); return inner.inst; @@ -153,61 +153,61 @@ Inst* Value::GetInstRecursive() const { bool Value::GetU1() const { if (IsIdentity()) return inner.inst->GetArg(0).GetU1(); - ASSERT(type == Type::U1); + assert(type == Type::U1); return inner.imm_u1; } u8 Value::GetU8() const { if (IsIdentity()) return inner.inst->GetArg(0).GetU8(); - ASSERT(type == Type::U8); + assert(type == Type::U8); return inner.imm_u8; } u16 Value::GetU16() const { if (IsIdentity()) return inner.inst->GetArg(0).GetU16(); - ASSERT(type == Type::U16); + assert(type == Type::U16); return inner.imm_u16; } u32 Value::GetU32() const { if (IsIdentity()) return inner.inst->GetArg(0).GetU32(); - ASSERT(type == Type::U32); + assert(type == Type::U32); return inner.imm_u32; } u64 Value::GetU64() const { if (IsIdentity()) return inner.inst->GetArg(0).GetU64(); - ASSERT(type == Type::U64); + assert(type == Type::U64); return inner.imm_u64; } Value::CoprocessorInfo Value::GetCoprocInfo() const { if (IsIdentity()) return inner.inst->GetArg(0).GetCoprocInfo(); - ASSERT(type == Type::CoprocInfo); + assert(type == Type::CoprocInfo); return inner.imm_coproc; } Cond Value::GetCond() const { if (IsIdentity()) return inner.inst->GetArg(0).GetCond(); - ASSERT(type == Type::Cond); + assert(type == Type::Cond); return inner.imm_cond; } AccType Value::GetAccType() const { if (IsIdentity()) return inner.inst->GetArg(0).GetAccType(); - ASSERT(type == Type::AccType); + assert(type == Type::AccType); return inner.imm_acctype; } s64 Value::GetImmediateAsS64() const { - ASSERT(IsImmediate()); + assert(IsImmediate()); switch (GetType()) { case IR::Type::U1: return s64(GetU1()); @@ -225,7 +225,7 @@ s64 Value::GetImmediateAsS64() const { } u64 Value::GetImmediateAsU64() const { - ASSERT(IsImmediate()); + assert(IsImmediate()); switch (GetType()) { case IR::Type::U1: return u64(GetU1()); diff --git a/src/dynarmic/src/dynarmic/ir/value.h b/src/dynarmic/src/dynarmic/ir/value.h index 1fec942e2e..5f8d2e76ca 100644 --- a/src/dynarmic/src/dynarmic/ir/value.h +++ b/src/dynarmic/src/dynarmic/ir/value.h @@ -11,7 +11,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/ir/type.h" @@ -147,12 +147,12 @@ public: template> /* implicit */ TypedValue(const TypedValue& value) : Value(value) { - ASSERT((value.GetType() & type_) != Type::Void); + assert((value.GetType() & type_) != Type::Void); } explicit TypedValue(const Value& value) : Value(value) { - ASSERT((value.GetType() & type_) != Type::Void); + assert((value.GetType() & type_) != Type::Void); } explicit TypedValue(Inst* inst) diff --git a/src/dynarmic/src/dynarmic/mcl/bit.hpp b/src/dynarmic/src/dynarmic/mcl/bit.hpp index bbedffd8ae..c4ec4259b5 100644 --- a/src/dynarmic/src/dynarmic/mcl/bit.hpp +++ b/src/dynarmic/src/dynarmic/mcl/bit.hpp @@ -10,7 +10,7 @@ #include #include "common/common_types.h" -#include "common/assert.h" +#include namespace mcl { namespace detail { @@ -104,7 +104,7 @@ constexpr T ones() { /// Create a mask with `count` number of one bits. template constexpr T ones(size_t count) { - ASSERT(count <= bitsizeof && "count larger than bitsize of T"); + assert(count <= bitsizeof && "count larger than bitsize of T"); if (count == 0) { return 0; } @@ -124,9 +124,9 @@ constexpr T mask() { /// Create a mask of type T for bits [begin_bit, end_bit] inclusive. template constexpr T mask(size_t begin_bit, size_t end_bit) { - ASSERT(begin_bit <= end_bit && "invalid bit range (position of beginning bit cannot be greater than that of end bit)"); - ASSERT(begin_bit < bitsizeof && "begin_bit must be smaller than size of T"); - ASSERT(end_bit < bitsizeof && "end_bit must be smaller than size of T"); + assert(begin_bit <= end_bit && "invalid bit range (position of beginning bit cannot be greater than that of end bit)"); + assert(begin_bit < bitsizeof && "begin_bit must be smaller than size of T"); + assert(end_bit < bitsizeof && "end_bit must be smaller than size of T"); return ones(end_bit - begin_bit + 1) << begin_bit; } @@ -227,7 +227,7 @@ constexpr T sign_extend(T value) { /// Sign-extends a value that has bit_count bits to the full bitwidth of type T. template constexpr T sign_extend(size_t bit_count, T value) { - ASSERT(bit_count != 0 && "cannot sign-extend zero-sized value"); + assert(bit_count != 0 && "cannot sign-extend zero-sized value"); using S = std::make_signed_t; const size_t shift_amount = bitsizeof - bit_count; return T(S(value << shift_amount) >> shift_amount); @@ -257,8 +257,8 @@ constexpr T replicate_element(T value) { /// Replicate an element across a value of type T. template constexpr T replicate_element(size_t element_size, T value) { - ASSERT(element_size <= bitsizeof && "element_size is too large"); - ASSERT(bitsizeof % element_size == 0 && "bitsize of T not divisible by element_size"); + assert(element_size <= bitsizeof && "element_size is too large"); + assert(bitsizeof % element_size == 0 && "bitsize of T not divisible by element_size"); if (element_size == bitsizeof) return value; return replicate_element(element_size * 2, static_cast(value | (value << element_size))); diff --git a/src/dynarmic/src/dynarmic/mcl/intrusive_list.hpp b/src/dynarmic/src/dynarmic/mcl/intrusive_list.hpp index d8b87366a1..30b9961f71 100644 --- a/src/dynarmic/src/dynarmic/mcl/intrusive_list.hpp +++ b/src/dynarmic/src/dynarmic/mcl/intrusive_list.hpp @@ -9,7 +9,7 @@ #include #include #include -#include "common/assert.h" +#include namespace mcl { @@ -114,7 +114,7 @@ public: reference operator*() const { - DEBUG_ASSERT(!node->is_sentinel()); + assert(!node->is_sentinel()); return static_cast(*node); } pointer operator->() const @@ -215,7 +215,7 @@ public: */ void pop_front() { - DEBUG_ASSERT(!empty()); + assert(!empty()); erase(begin()); } @@ -225,7 +225,7 @@ public: */ void pop_back() { - DEBUG_ASSERT(!empty()); + assert(!empty()); erase(--end()); } @@ -235,7 +235,7 @@ public: */ pointer remove(iterator& it) { - DEBUG_ASSERT(it != end()); + assert(it != end()); pointer node = &*it++; @@ -301,7 +301,7 @@ public: */ reference front() { - DEBUG_ASSERT(!empty()); + assert(!empty()); return *begin(); } @@ -311,7 +311,7 @@ public: */ const_reference front() const { - DEBUG_ASSERT(!empty()); + assert(!empty()); return *begin(); } @@ -321,7 +321,7 @@ public: */ reference back() { - DEBUG_ASSERT(!empty()); + assert(!empty()); return *--end(); } @@ -331,7 +331,7 @@ public: */ const_reference back() const { - DEBUG_ASSERT(!empty()); + assert(!empty()); return *--end(); } diff --git a/src/dynarmic/tests/A32/fuzz_arm.cpp b/src/dynarmic/tests/A32/fuzz_arm.cpp index e2546de635..04e21be972 100644 --- a/src/dynarmic/tests/A32/fuzz_arm.cpp +++ b/src/dynarmic/tests/A32/fuzz_arm.cpp @@ -65,7 +65,7 @@ bool AnyLocationDescriptorForTerminalHas(IR::Terminal terminal, Fn fn) { } else if constexpr (std::is_same_v) { return AnyLocationDescriptorForTerminalHas(t.else_, fn); } else { - ASSERT(false && "Invalid terminal type"); + assert(false && "Invalid terminal type"); return false; } }, terminal); diff --git a/src/dynarmic/tests/A32/fuzz_thumb.cpp b/src/dynarmic/tests/A32/fuzz_thumb.cpp index 67a01daf9c..421752e075 100644 --- a/src/dynarmic/tests/A32/fuzz_thumb.cpp +++ b/src/dynarmic/tests/A32/fuzz_thumb.cpp @@ -76,7 +76,7 @@ public: inst = bits | (random & ~mask); } while (!is_valid(inst)); - ASSERT((inst & mask) == bits); + assert((inst & mask) == bits); return static_cast(inst); } @@ -89,7 +89,7 @@ public: inst = bits | (random & ~mask); } while (!is_valid(inst)); - ASSERT((inst & mask) == bits); + assert((inst & mask) == bits); return inst; } diff --git a/src/dynarmic/tests/A32/test_arm_instructions.cpp b/src/dynarmic/tests/A32/test_arm_instructions.cpp index 5a27cd499c..c7501130cc 100644 --- a/src/dynarmic/tests/A32/test_arm_instructions.cpp +++ b/src/dynarmic/tests/A32/test_arm_instructions.cpp @@ -44,7 +44,7 @@ TEST_CASE("arm: Opt Failure: Const folding in MostSignificantWord", "[arm][A32]" test_env.ticks_left = 6; CheckedRun([&]() { jit.Run(); }); - // If we don't trigger the GetCarryFromOp ASSERT, we're fine. + // If we don't trigger the GetCarryFromOp assert, we're fine. } TEST_CASE("arm: Unintended modification in SetCFlag", "[arm][A32]") { diff --git a/src/dynarmic/tests/A32/testenv.h b/src/dynarmic/tests/A32/testenv.h index bebc2566da..98a7a8128a 100644 --- a/src/dynarmic/tests/A32/testenv.h +++ b/src/dynarmic/tests/A32/testenv.h @@ -14,7 +14,7 @@ #include #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/interface/A32/a32.h" @@ -98,11 +98,11 @@ public: } void CallSVC(std::uint32_t swi) override { - UNREACHABLE(); //ASSERT(false && "CallSVC({})", swi); + UNREACHABLE(); //assert(false && "CallSVC({})", swi); } void ExceptionRaised(u32 pc, Dynarmic::A32::Exception /*exception*/) override { - UNREACHABLE(); //ASSERT(false && "ExceptionRaised({:08x}) code = {:08x}", pc, *MemoryReadCode(pc)); + UNREACHABLE(); //assert(false && "ExceptionRaised({:08x}) code = {:08x}", pc, *MemoryReadCode(pc)); } void AddTicks(std::uint64_t ticks) override { @@ -187,11 +187,11 @@ public: } void CallSVC(std::uint32_t swi) override { - UNREACHABLE(); //ASSERT(false && "CallSVC({})", swi); + UNREACHABLE(); //assert(false && "CallSVC({})", swi); } void ExceptionRaised(std::uint32_t pc, Dynarmic::A32::Exception) override { - UNREACHABLE(); //ASSERT(false && "ExceptionRaised({:016x})", pc); + UNREACHABLE(); //assert(false && "ExceptionRaised({:016x})", pc); } void AddTicks(std::uint64_t ticks) override { diff --git a/src/dynarmic/tests/A64/testenv.h b/src/dynarmic/tests/A64/testenv.h index c25790e1c9..5f9e184ca3 100644 --- a/src/dynarmic/tests/A64/testenv.h +++ b/src/dynarmic/tests/A64/testenv.h @@ -9,7 +9,7 @@ #pragma once #include -#include "common/assert.h" +#include #include "common/common_types.h" #include "dynarmic/interface/A64/a64.h" @@ -106,11 +106,11 @@ public: } void CallSVC(std::uint32_t swi) override { - UNREACHABLE(); //ASSERT(false && "CallSVC({})", swi); + UNREACHABLE(); //assert(false && "CallSVC({})", swi); } void ExceptionRaised(u64 pc, Dynarmic::A64::Exception /*exception*/) override { - UNREACHABLE(); //ASSERT(false && "ExceptionRaised({:016x})", pc); + UNREACHABLE(); //assert(false && "ExceptionRaised({:016x})", pc); } void AddTicks(std::uint64_t ticks) override { @@ -205,11 +205,11 @@ public: } void CallSVC(std::uint32_t swi) override { - UNREACHABLE(); //ASSERT(false && "CallSVC({})", swi); + UNREACHABLE(); //assert(false && "CallSVC({})", swi); } void ExceptionRaised(u64 pc, Dynarmic::A64::Exception) override { - UNREACHABLE(); //ASSERT(false && "ExceptionRaised({:016x})", pc); + UNREACHABLE(); //assert(false && "ExceptionRaised({:016x})", pc); } void AddTicks(std::uint64_t ticks) override { diff --git a/src/dynarmic/tests/decoder_tests.cpp b/src/dynarmic/tests/decoder_tests.cpp index 3da578830a..4148536b46 100644 --- a/src/dynarmic/tests/decoder_tests.cpp +++ b/src/dynarmic/tests/decoder_tests.cpp @@ -11,7 +11,7 @@ #include #include -#include "common/assert.h" +#include #include "dynarmic/frontend/A32/decoder/asimd.h" #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" @@ -24,7 +24,7 @@ TEST_CASE("ASIMD Decoder: Ensure table order correctness", "[decode][a32][.]") { const auto table = A32::GetASIMDDecodeTable(); const auto get_ir = [](const A32::ASIMDMatcher& matcher, u32 instruction) { - ASSERT(matcher.Matches(instruction)); + assert(matcher.Matches(instruction)); const A32::LocationDescriptor location{0, {}, {}}; IR::Block block{location}; diff --git a/src/dynarmic/tests/fuzz_util.cpp b/src/dynarmic/tests/fuzz_util.cpp index 80fdd749ca..f671e44208 100644 --- a/src/dynarmic/tests/fuzz_util.cpp +++ b/src/dynarmic/tests/fuzz_util.cpp @@ -12,7 +12,7 @@ #include #include -#include "common/assert.h" +#include #include "dynarmic/tests/rand_int.h" #include "dynarmic/common/fp/fpcr.h" @@ -40,7 +40,7 @@ u32 RandomFpcr() { InstructionGenerator::InstructionGenerator(const char* format) { const size_t format_len = std::strlen(format); - ASSERT(format_len == 16 || format_len == 32); + assert(format_len == 16 || format_len == 32); if (format_len == 16) { // Begin with 16 zeros diff --git a/src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp b/src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp index c0e1e13d9b..8c546683bb 100644 --- a/src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp +++ b/src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp @@ -10,10 +10,10 @@ #include #include "dynarmic/mcl/bit.hpp" #include "dynarmic/tests/unicorn_emu/a32_unicorn.h" -#include "common/assert.h" +#include #include "dynarmic/tests/A32/testenv.h" -#define CHECKED(expr) do if ((expr)) ASSERT(false && "Call " #expr " failed with error\n"); while (0) +#define CHECKED(expr) do if ((expr)) assert(false && "Call " #expr " failed with error\n"); while (0) constexpr u32 BEGIN_ADDRESS = 0; constexpr u32 END_ADDRESS = ~u32(0); diff --git a/src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp b/src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp index c9a194d50a..eb4b628693 100644 --- a/src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp +++ b/src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp @@ -8,9 +8,9 @@ #include #include "dynarmic/tests/unicorn_emu/a64_unicorn.h" -#include "common/assert.h" +#include -#define CHECKED(expr) do if ((expr)) ASSERT(false && "Call " #expr " failed with error\n"); while (0) +#define CHECKED(expr) do if ((expr)) assert(false && "Call " #expr " failed with error\n"); while (0) constexpr u64 BEGIN_ADDRESS = 0; constexpr u64 END_ADDRESS = ~u64(0);