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https://git.eden-emu.dev/eden-emu/eden
synced 2026-10-20 18:59:26 +02:00
Address son sync issues
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parent
165a1d1da1
commit
9d620bba88
5 changed files with 26 additions and 18 deletions
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@ -26,6 +26,15 @@ namespace Vulkan {
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namespace {
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namespace {
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constexpr u32 COMPACT_VERTEX_BINDINGS = 8;
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constexpr u32 COMPACT_VERTEX_BINDINGS = 8;
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constexpr VkMemoryBarrier2 HOST_READ_BARRIER{
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.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER_2,
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.pNext = nullptr,
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.srcStageMask = VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT,
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.srcAccessMask = VK_ACCESS_2_MEMORY_WRITE_BIT,
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.dstStageMask = VK_PIPELINE_STAGE_2_HOST_BIT,
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.dstAccessMask = VK_ACCESS_2_HOST_READ_BIT,
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};
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template <u32 N>
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template <u32 N>
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struct VertexBindings {
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struct VertexBindings {
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std::array<VkBuffer, N> buffers;
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std::array<VkBuffer, N> buffers;
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@ -527,9 +536,16 @@ bool BufferCacheRuntime::CanReorderUpload(const Buffer& buffer,
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std::span<const u8> BufferCacheRuntime::DirectDownloadSpan(Buffer& buffer) {
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std::span<const u8> BufferCacheRuntime::DirectDownloadSpan(Buffer& buffer) {
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const std::span<u8> mapping = buffer.CoherentMapping();
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const std::span<u8> mapping = buffer.CoherentMapping();
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if (!mapping.empty()) {
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if (mapping.empty()) {
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scheduler.Wait((std::max)(buffer.getWriteTick(), buffer.LastUploadTick()));
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return mapping;
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}
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}
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if ((std::max)(buffer.getWriteTick(), buffer.LastUploadTick()) > host_read_tick) {
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scheduler.RequestOutsideRenderPassOperationContext();
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scheduler.Record(
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[](vk::CommandBuffer cmdbuf) { cmdbuf.PipelineBarrier(HOST_READ_BARRIER); });
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host_read_tick = scheduler.CurrentTick();
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}
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scheduler.Wait(host_read_tick);
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return mapping;
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return mapping;
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}
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}
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@ -291,6 +291,7 @@ private:
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VkMemoryBarrier2 read_barrier;
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VkMemoryBarrier2 read_barrier;
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VkMemoryBarrier2 write_barrier;
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VkMemoryBarrier2 write_barrier;
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u64 host_read_tick = 0;
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bool limit_dynamic_storage_buffers = false;
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bool limit_dynamic_storage_buffers = false;
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u32 max_dynamic_storage_buffers = (std::numeric_limits<u32>::max)();
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u32 max_dynamic_storage_buffers = (std::numeric_limits<u32>::max)();
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@ -898,7 +898,9 @@ void RasterizerVulkan::TiledCacheBarrier() {
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}
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}
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void RasterizerVulkan::FlushCommands() {
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void RasterizerVulkan::FlushCommands() {
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if (draw_counter == 0) {
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if (draw_tick != scheduler.CurrentTick() ||
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(scheduler.IsRenderPassActive() &&
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!maxwell3d->dirty.flags[VideoCommon::Dirty::RenderTargets])) {
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return;
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return;
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}
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}
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draw_counter = 0;
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draw_counter = 0;
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@ -1008,11 +1010,10 @@ void RasterizerVulkan::FlushWork() {
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maxwell3d->dirty.flags[VideoCommon::Dirty::RenderTargets])) {
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maxwell3d->dirty.flags[VideoCommon::Dirty::RenderTargets])) {
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scheduler.Flush();
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scheduler.Flush();
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draw_counter = 0;
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draw_counter = 0;
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return;
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} else if ((draw_counter & CHECK_MASK) == CHECK_MASK && !scheduler.IsRenderPassActive()) {
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}
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if ((draw_counter & CHECK_MASK) == CHECK_MASK && !scheduler.IsRenderPassActive()) {
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scheduler.DispatchWork();
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scheduler.DispatchWork();
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}
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}
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draw_tick = scheduler.CurrentTick();
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}
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}
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AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_, TextureCache& texture_cache_,
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AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_, TextureCache& texture_cache_,
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@ -227,6 +227,7 @@ private:
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boost::container::static_vector<VkSampler, MAX_TEXTURES> sampler_handles;
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boost::container::static_vector<VkSampler, MAX_TEXTURES> sampler_handles;
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u32 draw_counter = 0;
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u32 draw_counter = 0;
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u64 draw_tick = 0;
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Tegra::DepthFormat depth_bias_zeta_format{};
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Tegra::DepthFormat depth_bias_zeta_format{};
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std::array<u32, Tegra::Engines::Maxwell3D::Regs::NumVertexArrays> vertex_input_strides{};
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std::array<u32, Tegra::Engines::Maxwell3D::Regs::NumVertexArrays> vertex_input_strides{};
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u32 vertex_input_attributes{};
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u32 vertex_input_attributes{};
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@ -32,15 +32,6 @@ namespace Vulkan {
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namespace {
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namespace {
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constexpr size_t DEPTH_VIEW = 8;
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constexpr size_t DEPTH_VIEW = 8;
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constexpr VkMemoryBarrier2 HOST_READ_BARRIER{
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.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER_2,
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.pNext = nullptr,
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.srcStageMask = VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT,
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.srcAccessMask = VK_ACCESS_2_MEMORY_WRITE_BIT,
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.dstStageMask = VK_PIPELINE_STAGE_2_HOST_BIT,
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.dstAccessMask = VK_ACCESS_2_HOST_READ_BIT,
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};
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struct BeginRenderingCommand {
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struct BeginRenderingCommand {
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void operator()(vk::CommandBuffer cmdbuf, vk::CommandBuffer) const {
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void operator()(vk::CommandBuffer cmdbuf, vk::CommandBuffer) const {
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BeginRendering(cmdbuf, attachments);
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BeginRendering(cmdbuf, attachments);
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@ -478,6 +469,7 @@ void Scheduler::AllocateWorkerCommandBuffer() {
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}
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}
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u64 Scheduler::SubmitExecution(VkSemaphore signal_semaphore, VkSemaphore wait_semaphore) {
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u64 Scheduler::SubmitExecution(VkSemaphore signal_semaphore, VkSemaphore wait_semaphore) {
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master_semaphore->Refresh();
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EndPendingOperations();
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EndPendingOperations();
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InvalidateState();
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InvalidateState();
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@ -486,9 +478,6 @@ u64 Scheduler::SubmitExecution(VkSemaphore signal_semaphore, VkSemaphore wait_se
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this](vk::CommandBuffer cmdbuf, vk::CommandBuffer upload_cmdbuf) {
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this](vk::CommandBuffer cmdbuf, vk::CommandBuffer upload_cmdbuf) {
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upload_cmdbuf.PipelineBarrier(upload_write_barrier);
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upload_cmdbuf.PipelineBarrier(upload_write_barrier);
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upload_cmdbuf.End();
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upload_cmdbuf.End();
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if (device.IsUMA()) {
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cmdbuf.PipelineBarrier(HOST_READ_BARRIER);
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}
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cmdbuf.End();
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cmdbuf.End();
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if (on_submit) {
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if (on_submit) {
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