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[video_core/vic] remove handrolled vector implementation that also uses software prefetching(!!!!); don't try to outsmart compiler - also remove template spam (#2856)
Also removes sse2neon :) Software prefetching SUCKS and it's evil don't do it Signed-off-by: lizzie <lizzie@eden-emu.dev> Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/2856 Reviewed-by: crueter <crueter@eden-emu.dev> Reviewed-by: MaranBr <maranbr@eden-emu.dev> Reviewed-by: Caio Oliveira <caiooliveirafarias0@gmail.com> Co-authored-by: lizzie <lizzie@eden-emu.dev> Co-committed-by: lizzie <lizzie@eden-emu.dev>
This commit is contained in:
lizzie
crueter
parent
83c162d80d
commit
5c6aaa7eb1
8 changed files with 167 additions and 981 deletions
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@ -1,129 +0,0 @@
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From d765ebed3598ddfd7167fc546474626ac5ef9498 Mon Sep 17 00:00:00 2001
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From: Anthony Roberts <anthony.roberts@linaro.org>
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Date: Fri, 2 Aug 2024 16:55:57 +0100
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Subject: [PATCH] Add support for clang-cl on Windows (#633)
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This commit adds support for clang-cl (clang, pretending to be MSVC) to
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SSE2NEON on Windows ARM64 platforms. This change is part of some Blender
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work, as using clang-cl provides a ~20-40% speedup compared to MSVC.
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Compiled with the following command line (via a VS2022 Native ARM64 Tools
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CMD window):
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msbuild sse2neon.vcxproj /p:Configuration=Release /p:CLToolExe=clang-cl.exe
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/p:CLToolPath="C:\Program Files\LLVM\bin\"
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Known failures in test suite:
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Test mm_cvttpd_epi32
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Test rdtsc
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Co-authored-by: Anthony Roberts <anthony.roberts@linaro.org>
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---
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sse2neon.h | 22 +++++++++++-----------
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1 file changed, 11 insertions(+), 11 deletions(-)
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diff --git a/sse2neon.h b/sse2neon.h
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index 56254b5..76cf8e3 100644
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--- a/sse2neon.h
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+++ b/sse2neon.h
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@@ -180,7 +180,7 @@
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}
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/* Compiler barrier */
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-#if defined(_MSC_VER)
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+#if defined(_MSC_VER) && !defined(__clang__)
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#define SSE2NEON_BARRIER() _ReadWriteBarrier()
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#else
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#define SSE2NEON_BARRIER() \
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@@ -856,7 +856,7 @@ FORCE_INLINE uint64x2_t _sse2neon_vmull_p64(uint64x1_t _a, uint64x1_t _b)
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{
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poly64_t a = vget_lane_p64(vreinterpret_p64_u64(_a), 0);
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poly64_t b = vget_lane_p64(vreinterpret_p64_u64(_b), 0);
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-#if defined(_MSC_VER)
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+#if defined(_MSC_VER) && !defined(__clang__)
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__n64 a1 = {a}, b1 = {b};
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return vreinterpretq_u64_p128(vmull_p64(a1, b1));
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#else
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@@ -1767,7 +1767,7 @@ FORCE_INLINE void _mm_free(void *addr)
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FORCE_INLINE uint64_t _sse2neon_get_fpcr(void)
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{
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uint64_t value;
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-#if defined(_MSC_VER)
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+#if defined(_MSC_VER) && !defined(__clang__)
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value = _ReadStatusReg(ARM64_FPCR);
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#else
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__asm__ __volatile__("mrs %0, FPCR" : "=r"(value)); /* read */
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@@ -1777,7 +1777,7 @@ FORCE_INLINE uint64_t _sse2neon_get_fpcr(void)
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FORCE_INLINE void _sse2neon_set_fpcr(uint64_t value)
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{
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-#if defined(_MSC_VER)
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+#if defined(_MSC_VER) && !defined(__clang__)
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_WriteStatusReg(ARM64_FPCR, value);
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#else
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__asm__ __volatile__("msr FPCR, %0" ::"r"(value)); /* write */
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@@ -2246,7 +2246,7 @@ FORCE_INLINE __m128 _mm_or_ps(__m128 a, __m128 b)
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FORCE_INLINE void _mm_prefetch(char const *p, int i)
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{
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(void) i;
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-#if defined(_MSC_VER)
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+#if defined(_MSC_VER) && !defined(__clang__)
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switch (i) {
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case _MM_HINT_NTA:
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__prefetch2(p, 1);
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@@ -4817,7 +4817,7 @@ FORCE_INLINE __m128i _mm_packus_epi16(const __m128i a, const __m128i b)
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_pause
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FORCE_INLINE void _mm_pause(void)
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{
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-#if defined(_MSC_VER)
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+#if defined(_MSC_VER) && !defined(__clang__)
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__isb(_ARM64_BARRIER_SY);
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#else
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__asm__ __volatile__("isb\n");
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@@ -5713,7 +5713,7 @@ FORCE_INLINE __m128d _mm_undefined_pd(void)
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#pragma GCC diagnostic ignored "-Wuninitialized"
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#endif
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__m128d a;
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-#if defined(_MSC_VER)
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+#if defined(_MSC_VER) && !defined(__clang__)
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a = _mm_setzero_pd();
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#endif
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return a;
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@@ -8127,7 +8127,7 @@ FORCE_INLINE int _sse2neon_sido_negative(int res, int lb, int imm8, int bound)
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FORCE_INLINE int _sse2neon_clz(unsigned int x)
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{
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-#ifdef _MSC_VER
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+#if defined(_MSC_VER) && !defined(__clang__)
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unsigned long cnt = 0;
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if (_BitScanReverse(&cnt, x))
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return 31 - cnt;
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@@ -8139,7 +8139,7 @@ FORCE_INLINE int _sse2neon_clz(unsigned int x)
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FORCE_INLINE int _sse2neon_ctz(unsigned int x)
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{
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-#ifdef _MSC_VER
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+#if defined(_MSC_VER) && !defined(__clang__)
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unsigned long cnt = 0;
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if (_BitScanForward(&cnt, x))
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return cnt;
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@@ -9055,7 +9055,7 @@ FORCE_INLINE __m128i _mm_aeskeygenassist_si128(__m128i a, const int rcon)
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// AESE does ShiftRows and SubBytes on A
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uint8x16_t u8 = vaeseq_u8(vreinterpretq_u8_m128i(a), vdupq_n_u8(0));
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-#ifndef _MSC_VER
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+#if !defined(_MSC_VER) || defined(__clang__)
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uint8x16_t dest = {
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// Undo ShiftRows step from AESE and extract X1 and X3
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u8[0x4], u8[0x1], u8[0xE], u8[0xB], // SubBytes(X1)
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@@ -9242,7 +9242,7 @@ FORCE_INLINE uint64_t _rdtsc(void)
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* bits wide and it is attributed with the flag 'cap_user_time_short'
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* is true.
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*/
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-#if defined(_MSC_VER)
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+#if defined(_MSC_VER) && !defined(__clang__)
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val = _ReadStatusReg(ARM64_SYSREG(3, 3, 14, 0, 2));
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#else
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__asm__ __volatile__("mrs %0, cntvct_el0" : "=r"(val));
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--
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2.48.1
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