[dynarmic] jit fix branch v2 (#203)

Co-authored-by: lizzie <lizzie@eden-emu.dev>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/203
Reviewed-by: Shinmegumi <shinmegumi@eden-emu.dev>

src/dynarmic/tests/A64/fibonacci.cpp

@@ -8,7 +8,7 @@
 
 #include <array>
 #include <exception>
-#include <map>
+#include <unordered_map>
 
 #include <catch2/catch_test_macros.hpp>
 #include "dynarmic/common/common_types.h"
@@ -23,7 +23,7 @@ namespace {
 class MyEnvironment final : public A64::UserCallbacks {
 public:
     u64 ticks_left = 0;
-    std::map<u64, u8> memory{};
+    std::unordered_map<u64, u8> memory{};
 
     u8 MemoryRead8(u64 vaddr) override {
         return memory[vaddr];

src/dynarmic/tests/A64/fp_min_max.cpp

@@ -87,7 +87,7 @@ void run_test(u32 instruction, Fn fn) {
             jit.SetPC(0);
 
             env.ticks_left = 2;
-            jit.Run();
+            CheckedRun([&]() { jit.Run(); });
 
             REQUIRE(jit.GetVector(0)[0] == fn(test_case));
 
@@ -97,7 +97,7 @@ void run_test(u32 instruction, Fn fn) {
             jit.SetPC(0);
 
             env.ticks_left = 2;
-            jit.Run();
+            CheckedRun([&]() { jit.Run(); });
 
             REQUIRE(jit.GetVector(0)[0] == fn(test_case));
 
@@ -109,7 +109,7 @@ void run_test(u32 instruction, Fn fn) {
             jit.SetPC(0);
 
             env.ticks_left = 2;
-            jit.Run();
+            CheckedRun([&]() { jit.Run(); });
 
             REQUIRE(jit.GetVector(0)[0] == force_default_nan(fn(test_case)));
 
@@ -119,7 +119,7 @@ void run_test(u32 instruction, Fn fn) {
             jit.SetPC(0);
 
             env.ticks_left = 2;
-            jit.Run();
+            CheckedRun([&]() { jit.Run(); });
 
             REQUIRE(jit.GetVector(0)[0] == force_default_nan(fn(test_case)));
         }
@@ -136,7 +136,7 @@ void run_test(u32 instruction, Fn fn) {
             jit.SetPC(0);
 
             env.ticks_left = 2;
-            jit.Run();
+            CheckedRun([&]() { jit.Run(); });
 
             REQUIRE(jit.GetVector(0)[0] == fn(test_case));
 
@@ -148,7 +148,7 @@ void run_test(u32 instruction, Fn fn) {
             jit.SetPC(0);
 
             env.ticks_left = 2;
-            jit.Run();
+            CheckedRun([&]() { jit.Run(); });
 
             REQUIRE(jit.GetVector(0)[0] == force_default_nan(fn(test_case)));
         }

src/dynarmic/tests/A64/fuzz_with_unicorn.cpp

@@ -91,6 +91,9 @@ static u32 GenRandomInst(u64 pc, bool is_last_inst) {
             "MSR_reg",
             "MSR_imm",
             "MRS",
+            // Does not need test
+            "SVC",
+            "BRK"
         };
 
         for (const auto& [fn, bitstring] : list) {
@@ -198,9 +201,9 @@ static void RunTestInstance(Dynarmic::A64::Jit& jit, A64Unicorn& uni, A64TestEnv
     uni.ClearPageCache();
 
     jit_env.ticks_left = instructions.size();
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
 
-    uni_env.ticks_left = instructions.size();
+    uni_env.ticks_left = instructions.size() * 4;
     uni.Run();
 
     SCOPE_FAIL {
@@ -296,7 +299,7 @@ static void RunTestInstance(Dynarmic::A64::Jit& jit, A64Unicorn& uni, A64TestEnv
         return;
     }
 
-    REQUIRE(uni.GetPC() == jit.GetPC());
+    REQUIRE(uni.GetPC() + 4 == jit.GetPC());
     REQUIRE(uni.GetRegisters() == jit.GetRegisters());
     REQUIRE(uni.GetVectors() == jit.GetVectors());
     REQUIRE(uni.GetSP() == jit.GetSP());
@@ -306,7 +309,7 @@ static void RunTestInstance(Dynarmic::A64::Jit& jit, A64Unicorn& uni, A64TestEnv
     REQUIRE(FP::FPSR{uni.GetFpsr()}.QC() == FP::FPSR{jit.GetFpsr()}.QC());
 }
 
-TEST_CASE("A64: Single random instruction", "[a64]") {
+TEST_CASE("A64: Single random instruction", "[a64][unicorn]") {
     A64TestEnv jit_env{};
     A64TestEnv uni_env{};
 
@@ -333,7 +336,7 @@ TEST_CASE("A64: Single random instruction", "[a64]") {
     }
 }
 
-TEST_CASE("A64: Floating point instructions", "[a64]") {
+TEST_CASE("A64: Floating point instructions", "[a64][unicorn]") {
     A64TestEnv jit_env{};
     A64TestEnv uni_env{};
 
@@ -458,7 +461,7 @@ TEST_CASE("A64: Floating point instructions", "[a64]") {
     }
 }
 
-TEST_CASE("A64: Small random block", "[a64]") {
+TEST_CASE("A64: Small random block", "[a64][unicorn]") {
     A64TestEnv jit_env{};
     A64TestEnv uni_env{};
 
@@ -493,7 +496,7 @@ TEST_CASE("A64: Small random block", "[a64]") {
     }
 }
 
-TEST_CASE("A64: Large random block", "[a64]") {
+TEST_CASE("A64: Large random block", "[a64][unicorn]") {
     A64TestEnv jit_env{};
     A64TestEnv uni_env{};
 

src/dynarmic/tests/A64/misaligned_page_table.cpp

@@ -24,7 +24,7 @@ TEST_CASE("misaligned load/store do not use page_table when detect_misaligned_ac
     jit.SetRegister(0, 0x000000000b0afff8);
 
     env.ticks_left = 2;
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
 
     // If we don't crash we're fine.
 }

src/dynarmic/tests/A64/test_invalidation.cpp

@@ -27,38 +27,38 @@ TEST_CASE("ensure fast dispatch entry is cleared even when a block does not have
 
     jit.SetPC(100);
     env.ticks_left = 4;
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
     REQUIRE(jit.GetRegister(0) == 42);
 
     jit.SetPC(100);
     env.ticks_left = 4;
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
     REQUIRE(jit.GetRegister(0) == 42);
 
     jit.InvalidateCacheRange(108, 4);
 
     jit.SetPC(100);
     env.ticks_left = 4;
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
     REQUIRE(jit.GetRegister(0) == 42);
 
     env.code_mem[2] = 0xd28008a0;  // MOV X0, 69
 
     jit.SetPC(100);
     env.ticks_left = 4;
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
     REQUIRE(jit.GetRegister(0) == 42);
 
     jit.InvalidateCacheRange(108, 4);
 
     jit.SetPC(100);
     env.ticks_left = 4;
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
     REQUIRE(jit.GetRegister(0) == 69);
 
     jit.SetPC(100);
     env.ticks_left = 4;
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
     REQUIRE(jit.GetRegister(0) == 69);
 }
 
@@ -77,37 +77,37 @@ TEST_CASE("ensure fast dispatch entry is cleared even when a block does not have
 
     jit.SetPC(0);
     env.ticks_left = 4;
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
     REQUIRE(jit.GetRegister(0) == 42);
 
     jit.SetPC(0);
     env.ticks_left = 4;
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
     REQUIRE(jit.GetRegister(0) == 42);
 
     jit.InvalidateCacheRange(8, 4);
 
     jit.SetPC(0);
     env.ticks_left = 4;
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
     REQUIRE(jit.GetRegister(0) == 42);
 
     env.code_mem[2] = 0xd28008a0;  // MOV X0, 69
 
     jit.SetPC(0);
     env.ticks_left = 4;
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
     REQUIRE(jit.GetRegister(0) == 42);
 
     jit.InvalidateCacheRange(8, 4);
 
     jit.SetPC(0);
     env.ticks_left = 4;
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
     REQUIRE(jit.GetRegister(0) == 69);
 
     jit.SetPC(0);
     env.ticks_left = 4;
-    jit.Run();
+    CheckedRun([&]() { jit.Run(); });
     REQUIRE(jit.GetRegister(0) == 69);
 }

src/dynarmic/tests/A64/testenv.h

@@ -8,13 +8,11 @@
 
 #pragma once
 
-#include <array>
-#include <map>
-
+#include <unordered_map>
 #include "dynarmic/common/assert.h"
 #include "dynarmic/common/common_types.h"
-
 #include "dynarmic/interface/A64/a64.h"
+#include "../native/testenv.h"
 
 using Vector = Dynarmic::A64::Vector;
 
@@ -26,7 +24,7 @@ public:
     u64 code_mem_start_address = 0;
     std::vector<u32> code_mem;
 
-    std::map<u64, u8> modified_memory;
+    std::unordered_map<u64, u8> modified_memory;
     std::vector<std::string> interrupts;
 
     bool IsInCodeMem(u64 vaddr) const {
@@ -133,9 +131,9 @@ class A64FastmemTestEnv final : public Dynarmic::A64::UserCallbacks {
 public:
     u64 ticks_left = 0;
     char* backing_memory = nullptr;
+    bool ignore_invalid_insn = false;
 
-    explicit A64FastmemTestEnv(char* addr)
-            : backing_memory(addr) {}
+    explicit A64FastmemTestEnv(char* addr) : backing_memory(addr) {}
 
     template<typename T>
     T read(u64 vaddr) {
@@ -205,7 +203,7 @@ public:
         return true;
     }
 
-    void InterpreterFallback(u64 pc, size_t num_instructions) override { ASSERT_MSG(false, "InterpreterFallback({:016x}, {})", pc, num_instructions); }
+    void InterpreterFallback(u64 pc, size_t num_instructions) override { ASSERT_MSG(ignore_invalid_insn, "InterpreterFallback({:016x}, {})", pc, num_instructions); }
 
     void CallSVC(std::uint32_t swi) override { ASSERT_MSG(false, "CallSVC({})", swi); }
 

src/dynarmic/tests/A64/verify_unicorn.cpp

@@ -13,7 +13,7 @@
 
 using namespace Dynarmic;
 
-TEST_CASE("Unicorn: Sanity test", "[a64]") {
+TEST_CASE("Unicorn: Sanity test", "[a64][unicorn]") {
     A64TestEnv env;
 
     env.code_mem.emplace_back(0x8b020020);  // ADD X0, X1, X2
@@ -39,7 +39,7 @@ TEST_CASE("Unicorn: Sanity test", "[a64]") {
     REQUIRE(unicorn.GetPC() == 4);
 }
 
-TEST_CASE("Unicorn: Ensure 0xFFFF'FFFF'FFFF'FFFF is readable", "[a64]") {
+TEST_CASE("Unicorn: Ensure 0xFFFF'FFFF'FFFF'FFFF is readable", "[a64][unicorn]") {
     A64TestEnv env;
 
     env.code_mem.emplace_back(0x385fed99);  // LDRB W25, [X12, #0xfffffffffffffffe]!
@@ -59,7 +59,7 @@ TEST_CASE("Unicorn: Ensure 0xFFFF'FFFF'FFFF'FFFF is readable", "[a64]") {
     REQUIRE(unicorn.GetPC() == 4);
 }
 
-TEST_CASE("Unicorn: Ensure is able to read across page boundaries", "[a64]") {
+TEST_CASE("Unicorn: Ensure is able to read across page boundaries", "[a64][unicorn]") {
     A64TestEnv env;
 
     env.code_mem.emplace_back(0xb85f93d9);  // LDUR W25, [X30, #0xfffffffffffffff9]