Plexi09/eden-miror
1
0
Fork 0
mirror of https://git.eden-emu.dev/eden-emu/eden synced 2026-10-28 21:00:54 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

extra fixups

Browse source
This commit is contained in:
lizzie 2026-05-01 00:04:30 +00:00
parent d930ff52e1
commit 0e0b2f4895
7 changed files with 35 additions and 40 deletions
Download patch file Download diff file Expand all files Collapse all files

7
src/video_core/control/channel_state_cache.cpp
View file

@ -6,8 +6,11 @@
namespace VideoCommon {
ChannelInfo::ChannelInfo(Tegra::Control::ChannelState& channel_state)
: maxwell3d{*channel_state.maxwell_3d}, kepler_compute{*channel_state.kepler_compute},
gpu_memory{*channel_state.memory_manager}, program_id{channel_state.program_id} {}
: maxwell3d{channel_state.payload->maxwell_3d}
, kepler_compute{channel_state.payload->kepler_compute}
, gpu_memory{*channel_state.memory_manager}
, program_id{channel_state.program_id}
{}
template class VideoCommon::ChannelSetupCaches<VideoCommon::ChannelInfo>;

2
src/video_core/control/channel_state_cache.inc
View file

@ -41,7 +41,7 @@ void ChannelSetupCaches<P>::CreateChannel(struct Tegra::Control::ChannelState& c
AddressSpaceRef new_gpu_mem_ref{
.ref_count = 1,
.storage_id = address_spaces.size(),
.gpu_memory = channel.memory_manager.get(),
.gpu_memory = channel.memory_manager,
};
address_spaces.emplace(channel.memory_manager->GetID(), new_gpu_mem_ref);
OnGPUASRegister(channel.memory_manager->GetID());

9
src/video_core/control/scheduler.cpp
View file

@ -12,11 +12,8 @@
#include "video_core/gpu.h"
namespace Tegra::Control {
Scheduler::Scheduler(GPU& gpu_) : gpu{gpu_} {}
Scheduler::~Scheduler() = default;
void Scheduler::Push(s32 channel, CommandList&& entries) {
void Scheduler::Push(GPU& gpu, s32 channel, CommandList&& entries) {
std::shared_ptr<ChannelState> channel_state;
{
std::unique_lock lk(scheduling_guard);
@ -27,8 +24,8 @@ void Scheduler::Push(s32 channel, CommandList&& entries) {
}
// Process commands outside the lock to reduce contention.
// Multiple channels can prepare their commands in parallel.
channel_state->dma_pusher->Push(std::move(entries));
channel_state->dma_pusher->DispatchCalls();
channel_state->payload->dma_pusher.Push(std::move(entries));
channel_state->payload->dma_pusher.DispatchCalls();
}
void Scheduler::DeclareChannel(std::shared_ptr<ChannelState> new_channel) {

6
src/video_core/control/scheduler.h
View file

@ -22,17 +22,13 @@ struct ChannelState;
class Scheduler {
public:
explicit Scheduler(GPU& gpu_);
~Scheduler();
void Push(s32 channel, CommandList&& entries);
void Push(GPU& gpu, s32 channel, CommandList&& entries);
void DeclareChannel(std::shared_ptr<ChannelState> new_channel);
private:
ankerl::unordered_dense::map<s32, std::shared_ptr<ChannelState>> channels;
std::mutex scheduling_guard;
GPU& gpu;
};
} // namespace Control